ee365 adv. digital circuit design clarkson university lecture #7 intro to msi plds and decoders
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EE365Adv. Digital Circuit Design
Clarkson University
Lecture #7
Intro to MSI
PLDs and Decoders
Topics
• MSI Intro
• PLDs
• Decoders
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Role of MSI Components in Logic Design
• Gates are the fundamental building blocks of logic - the “atoms”.
• Medium Scale Integrated (MSI) components are the “molecules” - the commonly occurring functions.
• MSI components form the building blocks for much more complex functions .
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MSI vs. Gate Level Design• Functions more complex - more inputs and/or
outputs.• Find a good, feasible design, not necessarily
optimal.• Not restricted to two-level logic.• Trade-off propagation delay with simplicity of
design.• Keep IC count low (usually ignore gate count).
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MSI vs. Gate Level Design
• Look for designs which are scalable - easily expanded to handle more inputs.
• Look for designs which are hierarchical - built upon already designed functions.
• No automated, general design algorithm - must be creative.
• Same principles apply to custom VLSI or ASIC design.
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Programmable Logic Arrays (PLAs)
• Any combinational logic function can be realized as a sum of products.
• Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.– n inputs
• AND gates have 2n inputs -- true and complement of each variable.
– m outputs, driven by large OR gates• Each AND gate is programmably connected to each output’s
OR gate.
– p AND gates (p<<2n)
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Example: 4x3 PLA, 6 product terms
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Compact representation
• Actually, closer to physical layout (“wired logic”).
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Some product terms
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PLA Electrical Design
• See Section 5.3.5 -- wired-AND logic
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Programmable Array Logic (PALs)
• How beneficial is product sharing?– Not enough to justify the extra AND array
• PALs ==> fixed OR array– Each AND gate is permanently connected to a
certain OR gate.
• Example: PAL16L8
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• 10 primary inputs• 8 outputs, with 7 ANDs
per output• 1 AND for 3-state enable• 6 outputs available as
inputs– more inputs, at expense of
outputs– two-pass logic, helper
terms
• Note inversion on outputs– output is complement of
sum-of-products– newer PALs have
selectable inversion
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Designing with PALs
• Compare number of inputs and outputs of the problem with available resources in the PAL.
• Write equations for each output using ABEL.• Compile the ABEL program, determine
whether minimimized equations fit in the available AND terms.
• If no fit, try modifying equations or providing “helper” terms.
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Decoders• General decoder structure
• Typically n inputs, 2n outputs– 2-to-4, 3-to-8, 4-to-16, etc.
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Binary 2-to-4 decoder
Note “x” (don’t care) notation.
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2-to-4-decoder logic diagram
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MSI 2-to-4 decoder
• Input buffering (less load)• NAND gates (faster)
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Decoder Symbol
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Complete 74x139 Decoder
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More decoder symbols
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Minterms & Decoders
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Note that outputs to decoders correspond to Minterms
Minterms & Decoders
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• SOP can be formed by combining outputs• i.e., Z = (I0’ • I1’) + (I0 • I1’)
• Most Decoders have active-low outputs, so they need to be inverted or a NAND can be substituted
3-to-8 decoder
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74x138 3-to-8-decoder symbol
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Decoder cascading
4-to-16 decoder
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In-Class Practice Problem
• Wire the 74x139 to make a 3-to-8 decoder
• You may use inverters
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In-Class Practice Problem
• Note that this would not normally be done since the 74x138 does the same thing A
BC
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More cascading
5-to-32 decoder
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Decoder applications
• Microprocessor memory systems– selecting different banks of memory
• Microprocessor input/output systems– selecting different devices
• Microprocessor instruction decoding– enabling different functional units
• Memory chips– enabling different rows of memory depending on
address
• Lots of other applications
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Next time
• Buffers
• Drivers
• Encoders
• Multiplexers
• Exclusive OR Gates
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