ee247 lecture 11 - university of california,...

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K.

EE247Lecture 11

• Switched-Capacitor Filters (continued)– Effect of non-idealities– Bilinear switched-capacitor filters– Filter design summary

• Comparison of various filter topologies

• Data Converters

EECS 247 Lecture 11: S.C. Filters/ Data Converters © 2006 H. K. Page 2

Summary Last Lecture

• Switched-capacitor filter design considerations– DDI & LDI Integrator characteristics– Bottom-plate LDI integrator overcomes parasitic

sensitivity issues– Continuous-time and complex conjugate terminations

– Use of T-networks to implement high capacitor ratios• Switched-capacitor filters utilizing double sampling

technique • Effect of non-idealities

– Opamp finite gain– Opamp finite bandwidth– Finite slew rate of the opamp (this lecture)


Switched-Capacitor Direct-Transform Discrete (DDI) Integrator

1s1I

s 1I

CC 1in

CC 1

Vo z( z )zV

z

−−−

= − ×

= − × −

-

+

Vin

Vo

φ1 φ2CI

Cs

φ1

φ1

φ2

T=1/fs


DDI Switched-Capacitor IntegratorCI

Ideal Integrator Magnitude Error Phase Error

( )

( )

1s1I

j T / 2s sj T j T / 2 j T / 2I I

sI

sI

C j TC 1in

j jC CC C1

C j T / 2C

C j T / 2C j T

Vo z( z ) , z ezV

e ee1 since : s in 2 je e e

1j e 2 sin T / 2

T / 21 esin T / 2

ωω ω ω

ω

α α

ω

ω

α

ω

ωω ω

−−

−−

−

−

− −

−

−

= − × =

−= × = × =

= − × ×

= − × ×

-

+

Vin

Vo

φ1 φ2CI

Cs

φ1


DDI Switched-Capacitor Integrator

Example: Mag. & phase error for:1- f max

sig ./ fs = 1/12 Mag. error = 1% or 0.1dBPhase error=-ωT/2= -π f / fs= -π /12 [radian] 15 [degree]Qintg 1/( phase error @ωο in radian ) (Lecture 5 page 1)

Qintg= -12/π = -3.8

2- f / fs=1/32 Mag. error=0.16% or 0.014dBPhase error = ω T/2= -π f / fs= -π /32 [radian] 5.6 [degree]Qintg = -32/π = -10.2

CI

-

+

Vin

Vo

φ1 φ2CI

Cs

φ1

DDI Integrator:Magnitude error no problemPhase error major problem


LDI Switched-Capacitor Integrator

( )

( )

1/ 2s1I

j T / 2s e s 1j T j T / 2 j T / 2I I

sI

sI

C j TC 1 zin

C CC C1

CC

CC j T

Vo2 z( z ) , z eV

e e e

1j 2 sin T / 2

T / 21sin T / 2

ωω ω ω

ω

ω

ωω ω

−−

−− − +

−

− −

= − × =

= − × = ×

= − ×

= − ×

CI

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequencies << sampling freq.

Magnitude error negligible

-

+

Vin

Vo2

φ1 φ2CI

Cs

φ2

LDI

LDI (Lossless Discrete Integrator) same as DDI but output is sampled ½clock cycle earlier


Switched-Capacitor IntegratorParasitic Sensitivity

Effect of parasitic capacitors:

1- Cp1 - driven by opamp o.k.

2- Cp2 - at opamp virtual gnd o.k.

3- Cp3 – Charges to Vin & discharges into CI

Problem parasitic sensitivity

-

+

VinVo

φ1 φ2CI

CsCp3

Cp2

Cp1


Parasitic InsensitiveBottom-Plate Switched-Capacitor Integrator

Sensitive parasitic cap. Cp1 rearrange circuit so that Cp1 does not charge/discharge

φ1=1 Cp1 grounded

φ2=1 Cp1 at virtual groundCp2 driven by a low impedance source

Solution: Bottom plate capacitor integrator

Vi+

Cs-

+ Vo

CI

Cp1

Cp2

φ1 φ2

Vi-


Bottom Plate Switched-Capacitor Integrator

12

12

1s s1 1I I

s s1 1I I

C Cz zC C1 z 1 z

C Cz 1C C1 z 1 z

−−

− −

−

− −

− −

− −− −

Note: Different delay from Vi+ &Vi- to either output

Special attention needed for input/output connections

Vi+

Cs-

+ Vo

CIφ1 φ2

Vi-

Vi+on φ1

Vi-on φ2

Vo1on φ1

Vo2on φ2

φ1

φ2

Vo2

Vo1

Output/Inputz-Transform


Bottom Plate Switched-Capacitor Integratorz-Transform Model

12

12

11 1

1 1

z z1 z 1 z

z 11 z 1 z

−−− −

−

− −

− −

−− −

121

z1 z

−

−−

12z−

Input/Output z-transformVi+

Cs-

+ Vo

CIφ1 φ2

Vi-

φ1

φ2

Vo2

Vo1

Vi+

Vi- 12z+ Vo2

Vo1

LDI

s IC C

s IC C−


LDI Switched-Capacitor Ladder Filter

CsCI

12

1z

1 z

−

−−

-+

+ - + -3

1sτ 4

1sτ 5

1sτ

12z

−

12z

+

12z

+12z

+

12z

−

CsCI

−

CsCI

−CsCI

−CsCI

CsCI

Delay around integrator loop is (z-1/2 . z+1/2 =1) LDI function

12

1z

1 z

−

−−

12

1z

1 z

−

−−12z

−


Effect of Opamp Nonidealities on Switched Capacitor Filter Behaviour

• Opamp finite gain• Opamp finite bandwidth• Finite slew rate of the opamp• Non-linearities associated with opamp

output/input characteristics


Effect of Opamp Non-IdealitiesFinite DC Gain


Cs-

+ Vo

CIφ1 φ2

Vi-DC Gain = a

sI s 1

I

1

Cs C C

s C a

o

o a

1H( s ) f

s f

H( s )s

Q a

ωω

≈ −+ ×

−≈

+ ×

⇒ ≈ Finite DC gain same effect in S.C. filters as for C.T. filtersIf DC gain not high enough causes lowing of overall Q &

droop in passband


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth


Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.= ft

Vo

φ2

T=1/fs

settlingerror

time

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Assumption-

Opamp does not slew (will be revisited)Opamp has only one pole exponential settling


Effect of Opamp Non-IdealitiesFinite Opamp Bandwidth

actual idealIk k 1

I s

I t

I s s

t s

C1 e e ZH ( Z ) H ( Z )

C CC f

where kC C f

f Opamp unity gain frequency , f Clock frequency

π

− − −⎡ ⎤− + ×≈ ⎢ ⎥+⎣ ⎦

= × ×+

→ − − →


Cs-

+ Vo

CIφ1 φ2

Vi-

Unity-gain-freq.= ft

Ref: K.Martin, A. Sedra, “Effect of the OPamp Finite Gain & Bandwidth on the Performance of Switched-Capacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.

Vo

φ2

T=1/fs

settlingerror

time


Effect of Opamp Finite Bandwidth on Filter Magnitude Response

Example:For 1dB magnitude response deviation:1- fc/fs=1/12

fc/ft~0.04ft>25fc

2- fc/fs=1/32fc/ft~0.022

ft>45fc

3- Cont.-Timefc/ft~1/700

ft >700fc fc /ft

|Τ|non-ideal /|Τ|ideal (dB)

fc /fs=1/32fc /fs=1/12Active RC


Effect of Opamp Finite Bandwidth on Filter Critical Frequency

fc /ft

Δωc /ωc

fc /fs=1/32

fc /fs=1/12Active RC

Example:For maximum critical frequency shift of <1%

1- fc/fs=1/32fc/ft~0.028

ft>36fc

2- fc/fs=1/12fc/ft~0.046

ft>22fc

3- Active RCfc/ft~0.008

ft >125fc

C.T. filters

Ref: K.Martin, A. Sedra, “Effect of the Opamp Finite Gain & Bandwidth on the Performance of SwitchedCapacitor Filters," IEEE Trans. Circuits Syst., vol. CAS-28, no. 8, pp. 822-829, Aug 1981.


Opamp Bandwidth Requirements for Switched-Capacitor Filters Compared to Continuous-Time Filters

• Finite opamp bandwidth causes phase lag at the unity-gain frequency of the integrator for both type filters

Results in negative intg. Q & thus increases overall Q and gain@ results in peaking in the passband of interest

• For given filter requirements, opamp bandwidth requirements much less stringent for S.C. filters compared to cont. time filters

lower power dissipation for S.C. filters (at low freq.s only)

• Finite opamp bandwidth causes down shifting of critical frequencies in both type filters– Since cont. time filters are usually tuned tuning accounts for

frequency deviation– S.C. filters are untuned and thus frequency shift could cause

problems specially for narrow-band filters


Sources of Distortion in Switched-Capacitor Filters

• Distortion induced by finite slew rate of the opamp

• Opamp output/input transfer function non-linearity- similar to cont. time filters

• Distortion incurred by finite setting time of the opamp

• Capacitor non-linearity- similar to cont. time filters

• Distortion due to switch clock feed-through and charge injection


What is Slewing?

oV

Vi+Vi-

φ2

Cs

-

+

Vin

Vo

φ2CI

Cs

CI

CL

Assumption:Integrator opamp is a simple class Atransconductance type differential pairwith fixed tail current Iss

Iss


oV

Vi+Vi-

φ2

Cs

CI

Iss

What is Slewing?

Io

VinVmax

Imax= -Iss/2

Slope ~ gm

|VCs| > VmaxOutput current constant Io=Iss/2 or –Iss/2Vo ramps down/up Slewing

After Vcs is discharged enough to have: |VCs|<Vmax Io=gm VCs Exponential or over-shoot settling

Io

Opamp Io v.s. Vin

Imax= +Iss/2


Distortion Induced by Opamp Finite Slew Rate

Multiple pole settling

One pole settling

Output Voltage

TimeSlewing SettlingSettling (multi-pole)

Vo


Ideal Switched-Capacitor Output Waveform

φ1

φ2

Vin

Vo

Vcs

Clock-

+

Vin

Vo

φ1CI

Cs

-

+

Vin

Vo

φ2CI

Cs

φ2 High Charge transferred from Cs to CI


Slew Limited Switched-Capacitor IntegratorOutput Slewing & Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing LinearSettling



Distortion Induced by Finite Slew Rate of the Opamp

Ref: K.L. Lee, “Low Distortion Switched-Capacitor Filters," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Feb. 1986 (ERL Memorandum No. UCB/ERL M86/12).


Distortion Induced by Opamp Finite Slew Rate

• Error due to exponential settling changes linearly with signal amplitude

• Error due to slew-limited settling changes non-linearly with signal amplitude (doubling signal amplitude X4 error)

For high-linearity need to have either high slew rate or non-slewing opamp

( )( )

( )

o s

o s

2T2ok 2r s

2T 22 oo o3 o s 3

r s r s

8 sinVHD S T k k 4

8 sin fV 8 VHD for f f HDS T 15 15S f

ω

ω

π

ππ

=−

→ = >> → ≈



Example: Slew Related Harmonic Distortion

( )o s2T

2o3r s

2oo3

r s

8 sinVHD S T 15

f8 VHD 15S f

ω

π

π

=

≈


Switched-capacitor filter with 4kHz bandwidth, fs=128kHz, Sr=1V/μsec, Vo=3V

12dB


Distortion Induced by Opamp Finite Slew Rate Example

-120

-100

-80

-60

-40

-20

1 10 100 1000

HD

3 [d

B]

(Slew-rate / fs ) [V]

f / fs =1/32

f / fs =1/12

Vo =1V V

o =2V

Vo =1V V

o =2V


Distortion Induced by Finite Slew Rate of the Opamp

• Note that for a high order switched capacitor filter only the last stage slewing will affect the output linearity (as long as the previous stages settle to the required accuracy)

Can reduce slew limited linearity by using an amplifier with a higher slew rate only for the last stageCan reduce slew limited linearity by using class A/B amplifiers

• Even though the output/input characteristics is non-linear as long as the DC open-loop gain is high, the significantly higher slew rate compared to class A amplifiers helps improve slew rate induced distortion

• In cases where the output is sampled by another sampled data circuit (e.g. an ADC or a S/H) no issue with the slewing of the output as long as the output settles to the required accuracy & is sampled at the right time


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2CI

Cs

At the instant Cs connects to input of opamp (t=0+)Opamp not yet active at t=0+ due to finite opamp bandwidth delayFeedforward path from input to output generates a voltage spike at the output with polarity opposite to final Vo step- spike magnitude function of CI, CL , Cs

Spike increases slewing periodEventually, opamp becomes active - starts slewing followed by subsequent settling

CL

Vo

φ2CI

CsCL

t=0+


Switched-Capacitor Circuit Opamp not Active @ t=0+

-

+

Vin

Vo

φ2CI

CsCL

Vo

φ2CI

CsCL

t=0+

( )

( )

0 0

0 0 0

0 0 0 0

0 0 0

t t I Ls Cs Cs s eq eq

I L

t t tI s Iout Cs Cs

I L s eq I L

t t t tL s I eq L s Cs Cs s L Cs Cs

t t ts Iout Cs Cs

s L I L

C CCharg e sharing : C V V C C where CC C

C C CV V VC C C C C C

Assu min g C C C C C C V V C C V V

C CV V VC C C C

Note

− +

+ + −

− + − +

+ − −

= + =+

Δ = = ×+ + +

<< << → ≈ → ≈ + → ≈

→ Δ ≈ × ≈+ +

0 0final t ts sout Cs Cs

I I

C Cthat V V VC C

+ −Δ ≈ − ≈ −


More Realistic Switched-Capacitor Circuit Slew Scenario

-

+

Vin

Vo

φ2CI

CsCL

Vo

φ2CI

CsCL

t=0+

( )0 0

0 0 0

t t I Ls Cs Cs s eq eq

I L

t t ts sCs Cs Cs

I Ls eqs

I L

C CCharg e sharing : C V V C C where CC C

C CV V V C CC C CC C

− +

+ − −

= + =+

= =+ +

+

Notice that if CL is large some of the charge stored on Cs is lost prior to opamp becoming effective operation looses accuracy

Partly responsible for S.C. filters only good for low-frequency applications


More Realistic S.C. Slew Scenario

Vo_realIncluding t=0+spike


Slewing

Spike generated at t=0+

Vo_real

Vo_ideal



Ref: R. Castello, “Low Voltage, Low Power Switched-Capacitor Signal Processing Techniques," U. C. Berkeley, Department of Electrical Engineering, Ph.D. Thesis, Aug. ‘84 (ERL Memorandum No. UCB/ERL M84/67).


Sources of Noise in Switched-Capacitor Filters

• Opamp Noise– Thermal noise– 1/f (flicker) noise

• Thermal noise associated with the switching process (kT/C)– Same as continuous-time filters

• Precaution regarding aliasing of noise required


Other z domain IntegratorsExample: Bilinear

• Bilinear integrator

( ) ( ) ( ) ( )

( )

1 1

1

1

1 ( ) 1 ( )

( ) 1( ) 1

o o i i

o i

o

i

v nT v nT T k v nT v nT T

z V z k z V z

V z zH z kV z z

− −

−

−

⎡ ⎤= − + + −⎣ ⎦

⎡ ⎤ ⎡ ⎤− = +⎣ ⎦ ⎣ ⎦

+= =−


Bilinear Integrator

sI

j Tsj TI

sI s

1CC 1

CC 1

C sC Ts 2

1 ZH( Z )1 Z1 e

eT1

j T tan

ωω

ωω

ω

−+−

−−

−

+= − ×−

=− ×

=

Ideal Integrator Magnitude Error

No Phase Error! For signals at frequency <<sampling freq.

Magnitude error negligible

Ref: R. Gregorian, G. Temes, “Analog CMOS Integrated Circuits," Wiley, 1986, pp 277 .

- Not implemented by “standard” SC integrators- Synthesis:

Biquads: direct coefficient comparisonExample: Bilinear S.C. integrator:


LDI & Bilinear TransformationFrequency Warping

LDI :

Bilinear

1/ 21 s

s

j Tj T s

s

sT

2T

2s

1 s1 T1 2

T2s

T 11 Z21 Z j sin

2 j sinT

T 11 e1 1 Z2e1 Z jtan

2 jtanT

s

s

s

s

ωω

ω

ω

ω

ω

−−

−+−

−

−− −

⇒ =

⇒

+⇒ = =−

⇒


Other z domain IntegratorsExample: Bilinear

• Frequency translation

( ) 22

1

tan

jf TSC

RC

SC z es jf

s SCRC

s

H zs

f fff

ππ

ππ

===

⎛ ⎞= ⎜ ⎟

⎝ ⎠⎟⎟⎠

⎞⎜⎜⎝

⎛=

s

SCsRC f

fff ππ

sin

Bilinear LDI


Bilinear Transform

• Entire jω axis maps onto the unit circle

• Mapping is nonlinear (tan distortion)prewarp specifications of RC

prototype Matlab filter design automates this (see, e.g. bilinear)

⎟⎟⎠

⎞⎜⎜⎝

⎛=

s

SCsRC f

fff ππ

tan

0 0.5 1 1.5 2 2.5 3

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

f sc /f

s

fRC /fs


Bilinear & LDI Transformation Frequency Warping

As long as f<<fs error negligible


“Bilinear” Bandpass

fs = 100kHzfc = fs/8Q = 10

Matlab:

0.0378 z^2 - 0.0378

H(z) = ----------------------

z^2 - 1.362 z + 0.9244

zero at fs/2

Pole-Zero Map

Real Axis

Imag

Axi

s

-1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1


( )( )

( ) ( )( ) ( )656554

252352513

23

122

KKzKKKKzKKKzKKKKKzK

zVzV

i

o

−+++−+−+++−+=

phi1phi1 phi1

phi2 phi2

K1 CA = 0F

-1M-1M

CA = 1pFCA = 1pFCA = 1pFCA = 1pF

phi1phi1 phi2

phi2 phi1

K5 CB = 500fF

-1M-1M-1M-1M

CB = 1pF

phi1phi1 phi1

phi2 phi2

K4 CA = 1.125pF

K3 CB = 37.8fF

K2 CA = 151.2fF

K6 CA = 151.2fF

VoVi

Martin-Sedra Biquad

Periodic AC Analysis PAC1log sweep from 1k to 50k (300 steps)

fs = 100kHzCLK1

V1ac = 1V

Ref: K. Martin and A. S. Sedra, “Strays-insensitive switched-capacitor filters based on the bilinear z transform,” Electron. Lett., vol. 19, pp. 365-6, June 1979.


Magnitude Response

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

x 105

-70

-60

-50

-40

-30

-20

-10

0

Frequency [Hz]

Mag

nitu

de [

dB]


LDI vs Bilinear Transform• LDI transform:

– Realized by “standard” switched-capacitor integrators– Some high frequency zeros may get lost– Simple filter synthesis:

• Replace RC integrators with SC integrators• Ensure clock phases chosen so that all integrators loops LDI type

• Bilinear transform– Not implemented by “standard” SC integrators– Synthesis:

• Biquads: direct coefficient comparison• Ladders: see

R. B. Datar and A. S. Sedra, “Exact design of strays-insensitive switched capacitor high-pass ladder filters”, Electron. Lett., vol. 19, no 29, pp. 1010-12, Nov. 1983.


Switched-Capacitor Filter ApplicationExample: Voice-Band Codec (Coder-Decoder) Chip

Ref: D. Senderowicz et. al, “A Family of Differential NMOS Analog Circuits for PCM Codec Filter Chip,” IEEE Journal of Solid-State Circuits, Vol.-SC-17, No. 6, pp.1014-1023, Dec. 1982.

fs= 1024kHz fs= 128kHz fs= 8kHz fs= 8kHz

fs= 8kHz fs= 128kHz fs= 128kHz

fs= 128kHz


CODEC Transmit Path Lowpass Filter Frequency Response

0 2000 4000 6000 8000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

Note: fs=128kHz


CODEC Transmit Path Highpass Filter

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

1000010010

Note: fs=8kHz


CODEC Transmit Path Filter Overall Frequency Response

1000-50

-40

-30

-20

-10

0

Frequency (Hz)

Mag

nitu

de (d

B)

1000010010

Low Q bandpass (Q<1) filter shape Implemented with lowpass followed by highpass


CODEC Transmit Path Clocking Scheme

First filter (1st order RC type) performs anti-aliasing for the next S.C. biquad

The first 2 stage filters form 3rd order elliptic with corner frequency @ 32kHz Anti-aliasing for the next lowpass filter

The stages prior to the high-pass perform anti-aliasing for high-pass

Notice gradual lowering of clock frequency Ease of anti-aliasing


SC Filter SummaryPole and zero frequencies proportional to – Sampling frequency fs– Capacitor ratios

High accuracy and stability in responseLong time constants realizable without large R, C

Compatible with transconductance amplifiers– Reduced circuit complexity, power dissipation

Amplifier bandwidth requirements less stringent compared to CT filters (low frequencies only)Issue: Sampled-data filters require anti-aliasing prefiltering


Switched-Capacitor Filters versus Continuous-Time Filter Limitations

Considering overall effects:

• Opamp finite unity-gain-bandwidth

• Opamp settling issues

• Opamp finite slew rate

• Clock feedthru• Switch+ sampling

cap. finite time-constant

Filter bandwidthAssuming constant opamp fu

MagnitudeError

5-10MHz

S.C. Filter

Cont. Time Filter

Limited switched-capacitor filter performance frequency range


SummaryFilter Performance versus Filter Topology

_

1-5%

1-5%

1-5%

1-5%

Freq. tolerance+ tuning

<<1%40-90dB~ 10MHzSwitched Capacitor

+-40-60%40-70dB~ 100MHzGm-C

+-30-50%50-90dB~ 5MHzOpamp-MOSFET-RC

+-30-50%40-60dB~ 5MHzOpamp-MOSFET-C

+-30-50%60-90dB~10MHzOpamp-RC

Freq. tolerance w/o tuning

SNDRMax. Usable Bandwidth


Data Converters


Material Covered in EE247Where are We?

Filters – Continuous-time filters

• Biquads & ladder type filters• Opamp-RC, Opamp-MOSFET-C, gm-C filters• Automatic frequency tuning

– Switched capacitor (SC) filters

• Data Converters– D/A converter architectures– A/D converter

• Nyquist rate ADC- Flash, Pipeline ADCs,….• Oversampled converters• Self-calibration techniques

• Systems utilizing analog/digital interfaces


Data Converter Topics• Basic operation of data converters

– Uniform sampling and reconstruction– Uniform amplitude quantization

• Characterization and testing• Common ADC/DAC architectures• Selected topics in converter design

– Practical implementations– Desensitization to analog circuit non-idealities

• Figures of merit and performance trends


Suggested Reference Texts• R. v. d. Plassche, CMOS Integrated Analog-to-Digital and

Digital-to-Analog Converters, 2nd ed., Kluwer, 2003.

• B. Razavi, Data Conversion System Design, IEEE Press, 1995.

• S. Norsworthy et al (eds), Delta-Sigma Data Converters, IEEE Press, 1997.Extensive treatment of oversampled converters including stability, tones, bandpass converters.

• J. G. Proakis, D. G. Manolakis, Digital Signal Processing, Prentice Hall, 1995.


Converter Applications


Data Converter Basics

• DSPs benefited from device scaling

• However, real world signals are still analog:– Continuous time– Continuous amplitude

• DSP can only process:– Discrete time– Discrete amplitude

Need for data conversion from analog to digital and digital to analog

Analog Postprocessing

D/AConversion

DSP

A/D Conversion

Analog Preprocessing

Analog Input

Analog Output

000...001...

110

Filters

Filters

?

?


A/D & D/A ConversionA/D Conversion

D/A Conversion


Data Converters

• Stand alone data converters– Used in variety of systems

– Example: Analog Devices AD9235 12bit/ 65Ms/s ADC- Applications:

• Ultrasound equipment

• IF sampling in wireless receivers

• Various hand-held measurement equipment

• Low cost digital oscilloscopes


Data Converters• Embedded data converters

– Cost, reliability, and performance Integration of data conversion interfaces along with DSPs

– Main issues• Feasibility of integrating sensitive analog functions in a

technology optimized for digital performance

• Down scaling of supply voltage

• Interference & spurious signal pick-up from on-chip digital circuitry

• Portable applications dictate low power consumption


Example: Typical Cell PhoneContains in integrated form:• 4 Rx filters• 4 Tx filters

• 4 Rx ADCs• 4 Tx DACs• 3 Auxiliary ADCs• 8 Auxiliary DACs

Total: Filters 8

ADCs 7

DACs 12

Dual Standard, I/Q

Audio, Tx/Rx powercontrol, Battery chargecontrol, display, ...


D/A Converter Transfer Characteristics• For an ideal digital-to-analog

converter accepting digital inputs b1-bn and producing either an analog output voltage or current with: uniform, binary digital encoding & a unipolar output ranging from 0 to VFS

Nomenclature:

D/A

……..…b1 b2 b3 bn

V0

MSB LSB

FS

FSN

FS2

N # of bi ts

V ful l scale output

min. s tep size 1LSB

V2

Vor N log resolut ion

=

=

Δ = →

Δ =

= →Δ

N

0 FSi 1

N

i 1

i

N i

biV V

2

bi 2 , bi 0 or 1

=

=

−

=

= Δ × =

∑

∑


D/A Converter Exampe: D/A with 3-bit Resolution

D/A

b1 b2 b3

V0

MSB LSB

( )

( )

FS

0 1 2 3

3FS

0

0

NFS FS

2 1 0

2 1 0

Example : N 3

Assume V 0.8VInput code is 101

V b 2 b 2 b 2

Then : V / 2 0.1V

V 0.1V 1 2 0 2 1 2

V 0.5V

Note : MSB V / 2 & LSB V / 2

=

=

= Δ × + × + ×

Δ = =

→ = =× + × + ×

→ =

→ →

1 0 1


Ideal D/A Transfer Characteristic

• Ideal DAC introduces no error!

• One-to-one mapping from input to output

000 001 010 011 100 101 110 111

Step Height (1LSB =Δ)

Ideal Response

Digital InputCode

Analog OutputVFS

VFS /2

VFS /8


A/D Converter Transfer Characteristic

• For an ideal analog-to-digital converter with uniform, binary digital encoding & a unipolar input range for 0 to VFS

( ) FSi

FS m

Note : D Vb 1,al l i1

1V2

→ − Δ=⎛ ⎞−→ ⎜ ⎟⎝ ⎠

FS

FSm

where m # of bi ts

V ful l scale output

step size

V

2

=

=

Δ =

Δ =

D/A

……..…b1 b2 b3 bm

V0

MSB LSB


Ideal A/D Transfer Characteristic

• Ideal ADC introduces error

(+-1/2 Δ) Δ = VFS /2 m

m= # of bits

• This error is called ``quantization error``

111

110

101

100

011

010

001

000

Digital Output

Analog input

0 Δ 2Δ 3Δ 4Δ 5Δ 6Δ 7Δ

1LSB


Data Converter Performance Metrics• Data Converters are typically characterized by static, time-domain,

& frequency domain performance metrics :– Static

• Monotonicity• Offset• Gain error• Differential nonlinearity (DNL)• Integral nonlinearity (INL)

– Dynamic• Delay, settling time• Aperture uncertainty• Distortion- harmonic content• Signal-to-noise ratio (SNR), Signal-to-(noise+distortion) ratio (SNDR)• Idle channel noise• Dynamic range & spurious-free dynamic range (SFDR)

ee247 lecture 11 - university of california,...

Documents