ee141 © digital integrated circuits 2nd introduction 1 ee4271 vlsi design dr. shiyan hu office:...

EE141© Digital Integrated Circuits2nd Introduction1

EE4271EE4271VLSI DesignVLSI Design

Dr. Shiyan HuOffice: EERC [email protected]

Adapted and modified from Digital Integrated Circuits: A Design Perspective by Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic.

IntroductionIntroduction

EE141© Digital Integrated Circuits2nd Introduction

Class Time and Office HourClass Time and Office Hour Class Time: MWF 16:05-16:55 (EERC 214) Office Hours: MWF 15:00-16:00 or by appointment, office:

EERC 518 Textbook (required): Digital Integrated Circuits: A Design

Perspective, second edition, by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, Prentice Hall, 2003. or

CMOS VLSI Design: A Circuits and Systems Perspective, fourth edition, by Neil H.E. Weste and David M. Harris, Addiuson Wesley, 2009

Grading: Homework 20% Midterm 20% Final 30% Lab 30%

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Course WebsiteCourse Website http://www.ece.mtu.edu/faculty/shiyan/EE4271Fall13.htm Contact information of instructor

Email: [email protected] EERC 518 Instructor’s webpage: http://www.ece.mtu.edu/faculty/shiyan

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What is this course all about?What is this course all about?

Introduction to digital integrated circuits. CMOS devices and manufacturing technology.

CMOS inverters and gates. Propagation delay, noise margins, and power dissipation. Combinatorial Circuits and Sequential circuits. Computer-Aided Design.

What will you learn? Understanding, designing, and optimizing digital

circuits with respect to different quality metrics: speed, power dissipation, cost, and reliability


AgendaAgenda Introduction: Issues in digital integrated circuit (IC)

design Device: MOS Transistors Wire: R, L and C Fabrication process CMOS inverter Combinational logic structures Sequential logic gates Design methodologies VLSI Computer-Aided Design Timing/power optimizations on gate and interconnect


IntroductionIntroduction

Why is designing digital ICs different today than it was before?

What is the challenge?


The Transistor Revolution

First transistorBell Labs, 1948


The First Integrated Circuit

First ICJack KilbyTexas Instruments1958


Intel 4004 Micro-ProcessorIntel 4004 Micro-Processor

19711000 transistors1 MHz operation


Intel 8080 Micro-Processor

19744500 transistors


Intel Pentium (IV) microprocessor

200042 million transistors1.5 GHz


Modern ChipModern Chip


Moore’s LawMoore’s Law

In 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.


Moore’s lawMoore’s law

Twice the Twice the number of number of transistors, transistors, approximately approximately every two every two yearsyears


Moore’s LawMoore’s Law

161514131211109876543210

195

9

196

0

196

1

196

2

196

3

196

4

196

5

196

6

196

7

196

8

196

9

197

0

197

1

197

2

197

3

197

4

197

5

LO

G 2 O

F T

HE

NU

MB

ER

OF

CO

MP

ON

EN

TS

PE

R I

NT

EG

RA

TE

D F

UN

CT

ION

Electronics, April 19, 1965.


Transistor CountsTransistor Counts

1,000,000

100,000

10,000

1,000

10

100

11975 1980 1985 1990 1995 2000 2005 2010

8086

80286i386

i486Pentium®

Pentium® Pro

K1 1 Billion Billion

TransistorsTransistors

Source: IntelSource: Intel

ProjectedProjected

Pentium® IIPentium® III

Courtesy, Intel


ITRS Prediction


Moore’s law in MicroprocessorsMoore’s law in Microprocessors

40048008

80808085 8086

286386

486Pentium® proc

P6

0.001

0.01

0.1

1

10

100

1000

1970 1980 1990 2000 2010Year

Tra

nsi

sto

rs (

MT

)

2X growth in 1.96 years!

Transistors on Lead Microprocessors double every 2 yearsTransistors on Lead Microprocessors double every 2 years

Courtesy, Intel


FrequencyFrequency

P6Pentium ® proc

486386

28680868085

8080

80084004

0.1

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Fre

qu

ency

(M

hz)

Lead Microprocessors frequency doubles every 2 yearsLead Microprocessors frequency doubles every 2 years

Doubles every2 years

Courtesy, Intel

Not true any more!


0.18

Source: Gordon Moore, Chairman Emeritus, Intel Corp.

050

100

150

200

250

300

Technology generation (m)

Del

ay (

pse

c)

Transistor/Gate delay

Interconnect delay

0.8 0.5 0.250.25

0.150.35

Interconnects Dominate Interconnects Dominate


Power DissipationPower Dissipation

P6Pentium ® proc

486

3862868086

80858080

80084004

0.1

1

10

100

1971 1974 1978 1985 1992 2000Year

Po

wer

(W

atts

)

Lead Microprocessors power continues to increaseLead Microprocessors power continues to increase

Courtesy, Intel


Power is a major problemPower is a major problem

5KW 18KW

1.5KW 500W

40048008

80808085

8086286

386486

Pentium® proc

0.1

1

10

100

1000

10000

100000

1971 1974 1978 1985 1992 2000 2004 2008Year

Po

wer

(W

atts

)

Power delivery and dissipation will be prohibitivePower delivery and dissipation will be prohibitive

Courtesy, Intel


Power densityPower density

400480088080

8085

8086

286386

486Pentium® proc

P6

1

10

100

1000

10000

1970 1980 1990 2000 2010Year

Po

wer

Den

sity

(W

/cm

2)

Hot Plate

NuclearReactor

RocketNozzle

Power density too high to keep junctions at low tempPower density too high to keep junctions at low temp

Courtesy, Intel


Not Only MicroprocessorsNot Only Microprocessors

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

PowerManagement

Small Signal RF

PowerRF

((data from Texas Instruments)data from Texas Instruments)

CellPhone


Many Chips


Challenges in Digital DesignChallenges in Digital Design

• Ultra-high speed design• Interconnect delay

• Reliability, Manufacturability• Power Dissipation• Time to market


Productivity TrendsProductivity Trends

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

200

3

198

1

198

3

198

5

198

7

198

9

199

1

199

3

199

5

199

7

199

9

200

1

200

5

200

7

200

9

10

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

10,000

1,000

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

er C

hip

(M)

0.01

0.1

1

10

100

1,000

10,000

100,000

Pro

du

ctiv

ity

(K)

Tra

ns.

/Sta

ff -

Mo

.

Source: Sematech

Complexity outpaces design productivity

Co

mp

lexi

ty

Courtesy, ITRS Roadmap


Computer-Aided DesignComputer-Aided Design Every new generation can integrate 2x more

functions per chip Chip price does not increase significantly Cost of a function decreases by 2x

However, Design engineering population does not double every

two years. How to design much more complex chips (with more

and more functions)? Great need for ultra-fast design methods

Design Automation (Computer-Aided Design)


Design Abstraction Enables CADDesign Abstraction Enables CAD

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM


Design MetricsDesign Metrics

How to evaluate performance of a digital circuit (gate, block, …)? Speed (delay, operating frequency) Power dissipation Cost

– Design time– Design effort

Reliability– Process, voltage and temperature variations


Cost of Integrated CircuitsCost of Integrated Circuits

NRE (non-recurrent engineering) costs design time and effort to design layout and

mask one-time cost factor

Recurrent costs silicon processing, packaging, test proportional to volume proportional to chip area


NRE Cost is IncreasingNRE Cost is Increasing


Die CostDie Cost

Single die

Wafer

From http://www.amd.com

Going up to 12” (30cm)


YieldYield

%100per wafer chips ofnumber Total

per wafer chips good of No.Yield

yield Dieper wafer Dies

costWafer cost Die


DefectsDefects

area dieareaunit per defects

1Yield

is approximately 3 in the current fabrication processAbout 0.5-1 defect per cm2.


Some Examples (1994)Some Examples (1994)Chip Metal

layersLine width

Wafer cost

Def./ cm2

Area mm2

Dies/wafer

Yield Die cost

386DX 2 0.90 $900 1.0 43 360 71% $4

486 DX2 3 0.80 $1200 1.0 81 181 54% $12

Power PC 601

4 0.80 $1700 1.3 121 115 28% $53

HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

Pentium 3 0.80 $1500 1.5 296 40 9% $417


SummarySummary Digital integrated circuit design faces huge

challenges for the coming decades High speed Low power Short design time for highly complex circuit having 1

billion transistors Reliable under noise and variations

Purpose of the course Understand the basics of VLSI design Getting a clear perspective on the challenges and

potential solutions

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