EE105 Fall 2007 Lecture 19, Slide 1 Prof. Liu, UC Berkeley

Lecture 19

OUTLINE• Common-gate stage• Source follower

Reading: Chapter 7.3-7.4

ANNOUNCEMENTS• For Problem 4 of HW10, use VDD = 1.8V and VTH = 0.4V

• Note: Midterm #2 will be held on Thursday 11/15

EE105 Fall 2007 Lecture 19, Slide 2 Prof. Liu, UC Berkeley

Diode-Connected MOSFETs

• Note that the small-signal model of a PMOSFET is identical to that of an NMOSFET

11

1o

mX r

gR 2

2

1o

mY r

gR

Diode-connected NMOSFET

Small-signal analysis circuit Small-signal analysis circuit

Diode-connected PMOSFET

EE105 Fall 2007 Lecture 19, Slide 3 Prof. Liu, UC Berkeley

Summary of MOSFET Impedances• Looking into

the drain, the impedance is ro if the gate and source are (ac) grounded.

• Looking into the gate, the impedance is infinite (∞).

• Looking into the source, the impedance is 1/gm in parallel with ro if the gate and drain are (ac) grounded.

EE105 Fall 2007 Lecture 19, Slide 4 Prof. Liu, UC Berkeley

Common-Gate Amplifier Stage• An increase in Vin decreases VGS and hence decreases ID.

The voltage drop across RD decreases Vout increases

The small-signal voltage gain (Av) is positive.

Dmv RgA

EE105 Fall 2007 Lecture 19, Slide 5 Prof. Liu, UC Berkeley

Operation in Saturation Region• For M1 to operate in saturation, Vout cannot fall below Vb-VTH.

Trade-off between headroom and voltage gain.

EE105 Fall 2007 Lecture 19, Slide 6 Prof. Liu, UC Berkeley

I/O Impedances of CG Stage ( = 0)

Dout RR m

in gR

1

Small-signal analysis circuit fordetermining output resistance, Rout

Small-signal analysis circuit fordetermining input resistance, Rin

EE105 Fall 2007 Lecture 19, Slide 7 Prof. Liu, UC Berkeley

CG Stage with Source Resistance

S

m

Dv

Rg

RA

1

in

mS

mX v

gR

gv

1

1

1

1

SmDm

in

X

X

out

in

out

RgRg

v

v

v

v

v

v

Small-signal equivalent circuit seen at input

For= 0:

EE105 Fall 2007 Lecture 19, Slide 8 Prof. Liu, UC Berkeley

OSOmSSmOout rRrgRRgrR 11

• The output impedance of a CG stage with source resistance is identical to that of CS stage with degeneration.

Small-signal analysis circuit fordetermining output resistance, Rout

EE105 Fall 2007 Lecture 19, Slide 9 Prof. Liu, UC Berkeley

CG Stage with Biasing• R1 and R2 establish the gate bias voltage.

• R3 provides a path for the bias current of M1 to flow.

Dm

Sm

m

in

out RgRgR

gR

v

v

/1||

/1||

3

3

EE105 Fall 2007 Lecture 19, Slide 10 Prof. Liu, UC Berkeley

CG Stage with Gate Resistance• For low signal frequencies, the gate conducts no current. Gate resistance does not affect the gain or I/O impedances.

EE105 Fall 2007 Lecture 19, Slide 11 Prof. Liu, UC Berkeley

CG Stage Example

DOS

m

Omout RrRg

rgR ||||1

1

2

11

Smm

Dm

in

X

X

outv Rgg

Rg

v

v

v

vA

21

1

1

Small-signal equivalent circuit seen at input

Small-signal equivalent circuit seen at output

inSmm

in

Smm

mmX v

Rggv

Rgg

ggv

21

21

21

1

1

11

11

12

111

1O

mSOmout rg

RrgR

EE105 Fall 2007 Lecture 19, Slide 12 Prof. Liu, UC Berkeley

Source Follower Stage

Small-signal analysis circuit fordetermining voltage gain, Av

1||

1||

LO

m

LO

in

outv

Rrg

Rr

v

vA

Equivalent circuit

Looutinm

Lomout

Rrvvg

Rrvgv

1outin vvv 1

EE105 Fall 2007 Lecture 19, Slide 13 Prof. Liu, UC Berkeley

Source Follower Example• In this example, M2 acts as a current source.

21

1

21

||1

||

OO

m

OOv

rrg

rrA

EE105 Fall 2007 Lecture 19, Slide 14 Prof. Liu, UC Berkeley

Rout of Source Follower• The output impedance of a source follower is relatively low,

whereas the input impedance is infinite (at low frequencies); thus, it is useful as a voltage buffer.

L

m

LO

m

out Rg

Rrg

R ||1

||||1

Small-signal analysis circuit fordetermining output resistance, Rout

EE105 Fall 2007 Lecture 19, Slide 15 Prof. Liu, UC Berkeley

Source Follower with Biasing• RG sets the gate voltage to VDD; RS sets the drain current.

(Solve the quadratic equation to obtain the value of ID.)

221

THSDDDoxnD VRIVLW

CI

Assuming = 0:

EE105 Fall 2007 Lecture 19, Slide 16 Prof. Liu, UC Berkeley

Supply-Independent Biasing• If Rs is replaced by a current source, the drain current ID

becomes independent of the supply voltage VDD.