ee-612: lecture 25: cmos circuits: part 2reza2/courses/491/slides/05-c... · 2008-01-21 ·...

Lundstrom EE-612 F06 1

EE-612:Lecture 25:

CMOS Circuits: Part 2

Mark LundstromElectrical and Computer Engineering

Purdue UniversityWest Lafayette, IN USA

Fall 2006

www.nanohub.orgNCN


Outline

1) Review

2) Speed (continued)

3) Power

4) Circuit performance


CMOS inverter

VDD

VIN VOUT

PMOS

NMOS VDD

VDD

V--

>O

UT

VDD/2

VIN -->S B

D

S B

D

transfer characteristic

VDD/2

noise margins


importance of gain

Vout

VinVDD

VDD

VDD 2Aυ = 1 must have gain to

have noise margins

dVout

dVin

= Aυ = gmn + gmp( ) ron || rop( )> 1


outline

1) Review

2) Speed (continued)

3) Power



CMOS inverter speed

VDD

VIN

VOUT

S

D

D

S

+

-CTOT Rswn = kn

VDD

IN (on)kn >

12

τ =12

CTOTVDD

2IN (on)+

CTOTVDD

2IP (on)⎛⎝⎜

⎞⎠⎟

τ =RswN + RswP( )

2CTOT

τ = RswCTOT


loaded propagation delay

VDD

VIN

CTOT

CinCout Cwire Cin

Cin

CTOT = Cout + CL + FO × Cin


Miller C

VD0

p-Si

n+ n+

COV

+ -COV

VDD

0

VDD

0

Vc (t << 0) = −VDD

Vc (t >> 0) = +VDD

ΔVc = 2VDD

ΔQc = ΔVcCOV = 2VDDCOV = CMVDD

CM = 2COV

“feed forward”


on-current determines circuit speed

VDD

VIN

VOUT

S

D

D

S

+

-CTOT

1) quasi-static assumption2) simplified ID - VDS

VDSVDSAT

IN on( )

IN

τ = RswCTOT Rsw ~ VDD / ID (ON)


metrics for circuit speed

K.K. Ng, et al., “Effective On-Current of MOSFETs for Large-Signal Speed Consideration,” IEDM, Dec., 2001.

M.H. Na, et al., “The Effective Drive Current in CMOS Inverters,” IEDM, Dec., 2002.

J. Deng and H.S.P. Wong, “Metrics for Performance Benchmarking of Nanoscale Si and Carbon Nanotube FETs Including Device Nonidealities,”IEEE Trans. Electron Dev., 53, pp. 1317-1366, 2006.

R. Venugopal, et al., “Design of CMOS Transistors to Maximize Circuit FOM Using a Coupled Process and Mixed Mode Simulation Methodology,”IEEE Electron Dev. Lett., 53, pp. 1317-1366, 2006.


outline

1) Review

2) Speed

3) Power



power

VDD

VIN+

-

t0

VDD

Vin (t)

CTOT12

CTOTVDD2T


discharge cycle

+

-

t0

VDD

Vin (t)

CTOT12

CTOTVDD2

T / 2

EC (0) =12

CTOTVDD2

EC (T / 2) = 0

Pdynamic =ΔE

T / 2=

CTOTVDD2

T

Vin (t)

Pdynamic = α f CTOTVDD2

switching activity


discharge through a resistor

+

-

t0

VDD

Vin (t)

CTOT Vc (t)

T / 2

VC (t) = Vc (0)e− t / RCTOT = VDD e− t /τ

Vin (t)

R +-

PR (t) = VC2 (t) R

PAVE =PR (t)dt

0

T /2

∫T / 2

=2T

VDD2

R0

T /2

∫ e−2t /τdt

= f CTOTVDD2


charging cycle

VDD

VIN+

-CTOT

12

CTOTVDD2

does it take power to put energy in the capacitor?


charging cycle (ii)

+

-

t

0

VDD

V (t)

CTOT Vc (t)

T / 2

V (t)

EC (T / 2) =12

CTOTVDD2

EC (0) = 0

EB = VDD0

T /2

∫ i(t)dt

EB = VDD i(t)0

T /2

∫ dt = VDD Q

EB = VDD Q = CTOTVDD2

Ediss =12

CTOTVDD2


charging cycle (iii)

+

-

t

0

VDD

V (t)

CTOT Vc (t)

T / 2

V (t)

R +-

Vc (t) = VDD − i t( )R

i(t) = CTOTdVc

dt

i(t) = −RCTOTdidt

i(t) = i(0+ )e− t /τ = VDD R( )e− t /τ

EB = VDD i(t)dt0

T /2

∫ = CTOTVDD2

Ediss =12

CTOTVDD2


adiabatic charging

+

-

t0

VDD

V (t)

CTOT Vc (t)

T

V (t)

R +- i(t) = CTOTdVdt

= CTOTVDD

T

PR = i2R =CTOTVDD

T⎛⎝⎜

⎞⎠⎟

2

R

Ediss = PRdt0

T

∫ =CTOT

2 VDD2

T 2 RT

Ediss = CTOTVDD2 RCTOT

T⎛⎝⎜

⎞⎠⎟


outline

1) Review

2) Speed

3) Power


5) CMOS circuit metrics


device impact on circuit performace

Question:

Given a technology, how does circuit performance depend on transistor design (W, TOX, VDD, etc.)

Taur and Ning assume a 250nm technology and explore this question by Spice simulation (see pp. 264 - 279). Can we understand the major trends simply?


effect of transistor W on delay

τ =Rswn + Rswp( )

2CTOT = RswCTOT

CTOT = Cout + Cwire + FO × Cin Rsw = kVDD ID (on)

Cout ~ W

Cin ~ W

I(on) ~ W

Rsw ~ 1 / W


loaded vs. unloaded delay

τ = RswCTOT = Rsw Cout + FO × Cin + Cwire( )

i) unloaded:Cin and Cout dominate, CTOT ~ W--> τ independent of W

ii) loaded:CL dominates, CTOT ~ independent of W--> τ ~1/ W


effect of TOX on delay

τ = RswCTOT = Rsw Cout + FO × Cin + CL( )

i) intrinsic delay (CL = 0)

Rsw = kVDD / ID (ON) ~ TOX

Cin ~ 1 / TOX

Cout constant

τ int ~ constant

ii) loaded delay (CL > 0)

τ loaded ≈ RswCLτ loaded ↑ as TOX ↑

(see Fig. 5.32 of Taur and Ning)


effect of L on delay


Rsw = kVDD / ID (ON)

Cin ~ LCout ,CL constant

τ ↑ as L ↑


ID (ON ) =W COXυ(0) VGS −VT( )↓ as L ↑

Rsw ↑ as L ↑


effect of VDD on delay

Rsw = kVDD / ID (ON)

τ ~1

1−VT VDD

ID (ON ) =W COXυ(0) VGS −VT( )Rsw ~ VDD VDD −VT( )

Rsw ~ 1 1−VT VDD( )


Cout = εSi WD ~ 1 VDD +Vbi


delay vs. VDD

τ ~1

1−VT VDD


VDDVT

τ

fixed VT

VT VDD = 0.2

ID (off) ~ e−qVT /mkBT


power-delay trade-off

τ ~ VDD VDD −VT( ) f ~ 1−VT VDD( )

Pstatic ~ ID (OFF)VDD ~ e−qVT /mkBTVDD

Pdynamic = α fCTOTVDD2 ~ VDD

2 1−VT VDD( )

circuit speed:

dynamic (switching) power:

static (leakage) power:


power-delay trade-off

VDD

VT

Pdynamic ~ VDD2 1−VT VDD( )


Pstatic ~ e−qVT /mkBTVDD

speed ~ 1−VT VDD( )

increasing speed

decreasing active power

decreasing leakage power

HP

LSP


Outline

1) Review

2) Speed

3) Power




key metrics

1) Switching energy: ES =12

CVDD2

2) Switching delay: τ S =CVDD

ID (ON)

3) Dynamic power: PD = α f CVDD2

4) Energy-delay product: ESτ =12

C 2VDD3

ID (on)


the energy-delay metric

Energy-delay product:

ESτ =12

C 2VDD3

ID (on)~

VDD3

VDD −VT( )

Minimum energy-delay product:

( ) 0 1.5S optDD T

DD

EV V

Vτ∂

= ⇒ =∂


device metrics for 65 nm technology node

1) Switching energy: ES =12

CVDD2 ≈ 21 aJ

2) Switching delay: τ S =CVDD

ID (ON)= 0.64 ps

3) Dynamic power: PD = α f CVDD2

4) Energy-delay product: ESτ =12

C 2VDD3

ID (on)= 1.4 ×10−29 J-s


circuit performance (high-speed logic)

Typical power dissipation of a logic chip: 100 W

Dissipation of logic core: ≈ 20 W

Pcore = NcoreCSVDD

2

2fα = 107 ×

CS ×12

2× 4 ×109( )×10−1

Energy-delay product: ESτ ≈ 1.5 ×10−24 J-s

ES ≈CSVDD

2

2

CS ≈ 10 fF/node

Average switching energy: = 6,000 aJ


device circuit increase

delay:

switching energy:

energy-delay:

from device to circuit

0.64 ps 250 ps ~ 400 ×

21 aJ 6000 aJ ~300 ×

~ 10−29 J-s ~ 10−24 J-s ~100,000 ×


Outline

1) Review

2) Speed

3) Power




conclusions / questions

1) Device metrics aren’t enough; the circuit is critical.

2) How close is CMOS to fundamental limits?

ee-612: lecture 25: cmos circuits: part 2reza2/courses/491/slides/05-c... · 2008-01-21 ·...

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