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EE 290A – Sequential Optimization EE 290A – Sequential Optimization and Verificationand Verification

http://www-cad.eecs.berkeley.edu/~alanmi/courses/290A/index.htm

Tues. Thurs. 9:30-11 Cory 540 A/B3 hours credit

Instructors:Robert BraytonRoland Jiang

Alan Mishchenko

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OutlineOutline

IntroductionIntroduction ScheduleSchedule Latches and Flip-flopsLatches and Flip-flops Verification of a clock-scheduleVerification of a clock-schedule

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Requirements Attend class and participate in discussions Do research on an individual project

collaborating with a mentor Give two presentations on your project –

preliminary overview (March 3) and final project lecture – (May 10, 12)

lecture should be similar to a conference presentation of 20-25 minutes

Final project report (May 20) should be similar to a conference paper

Learn a lot and have fun

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Web site contentsWeb site contents NewsNews (probably we will send out e-mail to class roster instead of (probably we will send out e-mail to class roster instead of

posting here)posting here) GeneralGeneral OverviewOverview SyllabusSyllabus (rough and preliminary description of course content) (rough and preliminary description of course content) LecturesLectures (lectures will be posted here – hopefully before the (lectures will be posted here – hopefully before the

class)class) ExamplesExamples (this contains examples on which some CAD (this contains examples on which some CAD

programs can be applied)programs can be applied) ReadingReading (this contains a list of relevant papers for more info.) (this contains a list of relevant papers for more info.) ProjectsProjects (some proposed ones are here already with mentors but (some proposed ones are here already with mentors but

this list is preliminary. Final list will be given out early in this list is preliminary. Final list will be given out early in February)February)

SummarySummary

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Computing ResourcesComputing Resources

All students will be given an account on the All students will be given an account on the CAD computers – if don’t have one see CAD computers – if don’t have one see Roland JiangRoland Jiang These can be used to run programs – These can be used to run programs –

MVSIS, VIS, SIS, ESPRESSO, SPICE… MVSIS, VIS, SIS, ESPRESSO, SPICE… on exampleson examples

Used for project workUsed for project work

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Coordination with 219B – Coordination with 219B – Logic Synthesis 8-9:30 Tues. Thurs.Logic Synthesis 8-9:30 Tues. Thurs. Schedule with 219B has been coordinated with Prof. Schedule with 219B has been coordinated with Prof.

Kuehlmann so some basic material will be presented there Kuehlmann so some basic material will be presented there prior to use in 290A.prior to use in 290A. Required that 219B schedule to be changed from Required that 219B schedule to be changed from

previous years.previous years. This makes it possible to take both courses at the same This makes it possible to take both courses at the same

timetime This makes it possible to just take 290A without having This makes it possible to just take 290A without having

taken 219B – just make sure you attend 219B when taken 219B – just make sure you attend 219B when basic material is taught.basic material is taught.

Other than this dependency, 290A is self contained.Other than this dependency, 290A is self contained. Auditors are welcome to attend classes and can opt to do a Auditors are welcome to attend classes and can opt to do a

project.project.

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Sequential OptimizationSequential Optimization Much research exists – lots of effort in ’90sMuch research exists – lots of effort in ’90s Could lead to important improvements in area Could lead to important improvements in area

performance etc.performance etc. Interesting work from a theoretical standpointInteresting work from a theoretical standpoint

Not really used in commercial CADNot really used in commercial CAD except retimingexcept retiming Computationally expensive and therefore a lot Computationally expensive and therefore a lot

of techniques can only be applied to small of techniques can only be applied to small examplesexamples

Optimization use restricted by need to verify.Optimization use restricted by need to verify.

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Sequential VerificationSequential Verification Big area and a lot of current workBig area and a lot of current work Abstraction methods help in scalability to Abstraction methods help in scalability to

larger problemslarger problems Interesting theoretical foundationsInteresting theoretical foundations Lots of commercial interest in CAD Lots of commercial interest in CAD

companies and in system design houses.companies and in system design houses. Recent SAT-based methods have increased Recent SAT-based methods have increased

capability (also applied to optimization)capability (also applied to optimization)

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Purpose of CoursePurpose of Course

Only very small subset has been taught previouslyOnly very small subset has been taught previously Bring into focus best state-of-the-art methods to Bring into focus best state-of-the-art methods to

get synergistic viewget synergistic view See if these can be integrated and advanced in See if these can be integrated and advanced in

light of recent advancements in logic synthesis light of recent advancements in logic synthesis and verificationand verification

Expose fruitful directions of researchExpose fruitful directions of research Create a few conference papers.Create a few conference papers.

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OutlineOutline

IntroductionIntroduction ScheduleSchedule Latches and Flip-flopsLatches and Flip-flops Verification of a clock-scheduleVerification of a clock-schedule

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ScheduleSchedule Week 1 (January 18-20)Week 1 (January 18-20)

Jan 18: Introduction, latches and flipflops, clock schedule analysis Jan 18: Introduction, latches and flipflops, clock schedule analysis (Bob)(Bob)

Jan 20: Basics of reachability analysis (Alan)Jan 20: Basics of reachability analysis (Alan) Week 2 (January 25-27)Week 2 (January 25-27)

Jan 25: Cyclic circuits – Part 1 (Roland)Jan 25: Cyclic circuits – Part 1 (Roland) Jan 27: Cyclic circuits – Part 2 (Roland)Jan 27: Cyclic circuits – Part 2 (Roland)

Week 3 (February 1-3)Week 3 (February 1-3) Feb 1: Asynchronous synthesis – Part 1 (Alex Kondratyev, CBL)Feb 1: Asynchronous synthesis – Part 1 (Alex Kondratyev, CBL) Feb 3: Asynchronous synthesis – Part 2 (Alex Kondratyev, CBL)Feb 3: Asynchronous synthesis – Part 2 (Alex Kondratyev, CBL)

Week 4 (February 8-10)Week 4 (February 8-10) Feb 8: Asynchronous synthesis – part 3 (Alex Kondratyev, CBL)Feb 8: Asynchronous synthesis – part 3 (Alex Kondratyev, CBL) Feb 10: Clocking networks (Rajeev Murgai, Fujitsu)Feb 10: Clocking networks (Rajeev Murgai, Fujitsu)

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ScheduleSchedule Week 5 (February 15-17)Week 5 (February 15-17)

Feb 15: State-based FSM manipulations – Advanced reachability Feb 15: State-based FSM manipulations – Advanced reachability (Alan)(Alan)

Feb 17: State-based FSM manipulations – Sequential flexibility Feb 17: State-based FSM manipulations – Sequential flexibility (Alan)(Alan)

Week 6 (February 22-24)Week 6 (February 22-24) Feb 22: State-based FSM manipulations – State minimization Feb 22: State-based FSM manipulations – State minimization

(Alan)(Alan) Feb 24: Structure-based FSM manipulations – Clock skewing Feb 24: Structure-based FSM manipulations – Clock skewing

(Alan / Aaron Hurst)(Alan / Aaron Hurst) Week 7 (March 1-3)Week 7 (March 1-3)

Mar 1: Structure-based FSM manipulations – Retiming (Alan)Mar 1: Structure-based FSM manipulations – Retiming (Alan) Mar 3: Preliminary project presentations (290A students)Mar 3: Preliminary project presentations (290A students)

Week 8 (March 8-10)Week 8 (March 8-10) Mar 8: Structure-based FSM manipulations – Initialization Mar 8: Structure-based FSM manipulations – Initialization

sequences, peripheral retiming (Roland)sequences, peripheral retiming (Roland) Mar 10: Structure-based FSM manipulations – Inherent power of Mar 10: Structure-based FSM manipulations – Inherent power of

retiming and resynthesis (Roland)retiming and resynthesis (Roland)

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ScheduleSchedule Week 9 (March 15-17)Week 9 (March 15-17)

Mar 15: Structure-based FSM manipulations – Sequential testing and Mar 15: Structure-based FSM manipulations – Sequential testing and redundancy removal (Bob)redundancy removal (Bob)

Mar 17: Structure-based FSM manipulations – High-level retiming (Bob)Mar 17: Structure-based FSM manipulations – High-level retiming (Bob) Week 10 (spring break)Week 10 (spring break) Week 11 (March 29-31)Week 11 (March 29-31)

Mar 29: Structure-based FSM manipulations – Retiming and technology Mar 29: Structure-based FSM manipulations – Retiming and technology mapping (Alan)mapping (Alan)

Mar 31: Structure-based FSM manipulations – Sequential optimization Mar 31: Structure-based FSM manipulations – Sequential optimization w/o reachability (Alan)w/o reachability (Alan)

Week 12 (April 5-7)Week 12 (April 5-7) Apr 5: Formal verification – Temporal logic, omega automata, language Apr 5: Formal verification – Temporal logic, omega automata, language

containment (Bob)containment (Bob) Apr 7: Formal verification – Bounded model checking, temporal Apr 7: Formal verification – Bounded model checking, temporal

induction (Alan)induction (Alan) Week 13 (April 12-14)Week 13 (April 12-14)

Apr 12: Formal verification – Unbounded model checking – Part1 (Ken Apr 12: Formal verification – Unbounded model checking – Part1 (Ken McMillan, CBL)McMillan, CBL)

Apr 14: Formal verification – Unbounded model checking – Part2 (Ken Apr 14: Formal verification – Unbounded model checking – Part2 (Ken McMillan, CBL)McMillan, CBL)

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ScheduleSchedule Week 14 (April 19-21)Week 14 (April 19-21)

Apr 19: Formal verification – Sequential equivalence checking – Apr 19: Formal verification – Sequential equivalence checking – Part1 (Roland)Part1 (Roland)

Apr 21: Formal verification – Sequential equivalence checking – Apr 21: Formal verification – Sequential equivalence checking – Part2 (Roland)Part2 (Roland)

Week 15 (April 26-28)Week 15 (April 26-28) Apr 26: Formal verification – Functional dependency (Roland)Apr 26: Formal verification – Functional dependency (Roland) Apr 28: GALS and Latency Insensitive Design (Bob)Apr 28: GALS and Latency Insensitive Design (Bob)

Week 16 (May 3-May 5)Week 16 (May 3-May 5) May 3: Other topicsMay 3: Other topics May 5: Other topicsMay 5: Other topics

Week 17 (May 10)Week 17 (May 10) May 10: Final project presentations – Part1 (290A students)May 10: Final project presentations – Part1 (290A students) May 12: Final project presentations – Part2 (290A students)May 12: Final project presentations – Part2 (290A students)

May 13 – 20 Final examinations periodMay 13 – 20 Final examinations period May 20:May 20: Hand in Final Project Reports Hand in Final Project Reports

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OutlineOutline

IntroductionIntroduction ScheduleSchedule Latches and Flip-flopsLatches and Flip-flops Verification of a clock-scheduleVerification of a clock-schedule

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Latches and Flip-flops

Bi-stable circuit (no inputs)

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SR Latch (bi-stable circuit with control)

R

S Q

Q

* *

*

*

Assumption: 0

,

RS

QRS Q S Q

R

RQ

Q

SQ

R\SQR\SQ 0000 0101 1111 1010

00 00 11 11 11

11 00 00 XX XX

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D latch

C

D

Q

Q

D

C Q

Q

symbol

* ( )

R CD

S CD

Q S RQ CD C D Q CD CQ

S

R

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D flip-flop

When When CC is asserted (= 1) is asserted (= 1) Old value of is captured in slaveOld value of is captured in slave Master is openedMaster is opened follows the follows the DD input input

When When CC is de-asserted (= 0) is de-asserted (= 0) Master is closed and Master is closed and DD value is captured in master value is captured in master Slave is openedSlave is opened Transmits the output from the masterTransmits the output from the master

DC

Q DC

Q

Q

C

D

master slave

Q

Q

Q

Q

*Q S RQ CD CQ

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Summary of latch and flip-flop characteristics

SR latchSR latch Gated SR latchGated SR latch D latchD latch SR flip-flopSR flip-flop D flip-flopD flip-flop JK flip-flopJK flip-flop T flip-flop (edge triggered)T flip-flop (edge triggered) T flip-flop (clocked)T flip-flop (clocked)

*

*

*

*

*

*

*

*

Q S RQ

Q SC QR CQ

Q DC CQ

Q S RQ

Q D

Q KQ JQ

Q Q

Q TQ TQ

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Set-up and hold times

Set-up timeSet-up time Time during which data must be stable Time during which data must be stable

before the clock comesbefore the clock comes Hold timeHold time

Time during which data must be stable Time during which data must be stable after the clock comesafter the clock comes

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Analog analysis Assume pure CMOS thresholds, 5V railAssume pure CMOS thresholds, 5V rail Theoretical threshold center is 2.5 VTheoretical threshold center is 2.5 V

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Analog analysis

outV

inV

( )out inV T V

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Metastability

21 uin o tVV

12 uin o tVV

stablestable

stablestable

metastablemetastable

Metastability is inherent in any bi-stable system

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Metastability - dynamics

21 uin o tVV

12 uin o tVV

SeparatrixSeparatrix

stablestable

stablestable

metastablemetastable

D-latch operation

latch acts like a wire while its control is activelatch (later) grabs data when control changes

D-latch timing parameters

• Propagation delay (from C or D)• Setup time (D before C edge)• Hold time (D after C edge)

metastability

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Metastability - dynamics

21 uin o tVV

12 uin o tVV

SeparatrixSeparatrix

stablestable

stablestable

metastablemetastable

C

D

Q

Q

S

R

Pos.-edge-triggered D flip-flop behavior

DC

Q DC

Q

Q

C

D

master slave

D flip-flop timing parameters

• Propagation delay (from CLK)• Setup time (D before CLK)• Hold time (D after CLK)

metastability

Outline

• Introduction• Schedule• Latches and Flip-flops• Verification of a clock-schedule

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Timing verification of Timing verification of synchronous circuitssynchronous circuits

““checkTc and minTc: Timing Verification of Optimal checkTc and minTc: Timing Verification of Optimal Clocking of Synchronous Digital Circuits”, K. Clocking of Synchronous Digital Circuits”, K. Sakallah,T. Mudge and O. OlukotunSakallah,T. Mudge and O. Olukotun

““Verifying Clock Schedules”, T. Szymanski and N. Verifying Clock Schedules”, T. Szymanski and N. Shenoy.Shenoy.

Sakallah et. al. formulationSakallah et. al. formulation Handles arbitrary multi-phase clocksHandles arbitrary multi-phase clocks Captures signal propagation along short as well Captures signal propagation along short as well

as long pathsas long paths Simple formulationSimple formulation

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Clocking systemClocking system

A set of clock A set of clock kk phases phases A set of A set of nn D-latches D-latches Assume that all clock phases are active Assume that all clock phases are active

high, i.e. are transparent when clock is highhigh, i.e. are transparent when clock is high Data is captured when clock transits low.Data is captured when clock transits low.

1( ,..., )kC

1( ,..., )lL L L

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ParametersParameters

number of latches in circuitnumber of latches in circuit

clock phase controlling latch clock phase controlling latch ii

setup time of latch setup time of latch ii

hold time of latch hold time of latch ii

minimum combinational delay from latch minimum combinational delay from latch ii to to latch latch jj

maximum combinational delay from latch maximum combinational delay from latch ii to to latch latch jj

n

ip

iS

iH

ij

ij

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Variables Defining Clock ScheduleVariables Defining Clock Schedule

clock periodclock period

length of time that clock phase length of time that clock phase ii is active is active

absolute time within first period when phase absolute time within first period when phase ii begins, i.e. when clock phase rises. begins, i.e. when clock phase rises. (different from Szymanski paper)(different from Szymanski paper)

iw

ie

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Other VariablesOther Variablestime between start of phase time between start of phase ii and and nextnext phase phase jjearliest signal arrival time at latch earliest signal arrival time at latch ii (relative to start (relative to start

time of time of ppii))

latest signal arrival time at latch latest signal arrival time at latch ii (relative to start (relative to start time of time of ppii))

earliest signal departure time from latch earliest signal departure time from latch ii (relative to (relative to start time of start time of ppii))

latest signal departure time from latch latest signal departure time from latch ii (relative to (relative to start time of start time of ppii))

ijE

ia

iA

id

iD

All arrival and departure times are in their local time frame where the origin is at ei (i.e. ti

local= 0 when t = ei + n). Eij is used to translate between time frames.

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Equations and ConstraintsEquations and Constraints if

otherwise

j i j i

ijj i

e e e eE

e e

i

j

0

ei

ej

wi

wj

Note: here and

Note:

ij j i ji i j

ii

E e e E e e

E

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max(0, )i id a

max(0, )i iD A

i

j

0

ei

ej

wi

wj

Data departs latch input when it arrives and the latch is

transparent:

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min ( )j ii j i j ji p pa d E max ( )

j ii j i j ji p pA D E

pi

pj

0

ei

ej

wi

wj

ji

dj

pjpi

ji

Dj

pjpi

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Constraints for Correct OperationConstraints for Correct Operation

i i iA w S

pi

pj

0

ei

ej

wi

wj

max

max(0, )

max

(0

(

)

(0 ),

,

)

j j ji i i i

j

j ji i

ji j

i

i i

i i i

i j

i

e A e w S

A w S

w S

A w

E

e e

A

S

setup

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Constraints for Correct OperationConstraints for Correct Operationi i ia w H

pi

pj

0

ei

ej

wi

wj

max

max(0, )

max(0

(0,

, ( )

)

)

j j ji i i i

j ji i i

i i

i

j ji ji

i

i i

je e

a E

e a e w H

a w H

w H

a w H

hold

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Verification and OptimizationVerification and Optimization

Clock schedule optimization problem: find the minimum value of for which there is an assignment to all variables (including w and e) consistent with the constraints.

Clock schedule verification problem: Given values for w and e, find values for the rest of the variables that satisfy the constraints.

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Iterative constructionIterative construction

0 0

1

1

max( ,0)

max( ,0)

min ( )

max ( )

i i

m mi i

m mi i

m mi j i j ji ji

m mi j i j ji ji

a A

d a

D A

a d E

A D E

Note: • a solution is a fixed point• iteration from below• both min and max times are computed simultaneously

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LemmasLemmas

1. For all i and m > 0, (monotone increasing)

2. Let be a solution. Then for all i, m > 0,

3. If for some i, then the equations have no solution. (n is # latches)

4. If the iteration converges, then it converges to the minimum solution.

1 1 1 1, , ,m m m m m m m mi i i i i i i ia a A A d d D D

( , , , )a A d D 1 1 1 1, , ,m m m m

i i i i i i i ia a A A d d D D 1 1 or n n n n

i i i id d D D

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Uniqueness resultsUniqueness resultsThe construction is run to find a solution to the

equations, and then this solution is checked to see if it satisfies the setupsetup and holdhold inequalities. But what if there is not a unique solution? There can be multiple solutions If there is more than one solution, then the clock

period is optimum If there is more than one solution, then some of

those violate the setup constraints. The minimum solution is the “correct” one

because if we slow down the clock by just , all other solutions disappear.

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ExampleExample

Latch 1S = 2H = 3

= = 10

= 10

8 2

max( ,0)

max( ,0)

max ( )

min ( )

i i

i i

i j i j ji ji

i j i j ji ji

D A

d a

A D E

a d E

ii iA Sw i i iHa w

E11 =

Try = 10 +

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TheoremTheorem

If If is optimum, then there exists a cycle, is optimum, then there exists a cycle, jj00,j,j11,,

…,j…,jkk = j = j00 such that such that

1 1

1 1

0 0i i i i

k k

j j j ji i

E

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Pseudo codePseudo codefor each with 1 do

for 1 step 1 until

for each with 1 do

max( ,0)

max( ,0)

for each with 1 do

i i

i i

i i

i i n

A a

m m n

i i n

D A

d a

i i n

( ,max ( ))

( ,min ( ))

if no or changed during this pass, then

return "al

m

gorithm converged"

return "algorithm dive

a

rged"

x

max

i i j i j ji ji

i i j i j ji ji

i i

A A D E

a a d E

A a

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Experience (Szym. & Shen)Experience (Szym. & Shen)

Run in ISCAS’89 benchmarks Largest circuit had 3272 latches and 67704

edges Run time on this largest example was 20

sec., (1992 computers) most of which was spent reading in the circuit.

Typically only a few iterations were needed for convergence.

j i