Last Revised: 11/10/2016 1

EE 209 Project Part 1 – Find Your Roots

1 Introduction In this project you will complete the control unit and datapath for an integer square root engine. You should work on this lab INDIVIDUALLY!

2 What you will learn This lab is intended to teach you how to implement state machines, use datapath components and perform a non-trivial digital design.

3 Background Information and Notes 1. The Algorithm

To find the square root of a number, x, we can start with an upper and lower bound (ie. hi and lo, respectively) and perform a binary search of the number line, making a guess (which will be the midpoint) between hi and lo, squaring our guess and comparing that result to x itself. If the square of our guess is larger than x we know the real root is between lo and our guess (the midpoint) and thus can tighten our bounds. If the square of our guess is smaller than x, we know the real root is between our guess and hi. As we continue to tighten our bounds we will eventually get to the point where lo and hi differ by only 1 at which point we can return lo (which will either have the exact answer or the floor [rounded-down result] of the exact answer). A software implementation is shown below. We assume x is a 16-bit unsigned number in the range 0 to 64,000 and thus we know the initial bounds of the square root of x must be between 1 and 255.

int sqrt(x)

{

unsigned char hi=255, lo=1;

while(hi-lo > 1){

int guess = (hi+lo)/2;

if(guess*guess > x)

hi = guess;

else

lo = guess;

}

return lo;

}

EE 209 Project Part 1 - Find Your Roots

2 Last Revised: 11/10/2016

2. Block Diagram Below is the high level block diagram of the system you are to design. The user will provide a 16-bit input, X, and keep it constant while the computation takes place. The computation should start when the START signal is asserted. When the result is correctly computed, assert the DONE signal. To reuse the design, the user will assert the START signal for 2 clock cycles.

SQRT

x[15:0]

clk

reset

start

ans[7:0]

(SQRT)

done

3. The Datapath You will need to design the datapath for computing the square root. We provide you a:

mul8x8: 8x8 unsigned multiplier (yields a 16-bit unsigned output)

mux21_8bit: 2-to-1, 8-bit wide mux

comp8: 8-bit comparator

comp16: 16-bit comparator

reg8e: 8-bit register with enable

adder8: 8-bit adder

dff1s: 1-bit DFF

4. The “Incomplete” Control Unit

START

Init

START

On Reset

(power on)

DONE

DONE=1(ANS must be

valid during this

state)

START

START

...

Figure 1 – State Machine (You will need to define states other than INIT and DONE)

EE 209 Project Part 1 - Find Your Roots

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You will need to determine what other states, inputs, and outputs are required to make your design work. However, at the very least you MUST FOLLOW these requirements. You must have an initial state that should wait for a start signal to be asserted. You are welcome to do some initialization tasks in this state if you wish. The Done state simply allows us to notify the user that we are done (via the done signal) and that the result coming out of the ans signal is valid. We wait until the user turns start on again to move to Init (note the user would have to leave start on for 2 clock signals to move from the Done state to computing the next square root).

4 Procedure You will design and implement the square root system including the control unit / FSM and the datapath. You should also write a testbench “from scratch” to verify your operation. For part 1 we will only use simulation to ensure a working design. 1. Download the sqrt1 project .zip. Extract the files to a folder.

2. Describe your datapath and control unit in the sqrt.v

3. Use the general state diagram shown earlier but now define the actual outputs

that are needed to control the datapath (in addition to the DONE signal which is a primary output of the overall system).

4. Write your testbench sqrt_tb.v to simulate your design. We suggest testing

a few possible input numbers some small and some larger (e.g. 30, 64, 81, and 60000). Verify the correctness of your design.

5. Once you are satisfied your design works, go back to the ‘Implementation’ view,

select your top-level sqrt.v file, and synthesize your design. Ensure it synthesizes without errors (warnings are okay). Then, at the top of the processes pane, click on “Design Summary/Reports” and in the right window select “Synthesis Report” (see the screen capture below). Scroll through and read the output of this report. In particular, look at the “Final Report” about 2/3 of the way down. In this section you will find the ‘Device Utilization summary’ which indicates the size/area of your design (i.e. how much of the FPGA’s resources your design is using). Below that will be the timing report which will list the critical path and its delay (which sets the frequency at which you could run this design). Answer the questions in the review section below through your examination of these areas.

EE 209 Project Part 1 - Find Your Roots

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6. Submit your design file and testbench file as well as your answers to the review questions below (in a file name review.txt) via the link on the website.

5 Review 1. In the synthesis report, how many flip-flops does your design use? How

many 4-input LUTs? How many flip-flops and 4-input LUTs are available on our FPGA?

2. Examine the timing report. What is the minimum period and maximum frequency at which we can run this design?

3. In the timing report what is the critical path’s starting and ending point (i.e. which registers/flip-flops)? Look at the in->out pathway description. What major components does your critical path lead through?

EE 209 Project Part 1 - Find Your Roots

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6 EE 209 Project Part 1 Grading Rubric Student Name: _______________________________________________________

Item Outcome Score Max.

Datapath Correctness

Guess produced correctly

Correct comparison of guess*guess w/ X

Appropriate register (hi or lo) is chosen to update

STOP check is performed correctly

Yes / No

Yes / No

Yes / No

Yes / No

1

1

1

1

FSM

Done Produced correctly

1st computation started correctly

Subsequent computation started correctly when

START held high 2 successive cycles

Subsequent computation started correctly when

START applied in non-consecutive cycles

Yes / No

Yes / No

Yes / No

Yes / No

1

1

1

1

Test Cases

Test Case 1

Test Case 2

Yes / No

Yes / No

1

1

SubTotal 10

Late Deductions (-1 pts. per day)

Total 10

Open Ended Comments: