EE 201A/EE298

Modeling and Optimization for VLSI Layout

Instructor: Lei He

Email: LHE@ee.ucla.edu

Outline

Course logisticsCourse logistics

OverviewOverview What are covered in the courseWhat are covered in the course What are interesting trends for physical designWhat are interesting trends for physical design

Instructor Info

Email: LHE@ee.ucla.eduEmail: LHE@ee.ucla.edu Phone: 310-206-2037Phone: 310-206-2037 Office: Engineering IV 68-117Office: Engineering IV 68-117 Office hours: Tu/Th 2-3pm or by Office hours: Tu/Th 2-3pm or by

appointmentappointment The best way to reach me: The best way to reach me:

Email with EE201 in subject lineEmail with EE201 in subject line

About this Course

One of selective course for EE’s ECS Major Field StudentsOne of selective course for EE’s ECS Major Field Students Question in M.S. comprehensive exam / PhD prelimsQuestion in M.S. comprehensive exam / PhD prelims Offered every other springOffered every other spring Will be under another course number (EE205B)Will be under another course number (EE205B)

Related coursesRelated courses Mani’s EE202A Embedded Computing Systems (Fall)Mani’s EE202A Embedded Computing Systems (Fall) Ingrid’s EE201A on Advanced VLSI (Spring)Ingrid’s EE201A on Advanced VLSI (Spring) Bill M-S’s EE204A on Compilers (Winter)Bill M-S’s EE204A on Compilers (Winter) My EE205A Fundamental to CAD (Winter)My EE205A Fundamental to CAD (Winter)

Mani’s EE206A Wireless Systems (Spring)Mani’s EE206A Wireless Systems (Spring) My EE205B (every other Spring)My EE205B (every other Spring)

Course Prerequisites

Official prerequisiteOfficial prerequisite EE116BEE116B VLSI System DesignVLSI System Design But mainly self-containedBut mainly self-contained

Knowledge to help you appreciate moreKnowledge to help you appreciate more CS180CS180 Introduction to algorithmsIntroduction to algorithms

EE205A and EE205B EE205A Fundamental to CAD of embedded systemsEE205A Fundamental to CAD of embedded systems

System level performance/power/thermal modeling and System level performance/power/thermal modeling and optimizationoptimization

Synthesis – scheduling and allocation, logic optimization Synthesis – scheduling and allocation, logic optimization and technology mappingand technology mapping

FPGA circuits and architectures and placement and FPGA circuits and architectures and placement and routing for FPGArouting for FPGA

EE205B Modeling and Optimization for VLSI EE205B Modeling and Optimization for VLSI layoutlayout Advanced algorithms for physical designAdvanced algorithms for physical design

Fundamentals of combinatorial algorithmFundamentals of combinatorial algorithm Detailed performance, signal integrity, power and thermal Detailed performance, signal integrity, power and thermal

modelsmodels Incorporating physical design into system designIncorporating physical design into system design

System Specification

Functional Design

Logic Design

Circuit Design

X=(AB*CD)+(A+D)+(A(B+C))

Y=(A(B+C))+AC+D+A(BC+D))

VLSI Design Cycle

Physical Design

Fabrication

Packaging

VLSI Design Cycle (cont.)

Partition

Floorplanning

Placement

Simplified Physical Design Cycle

Routing

Extraction and Verification

Front-endFront-end

physical designphysical design

Back-endBack-end

physical designphysical design

Course Outline and Schedule

Front-end physical design (4.5 weeks)Front-end physical design (4.5 weeks) Partitioning, floorplanning and placementPartitioning, floorplanning and placement Power and thermal modelingPower and thermal modeling Algorithms: divided and conquer, simulated annealing, genetic algorithmAlgorithms: divided and conquer, simulated annealing, genetic algorithm Project proposal due by end of fifth weekProject proposal due by end of fifth week

Back-end physical design (4.5 weeks)Back-end physical design (4.5 weeks) Interconnect extraction and modeling Interconnect extraction and modeling Interconnect synthesisInterconnect synthesis Noise modeling and avoidanceNoise modeling and avoidance Clock and power supply design **Clock and power supply design ** Algorithms: dynamic programming, linear programmingAlgorithms: dynamic programming, linear programming Project report due the last day of the quarterProject report due the last day of the quarter

ACM IEEE Design Automation Conference (DAC)

http://www.dac.com (San Diego, Young student program)

International Conference on Computer Aided Design(ICCAD)

Design, Automation and Test in Europe (DATE)

Asia and South Pacific Design Automation Conference (ASP-DAC)

International symposium on physical design (ISPD)

International symposium on low power electronics and design

International symposium on field programmable gate array

IEEE International Symposium on Circuits and Systems (ISCAS)

Related VLSI CAD Conferences

IEEE Transactions on CAD of Circuits and systems (TCAD)

ACM Trans. on Design Automation of Electronic Systems (TODAES)

IEEE Transactions on Circuits and Systems (TCAS)

IEEE Trans. on VLSI Systems (TVLSI)

IEEE Trans. on Computer

Integration

Algorithmica

SIAM journal of Discrete and Applied Mathematics

Related VLSI CAD Journals

Synposys, Cadence, Magma, Mentor Graphics, …

Over hundreds companies have booths at DAC

Two of them are among the ten biggest software companies in the world

But they are smaller than the biggest spin-off of EDA

EDA is regarded as A-graded bonds for Venture Capitalists

One of few IT segments still recruits heavily and offers salary higher than Intel/IBM

EDA system is regarded as one of the most complicated software systems mankind ever built

Money Talk for VLSI CAD

References for this Course

Selected papers from TCAD, TODAES, and major CAD Selected papers from TCAD, TODAES, and major CAD conferences such as DAC, ICCAD and ISPDconferences such as DAC, ICCAD and ISPD

Naveed A. Sherwani, "Algorithms for VLSI Physical Design Naveed A. Sherwani, "Algorithms for VLSI Physical Design Automation", 3rd Edition, 1998.Automation", 3rd Edition, 1998.

H. Cormen, et al “Introduction to Algorithms” MIT H. Cormen, et al “Introduction to Algorithms” MIT Electrical Engineering and Computer Science Series 1990.Electrical Engineering and Computer Science Series 1990.

H. Bakoglu, H. Bakoglu, Circuits, Interconnects, and Packaging for VLSICircuits, Interconnects, and Packaging for VLSI, , Addison WesleyAddison Wesley

Cong et al., Performance Optimization of VLSI Interconnect Cong et al., Performance Optimization of VLSI Interconnect Layout, Layout, Integration, the VLSI JournalIntegration, the VLSI Journal 21 (1996) 1--94. 21 (1996) 1--94.

Grading Policy

HomeworkHomework 15%15% Midterm (7Midterm (7thth week) week) 20%20% Course presentationCourse presentation 15%15% Term projectTerm project 50%50%

A A score > 85 and programming project score > 85 and programming project

Course Presentation (15%)

2~3 student a team2~3 student a team Survey an area (topics and resources specified by me Survey an area (topics and resources specified by me

on a continual basis)on a continual basis) Prepare slides and do a 30-35 minute presentation in Prepare slides and do a 30-35 minute presentation in

the classthe class slides prepared jointlyslides prepared jointly either all students share the presentation or I will select the either all students share the presentation or I will select the

speaker randomly at the presentation timespeaker randomly at the presentation time

Prepare a web site that should contain a report based Prepare a web site that should contain a report based on your survey, a bibliography, and links to resources on your survey, a bibliography, and links to resources and of course your slidesand of course your slides

Term Project (50%)

One of the following two:One of the following two: One-person survey and critic of selected topic (at most 35%)One-person survey and critic of selected topic (at most 35%) Individual programming project for a team of 2 to 3 personsIndividual programming project for a team of 2 to 3 persons

Coupled system design and physical designCoupled system design and physical design Floorplanning with thermal constraintsFloorplanning with thermal constraints 3D modeling and physical design3D modeling and physical design Or any topic agreed by instructorOr any topic agreed by instructor

Up to 30 minute presentation during the finals week, Up to 30 minute presentation during the finals week, like a conference talk like a conference talk

Up to 12 page report in the style of a technical Up to 12 page report in the style of a technical conference paperconference paper

ACM style ACM style http://www.acm.org/sigs/pubs/proceed/template.htmhttp://www.acm.org/sigs/pubs/proceed/template.htm

Who should take this course

It is another courseIt is another course Discuss wide scope of knowledgeDiscuss wide scope of knowledge But research (presentation + project) on your But research (presentation + project) on your

own focusown focus

For students who are motivated toFor students who are motivated to Learn SI, power/thermal for advanced designsLearn SI, power/thermal for advanced designs Learn algorithm basics without taking CS280Learn algorithm basics without taking CS280 Understand CAD betterUnderstand CAD better Become a CAD professionalBecome a CAD professional

More than 10 million transistor

Performance driven designs

Time-to-Market

Design cycle

High performance, high cost

…...

Complexities of Physical Design

Technology (um) 0.25 0.18 0.15 0.13 0.10 0.07Year 1997 1999 2001 2003 2006 2009

# transistors 11M 21M 40M 76M 200M 520MOn-Chip Clock (MHz) 750 1200 1400 1600 2000 2500

Area (mm2) 300 340 385 430 520 620Wiring Levels 6 6-7 7 7 7-8 8-9

Moore’s Law and NTRS

Moore’s LawMoore’s Law The min. transistor feature size decreases by 0.7X every three The min. transistor feature size decreases by 0.7X every three

years (Electronics Magazine, Vol. 38, April 1965)years (Electronics Magazine, Vol. 38, April 1965) True in the past 30 years, and expected to hold for another 10-True in the past 30 years, and expected to hold for another 10-

15 years15 years National Technology Roadmap for Semiconductors National Technology Roadmap for Semiconductors

(NTRS’97)(NTRS’97)

Productivity Gap

xxx

xxx

x 21%/Yr. Productivity growth rate

x

58%/Yr. Complexity growth rate

1

10

100

1,000

10,000

100,000

1,000,000

10,000,000

199810

100

1,000

10,000

100,000

1,000,000

10,000,000

100,000,000

Lo

gic

Tra

nsi

sto

rs/C

hip

(K

)

Tra

nsi

sto

r/S

taff

-Mo

nth

Chip Capacity and Designer Productivity

2003

Source: NTRS’97

Design Challenges in Nanometer Technologies

Interconnect-limited designsInterconnect-limited designs Interconnect performance limitationInterconnect performance limitation Interconnect modeling complexityInterconnect modeling complexity Interconnect reliabilityInterconnect reliability Impact of new interconnect materialsImpact of new interconnect materials

Small feature sizeSmall feature size Process variationsProcess variations Leakage (~50% of total power)Leakage (~50% of total power)

High degree of on-chip integrationHigh degree of on-chip integration Complexity and productivityComplexity and productivity Limitation of current design abstraction and hierarchyLimitation of current design abstraction and hierarchy System on a chip and system in package or 3D technologySystem on a chip and system in package or 3D technology Power/thermal barrierPower/thermal barrier

Complexity of VLSI circuits

Full custom

Performance Size Cost Market time

Standard Cell Gate Array FPGA

Different design styles

Cost ,Flexibility,Performance

Design Styles

Full Custom Design StylePad Metal Via Metal 2

I/OData Path

ROM/RAM

PLA

A/D ConverterRandom logic

Standard Cell Design StyleVDD Metal 1

CellMetal 2

FeedthroughGND

D C C B

A C C

D C D B

C C C B

Cell A

Cell C

Cell B

Cell D Feedthrough cell

Gate Array Design Style (or Structured ASIC)

A

B

C

A

B

C

VDD Metal1 Metal2

Programmable logic Programmable interconnects Programmable inputs/outputs

Field-Programmable Gate-Arrays (FPGAs)

FPGA Design Style

Comparisons of Design Styles

full-custom standard cell gate array FPGA

cell size variable fixed height * fixed fixed

cell type variable variable fixed programmable

cell placement variable in row fixed fixed

interconnections variable variable variable programmable

* uneven height cells are also used

style

Area

Performance

Fabrication layers

style

full-custom standard cell gate array FPGA

compact

high

compact

to moderatemoderate large

high to moderate

moderate low

ALL ALL routing layers

none

Comparisons of Design Styles

Printed Circuit Board PCB

Multi-Chip Module MCM

Wafer Scale Integration WSI or 3D

Packaging

Area

Performance, cost

The increasing complexity and density of the semiconductor devices are driving the development of more advanced VLSI packaging and interconnection approaches.

Packaging Styles

Printed Circuit Board Model

Large number of layers (150a pitch)

Larger area

Low performance

Low cost

PackagePlated through holes

IC ( a )

( b )

MCM Model

Up to 36 layers ( 75a pitch)

Moderate to small area

Moderate to high performance

High cost

Heat dissipation problems

IC ( a )

( b )

Wafer Scale Integration

Small number of layers (VLSI technology- 6a pitch)

Smallest area

Significant yield problems

Very high performance

Significant heat dissipation problems

Comparisons of Packaging Styles

Technology Figure of Merit

(inches/psec. density inches/sq in)

WSI

MCM

PCB

28.0

14.6

2.2

Merit = propagation speed (inches/psec.) * interconnection density (inches/sq. in). Interconnect resistance was not considered

Increasingly on the Same Chip or in the Same Package (SoC and SiP)

SC3001 DIRAC chip (Sirius Communications)SC3001 DIRAC chip (Sirius Communications)

History of VLSI Layout ToolsYear Design Tools

1950 - 1965

1965 - 1975

1975 - 1985

1985 – 1995

1995 -- present

Manual Design

Layout editorsAutomatic routers( for PCB)Efficient partitioning algorithm

Automatic placement toolsWell Defined phases of design of circuitsSignificant theoretical development in all phases

Performance driven placement and routing toolsParallel algorithms for physical designSignificant development in underlying graph theoryCombinatorial optimization problems for layout

Interconnect layout optimization, Interconnect-centric design, physical-logical codesign

One of the new trends: SoC and SiP for 3D technology

Summary Physical design is the most complicated step in the VLSI design Physical design is the most complicated step in the VLSI design

cyclecycle

Physical design is further divided into clustering, partitioning, Physical design is further divided into clustering, partitioning, floorplanning, placement, global and detailed routing. Extraction floorplanning, placement, global and detailed routing. Extraction and verification is an important aspect.and verification is an important aspect.

There are four major design styles -- full custom, standard cell, There are four major design styles -- full custom, standard cell, gate array (structured ASIC), and FPGAs.gate array (structured ASIC), and FPGAs.

There are three alternatives for packaging of chips -- PCB, MCM There are three alternatives for packaging of chips -- PCB, MCM and WSI. But increasingly, we design for SoC and SiP and will use and WSI. But increasingly, we design for SoC and SiP and will use 3D technology3D technology

Automation reduces cost, increases chip density, reduces time-Automation reduces cost, increases chip density, reduces time-to-market, and improves performance.to-market, and improves performance.

CAD tools currently lag behind fabrication technology, which is CAD tools currently lag behind fabrication technology, which is hindering the progress of IC technologyhindering the progress of IC technology

Homework (due April 14th) Read ITRS roadmap executive summary and write one page Read ITRS roadmap executive summary and write one page

summary and critic on one aspect related to your research or summary and critic on one aspect related to your research or fieldfield http://public.itrs.net/Files/2001ITRS/Home.htmhttp://public.itrs.net/Files/2001ITRS/Home.htm

Search literature or web related to SoC, SiP and 3D technology, Search literature or web related to SoC, SiP and 3D technology, summarize five papers on a coherent topic (e.g., technology, summarize five papers on a coherent topic (e.g., technology, design, or CAD) and speculate potential need of CAD researchdesign, or CAD) and speculate potential need of CAD research Following style of conference paperFollowing style of conference paper

With course project proposal in mindWith course project proposal in mind

Submit homework in PDF via emailSubmit homework in PDF via email

Check out course website for notes of future lecturesCheck out course website for notes of future lectures http://eda.ee.ucla.edu/EE201A-04Springhttp://eda.ee.ucla.edu/EE201A-04Spring