EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari1 FRONT-END and HV 1)System architecture: brief summary 2)Status of chips production 3)Front-end board for the wire-chambers: status 4)First prototype of front-end board for GEMs 5)Tests performed 6)Front-end chip for GEMs 7)Radiation hardness 8)Organisation and responsibilities 9)Grounding issues 10)HV EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari2 The LHCb muon electronics project Common project with wire chambers: 1)same far-end structure 2)same front-end board conception: 2 CARIOCA chips + 1 DIALOG chip 3)same bids and producing companies 4)same people BUT 1)CARIOCA CARIOCA GEM 2)front end board (CARDIAC) of different size and layout 3)SPB integrated on the CARDIAC 4)different cables and connectors space requirememnts EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari3 System architecture Triple_GEM det a F/E board 8 PCH ASD 8 LCH DIALOG ON DETECTOR ELECTRONICS I 2 C MASTER LOW VOLTAGE CONTROLS CALIBRATION PULSES SERVICE board (on crates) SYNCHRONIZATION TIME (PHASE) MEASUREMENT DATA FORMATTING DATA TO MUON TRIGGER OFF DETECTOR ELECTRONICS 10m cabling (LVDS) DATA TO DAQ RECONSTRUCTION Counting Room Triple_GEM det b EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari4 CARIOCA Discriminator threshold can be individually set to compensate for offset from process variation internal test structure to inject signal from DIALOG to CARIOCA input; minimum injected charge 50fC only checks if channel ON/OFF At Cdet=15-30pF, t r =8ns, Zin=50, ENC= fC linear up to 200fC shaper, 2pole-zero ion tail cancellation active BLR All differential circuitry, unipolar shaping DC coupled (CERN + CBPF Rio) IBM 0.25 m radiation tolerant technology 8 analog input channels 8 LVDS output channels gain about Cdet=15-30pF VERY SIMILAR CHARACTERISTICS TO ASDQ EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari5 DIALOG generates logical channels by OR-ing of two face-to-face physical channels provides a masking facility to access single channels threshold DAC and line drivers for the CARIOCA chip integrates 16 8-bit DACs with output buffer to set the CARIOCA discriminator threshold with about 0.17fC granularity Programmable delays 31 steps of 1.6ns 50ns max Digital shaping output signal width 8 steps of 3ns 25ns max Front-end rate and noise monitor bits rate counters all functionalities can be controlled via I 2 C interface Triple-voted and auto-corrected register for better SEU immunity INFN -CA IBM 0.25 m radiation tolerant technology 16 LVDS input channels 8 LVDS output channels EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari6 Chip NRE run submission RETICULE: 4 CARIOCA, 2 DIALOG, 1 SYNC 1 CARIOCAGEM. Reticule size 15.3 x 8.1 mm 2 Reticules/wafer ~ 205 Chips per wafer: 820 CARIOCA, 410 DIALOG, 205 SYNC, 205 CARIOCAGEM Expected CARIOCACARIOCAGEMDIALOGSYNCComments NRE wafers Production wafers Needed Assuming 80% yield and 20% spares Submitted in September, Wafers Received in November, Packaged circuits to be delivered next week EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari7 Wire chamber front-end boards CARDIAC 63mm 50mm DCC final DIALOG final CARIOCA CARDIAC 2.0 on wire-chamber More extensively tested 6 layers: signal, GND, LV, signal,GND,signal power consumption 0.5A 1.25W EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari8 CARDIAC About 20 boards of CARDIAC 2.0 produced and tested Good experience now with the PVSS/CANBUS system (Rome I) to communicate with and program the DIALOG chip via I2C bus Many measurements in the Lab (Cagliari and Potenza-Rome1): performance almost OK Experience with CARDIAC 2.0 EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari9 Experience with CARDIAC 2.0 Study of the efficiency and time properties to test: - the front-end electronics reliability; - high rate on the chamber The tests were completely satisfactory Test at GIF (CERN): fully equipped M3R2 wire-chamber 12 CARDIAC boards: The same number of I2C lines as for triple-GEM chambers!!! 2 I2C long lines chains and 1 SB controlled via CANBUS by a PVSS program EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari10 The front end board for GEMs: CARDIAC GEM CARDIACGEM 1.0 : a very first prototype 3 boards assembled Tight space requirements 45x70mm length and 14mm thichkness Two boards in one: FEB+SPB Spark protection on the bottom; the 3 chips on the top Spark protection circuit: only 500V simplified two resistors+2 double diodes -> to be tested (the one of WPC well tested) New type of connectors and cables pitch reduced by half need a special cable 0.635mm pitch top bottom 70mm 45mm I2C LV LVDS EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari11 How the board is plugged in Minimum space available on the top for cables 5-6mm EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari12 Lab tests of CARDIAC (-GEM) Standard lab tests (also at the Company assembling the boards) gain curve S-curve Cdet=15pF Problem: due to process variations spread in gain curve parameters: a)SLOPE b) INTERCEPT If one threshold value for all channels is set, then about 1fC rms effective threshold spread is obtained ENC~05-06fC; not depending on channel position too much for GEMs (we want to trigger at ~2-2.5fC) remember: WPC trigger at 6-7fC much less of a problem EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari13 Lab tests of CARDIAC (-GEM) (II) STRATEGY to reduce the threshold spread: 1)measure noise counts vs. TH curve 2)correct for the intercept spread in two ways: a) equalising minimum thresholds(>0!! in this chip) b) equalising noise count values effective threshold spread is reduced to about 0.5fC(a) or 0.7fC(b) rms This can be done in LHCb and continously monitored! y~erfc(x) EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari14 Lab tests of CARDIAC (-GEM) (III) A further improvement of the threshold spread (reducing it to ~0fC) can be obtained in the lab: 1)measuring directly the gain at the assembling company and keeping a database (foreseen in the contract) G/G(%)=0.5x T( 0 C) =20mV of power supply the same cannot be done for the intercepts since e.g. G/G(%)= 1mV of power supply!!! 20mV in supply voltage moves the intercept by 20% !!!! the slope is much less sensistive than the intercept to supply voltage variations we are lucky that the intercept spread can be compensated for with the other method 2) injecting a calibration pulse on G3down (to be tested) EDR GEM - LNF 5/2/05Walter Bonivento - INFN Cagliari15 Lab Test with GEM chamber (HV off) Count rates on 3 chambers with ~3fC threshold below a kHz (most channels