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RF power silicon-on-glass VDMOSFETNebojsa Nenadovic, Student Member, IEEE, Vittorio Cuoco,Student Member, IEEE, Steven J. C. H. Theeuwen,Hugo Schellevis, Geert Spierings, Antonio Griffo, Marco Pelk, Lis K. Nanver,Member, IEEE, Rik F. F. Jos, and

Jan W. Slotboom,Member, IEEE

Abstract— We have fabricated VDMOSFETs that are designedfor applications in future base station power amplifiers. They aremade in a substrate transfer silicon-on-glass technology. For agate length of 0.8µm and gate width of 350µm the fT /fmax is6/10 GHz and the breakdown voltage approaches 100 V. Thedevices feature excellent linearity (IM3 of -50 dBc at 10 dBback-off) and high power gain (14 dB) at 2 GHz, and are thefirst vertical DMOSFETs suitable for 2 GHz power applications.Excellent heat sinking and no significant degradation of thequiescent current due to hot-carrier injection ensure thermalstability and good long-term reliability of fabricated devices.

Index Terms— RF power MOSFETs, substrate transfer, self-heating.

I. I NTRODUCTION

H IGH frequency power gain of bulk-silicon vertical dou-ble diffused MOSFETs (VDMOSFETs) is limited due

to large gate-drain capacitance and source leads inductanceto ground. Governed by an excellent linearity performance ofVDMOSFETs, laterally diffused MOSFETs (LDMOSFETs)were designed and fabricated [1], [2], and demonstrated tofeature high RF power gain and good linearity. Nowadays,LDMOSFETs are state-of-the-art devices for highly linear RFpower applications [3].

To improve RF performance, the initial concept of a LD-MOSFET has been modified to include a field-plate electrode[4], which overlaps the gate and is connected to the source.Such electrode reduces the fields at the edge of the gatethus increasing the breakdown voltage, reducing feedbackcapacitance and improving device linearity. Combined withreduction of the gate area, a field-plate electrode has beenintroduced within a VDMOSFET as well [5]. However, eventhough gate-drain capacitance is significantly reduced, largeleads inductance from source to ground still limits the RFgain of bulk-silicon VDMOSFETs.

Future generations of highly integrated wireless systems askfor new RF power device concepts. Implementation of a LD-MOSFET in thin-film SOI was demonstrated to be a promisingtechnology to meet such demands [6]. Nevertheless, in bothbulk and especially SOI device realization, inefficient heat re-moval from the active device regions degrades carrier mobilityand negatively affects device RF performance [7]. Recently

N. Nenadovic (contact author), V. Cuoco, H. Schellevis, A. Griffo, M. Pelk,L. K. Nanver and J. W. Slotboom are with Laboratory of ECTM, DIMES,Delft University of Technology, Feldmannweg 17, P.O. BOX 5053, 2600 GBDelft, The Netherlands. Tel. +31-15-2782185, fax. +31-15-2622163, E-mail:n.nenadovic@dimes.tudelft.nl.

J. W. Slotboom is also with Philips Research Laboratories, Prof. Holstlaan4, 5656 AA Eindhoven, The Netherlands.

S. J. C. H. Theeuwen, G. Spierings and R. Jos are with Philips Semicon-ductors - RF Modules, Gerstweg 2, 6534 AE Nijmegen, The Netherlands.

developed substrate transfer technology [8] opens possibilitiesto solve heat transport related problems. Moreover, it allowsa complete freedom of substrate choice which can result inelimination of substrate losses implying integration of evenbetter passives, and further reduction in cross-talk and powerconsumption. Besides, substrate transfer technology opens theway for other technological advances like back-wafer low-ohmic contacting [9] and 3D integrated circuit fabrication [10].

The above mentioned device and technology concepts (i.e.substrate transfer, back-wafer low-ohmic contacting and usageof a field-plate electrode) are combined in this work to designand fabricate VDMOSFETs very attractive for 3G wirelessapplications. This paper describes the first VDMOSFETsfabricated in substrate transfer silicon-on-glass technology.

II. D EVICE DESIGN AND FABRICATION

A schematic of the process flow is shown in Fig. 1. Thesubstrate transfer technology divides the processing into first aconventional front-wafer silicon processing on the SOI startingmaterial, second the wafer transfer to glass by gluing withremoval of the bulk silicon to the buried oxide, and lastly theback-wafer processing at temperatures below 300◦C.

In the front-wafer processing here, a production RF LDMOSprocess at Philips Semiconductors has been modified to realizethe source, gate and drain epi-profile of the VDMOS structure.The n-profile of the drain is formed by growing an n-epifollowed by a blanket implantation and high temperaturediffusion. The modified 0.8-µm LDMOS processing includesp+-sinker source and gate implantation/diffusion, a 40 nm-thick thermal gate oxidation, poly-Si field-plate and gateelectrode formation with self-aligned p-well and n+-sourceimplantation/diffusion, and Al on TiN metallization.

The substrate transfer to glass and the bulk Si removal to theburied oxide by TMAH etching follows. The substrate transferis also a Philips production process but is run at DIMES withseveral enhancements: the back-wafer is patterned with thesame high-precision lithography as the front-wafer and lowohmic n- and p-type contacts are formed by implanting andlaser annealing 5 keV As+ and B+, respectively, and metal-lization with sputtered Al/Si. The gate p+-plugs are isolatedby trench etching from the back-wafer to the front-wafer oxideisolation. The trenches are then filled with BCB and etchedback till Al/Si. The processing continues with electro-platingof a two level thick copper interconnect on the back-waferwith Ti/TiN diffusion and adhesion barrier. Electro-plated Cuis covered with BCB before the devices can be solderedto a PCB. The first 4µm-thick copper layer on the drainminimizes debiasing over long drain fingers, and the second

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Fig. 1. Schematic of VDMOSFET on glass process flow: (a) front-waferprocessing, (b) substrate transfer and (c) back-wafer processing.

4+4 µm-thick layer to the source contacts improves thermalconductance to the thermal ground. In contrast to conventionalbulk-silicon VDMOSFETs, the back-wafer contacting alongwith copper electro-plating allow the elimination of the sourceleads inductance to ground by forming a common thermal andelectrical ground. A SEM image of a single-cell device afterthe two level copper electro-plating is given in Fig. 2.

III. R ESULTS AND DISCUSSION

In the development of the present VDMOS structure, severaldevice layouts and process flows, based on a 0.8µm RF-LDMOS technology, were considered and thoroughly analyzedby means of process, device and RF-performance simulations[11], [12]. The first fully processed VDMOS devices that aremeasured here have a gate-to-drain distanced1=5.6 µm, an-epi thicknessd2=3.5 µm and a distance between the gate

DRAIN4 m Cum

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Fig. 2. SEM image of two levels of copper electro-plated on the back-waferof silicon-on-glass VDMOST. Gate width isWg=70 µm.

and field-plate electroded3=1 µm, where all the distances arespecified in Fig. 1(c2). We focus on measurements done on asingle-cell GSG devices suitable for RF characterization, suchas those shown in Fig. 2 having the gate widthWg=350 µm.Fig. 3(a) displays measured output characteristics and off-statebreakdown voltageBVoff of nearly 100 V. Pulsed small signals-parameters of the devices were measured versus frequencyupto 11 GHz, andfT and fmax (Fig. 3(b)) were extractedfrom 20 dB/dec current gain and maximum available gain(k < 1) characteristics, respectively. The measured values arefT /fmax=5/8 GHz forVDS=25 V andfT /fmax=6/10 GHz forVDS=45 V. Furthermore, pulsed s-parameters were measuredversus bias and used as input for the powerful Smoothiedatabase model for FET devices, proven to yield very accurateprediction of RF performance [13]. Load-pull simulations at2 GHz yields, in class-AB bias conditions, a two-tone powergain as high as 14 dB, IM3 lower than -50 dBc at 10 dBback-off and very low IM5 (Fig. 4). The same production linebulk-Si RF-LDMOSFETs, show two-tone power gain of 15 dBand IM3 of -40 dBc at 10 dB back-off.

Silicon-on-glass VDMOSFETs experience no significantdegradation of the quiescent currentIdq even though noadditional efforts were made to engineer the drain profile.Measurements on the fabricated devices indicate degradationof less than 10% in 20 years, which is very good for such RFperformance and is much better compared to the same produc-tion line LDMOSFETs. Furthermore, temperature distributionsshown in Fig. 5, numerically calculated for large, high powerdevices, predict that a silicon-on-glass VDMOSFET, when sol-dered to a thermally conducting substrate, features much lowertemperature increase than the bulk silicon device soldered tothe same substrate. This is due to the much closer proximity ofthe heat sink to the active device regions achieved by substratetransfer.

IV. CONCLUSIONS

The fabricated silicon-on-glass VDMOSFETs demonstratehighly linear characteristics that are attractive for manywireless power applications. They feature anfT /fmax of6 GHz/10 GHz, high power gain at 2 GHz, very good thermalstability and long-term reliability. These are the first VDMOS-FETs featuring excellent RF characteristics being suitable for3G applications.

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Fig. 3. Measured (a) off-state breakdown voltage and pulsed outputcharacteristics, and (b) current dependence offT andfmax.

REFERENCES

[1] A. Wood, C. Dragon, and W. Burger, “High performance siliconLDMOS technology for 2 GHz RF power amplifier applications,” inIEDM Tech. Dig., 1996, pp. 87–90.

[2] A. Wood, W. Brakensick, C. Dragon, and W. Burger, “120 Watt, 2 GHz,Si LDMOS RF power transistor for PCS base station applications,” inMTT-S digest, 1998, pp. 707–710.

[3] S. Xu, F. Baiocchi, H. Safar, J. Lott, A. Shibib, Z. Xie, T. Nigam,B. Jones, B. Thomson, J. Desko, and P. Gammel, “High power siliconRF LDMOSFET technology for 2.1 GHz power amplifier applications,”in Proc. ISPSD, 2003, pp. 190–193.

[4] G. Ma, W. Burger, c. Dragon, and T. Gillenwater, “High efficiencyLDMOS power FET for low voltage wireless communications,” inIEDM Tech. Dig., 1996, pp. 91–94.

[5] S. Xu, C. Ren, Y. C. Liang, P.-D. Foo, and J. K. O. Sin, “Theo-retical analysis and experimental characterization of the dummy-gatedVDMOSFET,” IEEE Trans. Electron Devices, vol. 48, pp. 2168–2176,2001.

[6] J. G. Fiorenza, D. A. Antoniadis, and J. A. del Alamo, “RF powerLDMOSFET on SOI,” IEEE Electron Device Lett., vol. 22, pp. 139–141, 2001.

[7] P. Khandelwal, M. Trivedi, K. Shenai, and S. K. Leong, “Thermal andpackage performance limitations in LDMOSFET’s for RFIC applica-tions,” IEEE Trans. Microwave Theory Tech., vol. 47, pp. 575–585,1999.

[8] R. Dekker, P. G. M. Baltus, and H. G. R. Maas, “Substrate transfer forRF technologies,”IEEE Trans. Electron Devices, vol. 50, pp. 747–757,2003.

[9] L.K. Nanver, H. W. van Zeijl, H. Schellevis, R. J. M. Mallee,J. Slabbekoorn, R. Dekker, and J. W. Slotboom, “Ultra-low-temperaturelow-ohmic contacts for SOA applications,” inProc. IEEE BCTM, 1999,pp. 137–140.

[10] K. W. Guarini, A. W. Topol, M. Ieong, R. Yu, L. Shi, M. R. Newport,D. J. Frank, D. V. Singh, G. M. Cohen, S. V. Nitta, D. C. Boyd, P. A.O’Neil, S. L. Tempest, H. H. Pogge, S. Purushothaman, and W. E.Haensch, “Electrical integrity of state-of-the-art 0.13µm SOI CMOSdevices and circuits transferred for three-dimensional (3D) integratedcircuits (IC) fabrication,” inProc. IEDM, 2002, pp. 943–945.

[11] N. Nenadovic, V. Cuoco, S. J. C. H. Theeuwen, L. K. Nanver, H. F. F.Jos, and J. W. Slotboom, “A novel vertical DMOS transistor in SOAtechnology for RF power applications,” inProc. MIEL, 2002, pp. 159–162.

[12] N. Nenadovic, V. Cuoco, S. J. C. H. Theeuwen, L. K. Nanver, H. F. F.Jos, and J. W. Slotboom, “High-performance Silicon-On-Glass VDMOStransistor for RF-power applications,” inProc. ESSDERC, 2002, pp.379–382.

[13] V. Cuoco, M. P. van d. Heijden, M. Pelk, and L. C. N. de Vreede,“Experimental Verification of the Smoothie Database Model for Thirdand Fifth Order Intermodulation Distortion,” inProc. ESSDERC, 2002,pp. 635–638.

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Fig. 4. Two-tone transducer gain and third- and fifth-order intermodulationdistortion versus output power.

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Fig. 5. Simulated temperature profile along the cross section of high-power(a) bulk and (b) silicon-on-glass device atVDS=25 V andIDS=3.5 µA/µm.Silicon substrate thickness in (a) is set to 300µm, while the thicknessof a thermally conducting substrate in both (a) and (b) is set to 200µm.The ambient temperature and temperature of the heat sink below thermallyconducting substrate is made 300 K.