ecl 302 electronic circuits - i and simulation lab

Exp.No: Page no-1 Date: / /

Electronic Circuits –I Lab Vidyaa Vikas College of Engineering and Technology

SYMBOLS AND PIN DIAGRAMS



CIRCUIT SIMULATION USING ORCAD SIMULATION TOOL

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Procedure for Circuit simulation:

1. Choose ORCAD capture icon from the program window.

2. In file, select new and then project.

3. Enter the name of the project, create the new project using A/D or mixed

modeling and specify the location.

4. Create PSPICE project as a blank project.

5. In the schematic window click on the right most corners to select the tools.

6. Select the place part tool to select the components that are specified circuit

diagram.

7. Place the components on the schematic page as given in the circuit diagram.

8. Select place wire tool to connect the components as per the circuit diagram.

9. Place the junctions where ever it is necessary.

10. Select the place ground tool to place ground as needed in the circuit diagram.

11. Select the voltage / level marker from the tool bar and place as per the

requirement and save the project.

12. Choose new simulation profile and name the simulation profile.

13. Select edit simulation settings from the tool bar and make the necessary

simulation settings.

14. Select Run PSPICE option and obtain the results.

15. Adjust the run to time by selecting edit simulation settings for proper results.

Note:

1. Simulation of all the experiments using ORCAD tool is mandatory.

2. The above said procedure should be followed in common to all

the experiments given in the syllabus formulated by Anna

University – Coimbatore.



STUDY OF DIFFERENT TYPES OF BIASING OF ACTIVE CIRCUITS

(BIASING OF BIPOLAR JUNCTION TRANSISTOR - BJT)

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Aim:

To Study and simulate the different biasing techniques of Bipolar Junction Transistor (Fixed bias and voltage divider bias). Components required:

S.No Description Range Type Quantity

1 PSPICE Simulation Tool - - -

2 PC System

Theory:

The process of raising the strength of a weak signal without any change in its general shape is called faithful amplification. The key factor for achieving this faithful amplification is biasing. Biasing the circuit should ensure the following conditions,

1. Proper zero signal collector current. 2. Minimum proper Base–Emitter voltage (VBE) at any instant. 3. Minimum proper Collector–Emitter voltage (VCE) at any instant.

(VCE does not fall below 0.5 V for Germanium and 1V for silicon) Conditions (1) and (2) ensure that base-emitter junction shall remain properly

forward biased and (3) ensure that base-collector junction shall remain reverse biased at all times. The fulfillment of these conditions will ensure that the transistor works over the active region of the output characteristics i.e., between saturation to cutoff region.

Methods of Transistor Biasing:

1. Base resistor or fixed bias. 2. Self bias or voltage divider bias

Base Resistor or Fixed biasing technique:

In this method, a high resistance RB (several 100 Kilo ohms) is connected between the base and positive end of supply for NPN transistor and between base and negative end of supply for PNP transistor. Hence zero signal Base current is provided by VCC and its flows through RB. Since base is positive with respect to emitter, the base emitter junction is forward biased. The required value of zero signal base current IB can be made to flow by selecting the proper value of base resistor RB.

Figure 1.1.1: CE amplifier circuit with fixed bias



(A) Circuit Arrangement for Base resistor or fixed biasing technique:

Circuit Design:

Design a common emitter amplifier circuit with base resistor biasing method for

the given specifications

β =100 VCC = 15V VBE = 0.6V VCE = 8V IC = 2 mA

S = β + 1 ---- β = S – 1

S = 100+1

S = 101

We know that, IB = IC / β

IB = 2×10-3 / 100

IB = 0.02 mA

To find RB and RC:

VCC = IB RB + VBE

RB = (VCC - VBE) / IB

= (15-0.6) / 0.02×10-3

RB = 720 K Ω

VCC = IC RC + VCE.

RC = VCC - VCE / IC

= (15-8) / 2×10-3

RC = 500 Ω



Circuit Analysis for Base resistor or fixed biasing technique:

From the Figure 1.1.1 It is required to find the value of RB so that the required

collector current flows in the zero signal conditions. Let IC be the required zero signal

collector current.

Therefore IB = IC / β --------- (1)

Where, β is the current amplification factor for CE configuration. Considering the closed circuit A-B-E-N-A and applying KVL,

VCC = IB RB + VBE

RB = (VCC - VBE) / IB --------- (2)

Eqn. (2) can be rewritten as,

RB = VCC / IB; since VCC >> VBE VBE can be Neglected

Stability factor(s):

S= β + 1

Advantages of Base Resistor Method:

1. The biasing circuit is very simple as only one resistance RB is required.

2. Biasing conditions can easily be set and the calculations are simple.

3. There is no loading of the source by the biasing circuit since no resistor is

employed across base emitter junction.

Disadvantages of Base Resistor Method:

1. This method provides poor stabilization.

2. The stability factor is very high.

Self Bias or Voltage Divider Bias:

This is most widely used method of providing biasing and stabilization to a

transistor. In this method, two resistances R1 and R2 are connected across the supply

voltage VCC and provide biasing. The emitter resistance RE provides stabilization. The

name “Voltage Divider” comes from the voltage divider form by R1 and R2. The voltage

drop across R2 forward biases the base-emitter junction. This causes the base current

and hence collector current flows in the zero signal condition.

Circuit Analysis for Self Bias or Voltage Divider Bias:

To find collector Current (IC):

I1 = VCC / R1 + R2 ---- (1)

VB = VCC R2 / R1 + R2 ---- (2)



Design a common emitter amplifier circuit with Voltage Divider biasing method

for the given specifications

VCC = 10 V IE =1mA S = 7 hfe = 100 VCE = 5V VE = 1V

To find RC:

VCC = IC RC + VCE + IE RE

= IC RC + VCE + VE ------------ (VE=IE RE)

IC RC = VCC - VCE - VE

RC = (VCC - VCE - VE) / IC

= (10 – 5 – 1) / 1×10-3

RC = 4 K Ω

To find VB:

VB = VBE + VE

= 0.7 + 1 = 1.7 V

VB = 1.7 V

S = (1+ β) (1+ (RB / RE))

1+ β + (RB / RE)

Solving the above equation we get,

S = 1+ (RB / RE)

RB = (S-1) RE

= (7-1) *(1×103)

RB = 6 K Ω

To find R1 and R2:

VB = VCC R2 / R1 + R2 ------ (1)

R1 + R2 = VCC R2 / VB ------ (A)

RB = R1 R2 / R1 + R2 ------ (2)

R1 + R2 = R1 R2 / RB ------ (B)

From the Equations A and B, (LHS = RHS)

VCC R2 / VB = R1 R2 / RB

R1 = RB VCC / VB

= (6×103) * 10 / 1.7

R1 = 35.29 K Ω

We know that,

RB = R1 R2 / R1 + R2



RB = R1 R2 / R1 + R2 ---- (3)

VBE = VB - VE

VB = VBE + VE ---- VE = IE RE

VB = VBE + IE RE

IE = VB – VBE / RE

(Or)

IC = VB – VBE / RE ---- (4) IE ≈ IC (IE = IC + IB (IBNegligible))

Considering Eqn. (4) IC does not depend upon β. Though IC depends upon VBE but

in practice VB >> VBE so that IC is practically independent of VBE. Thus IC in this voltage

divider bias circuit is almost independent of transistor parameters and hence good

stabilization is ensured.

Fig 1.1.2: CE amplifier circuit with Voltage divider bias

To find Collector – Emitter Voltage (VCE):

Applying KVL to the Collector side,


VCE = VCC - IC RC - IE RE

VCE = VCC - IC (RC+RE) --------- IE ≈ IC

Stabilization (S):

In this circuit excellent stabilization is provided by RE

VB = VBE + IC RE --------- IE ≈ IC

If collector Current (IC) increases due to rise in temperature, causes the voltage drop

across emitter resistance RE to increase. As voltage drop across R2 is independent of IC

therefore, VBE decreases. This in-turn causes IB to decrease which in-turn restore IC to

the original value.

Stability Factor(S) = (1+ β) (1+ (RB / RE))

1+ β + (RB / RE)



Sub. RB = 6 K Ω and R1 = 35.29 K Ω in above equation,

6×103 = 35.29×103 * R2 / 35.29×10

3 + R2


R2 = 7.3 K Ω ≈ 7 K Ω

To find CC and CE:

CC = XCC = Zi / 10

Zi = R1 ll R2 ll hie

h ie = h fe × re

re = VT / IE = 26×10-3 / 1×10-3 = 26 Ω

h ie = 100 × 26 = 2.6 K Ω

XCC = R1 ll R2 ll hie / 10 ----- R1 ll R2 = R1 R2 / R1 + R2

= 6 KΩ ll 2.6 KΩ / 10 = 35.29KΩ *7.3KΩ

XCC= 0.182 KΩ 35.29KΩ+7.3KΩ

XCC = 1/ 2∏f CC = 6 KΩ

CC = 1/ (2×3.14×100×0.182×103)

= 8.74×10-6 = 8.74 µ f CC ≈ 10 µ f

XCE = 1/ 2∏f CE

XCE = Z0 /10 = R E / 10

XCE = R E / 10 = 100 Ω

CE = 1/ (2×3.14×100×100)

CE = 16 µ f



Note:

R2 = 0.1 β RE

To find load resistance:

RL = VCC – VE / 2 IE

To find the value of coupling capacitor:

CC = 1/ 2∏f XCC

Where, XCC = Zi / 10 = R in / 10

Zi = R1 ll R2 ll h ie

h ie = h fe × re

re = VT / IE -------- (VT = 26mV)

To find the value of bypass capacitor:

CE = 1/ 2∏f XCE

Where XCE= R E / 10

Description Max. Marks

Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the biasing of Bipolar Junction Transistor in base resistor bias method and

voltage divider bias method were studied and verified the same by using PSPICE circuit

simulation tool.



Design a common source JFET amplifier in self biased condition for the given

specifications

ID =1.5 mA VDS= 10V IDSS = 0.5mA VP = - 2V VDD= 12 V

To find VGS:

ID = IDSS 1- (VGS / VP) 2

1.5×10-3 = 5×10-3 1+ (VGS / 2) 2

√ (1.5/5) = 1+ (VGS / 2) ------ √ (1.5/5) = 0.55


VGS = - 0.906 V

To find VS:

VGS = VG - VS ------ (VG = 0)

VGS = - VS = - 0.9 V

VS = 0.9 V

To find RS:

RS = VS / IS ------ (IS = ID)

RS = VS / ID

= 0.9 / 1.5×10-3

RS = 0.6 KΩ

To find RD:

VDD = ID RD + VDS + IS RS ------ (VS = IS RS)

VDD = ID RD + VDS + VS

12 = 1.5×10-3 RD +10+0.9

Solving the above equation,

RD = (12 -10.9) / 1.5×10-3

RD = 0.73 KΩ

To find CC:

XC1 = RG / 10 ----- RG=1MΩ (To make the gate current negligible) = 1×106 / 10

XC1 = 0.1MΩ

XC1 = 1/ 2∏f CC1

CC1 = 1/ 2∏f XC1 = 1/ (2×3.14×100×0.1×106) = 0.015 µ f

CC1 = CC2 = 0.015 µ f

CC1 = CC2 ≈ 0.01 µ f



STUDY OF DIFFERENT TYPES OF BIASING OF ACTIVE CIRCUITS

(BIASING OF JUNCTION FIELD EFFECT TRANSISTOR - JFET)

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Aim:

To Study and simulate the different biasing techniques of Junction field effect Transistor (Fixed bias and voltage divider bias). Components required:

S.No Description Range Type Quantity

1 PSPICE Simulation Tool - - -

2 PC System

Theory:

Generally, field effect transistor’s output characteristics are controlled by input

voltage, thus field effect transistor is classified as a voltage controlled device. This

behavior of the FET represents the clear difference from the BJT (Current controlled

device).

FET is classified into two types,

1. Junction Field Effect Transistor (JFET)

2. Metal Oxide Semiconductor Field Effect Transistor (MOSFET).

A JFET is a three terminal semiconductor device in which current conduction is by one

type of carrier i.e. electrons or holes.

JFET Biasing:

For the proper operation of n-channel JFET, gate must be negative w.r.t. source.

This can be achieved either by inserting a battery in the gate circuit or by a circuit known

as biasing circuit. Biasing of JFET is the most likely one due to the reason that batteries

are costly and require frequent replacement.

Biasing Circuit:

The biasing circuit uses supply voltage VDD to provide the necessary bias. There

are two most commonly used biasing methods are

1. Self bias

2. Voltage divider bias / Potential divider bias.

Self-Bias Method:

Figure 1.2.1 shows the self bias method. The resistor RS is the base resistor. The

DC component of drain current flowing through RS produces the desired bias voltage.

The capacitor CS bypasses the AC component of the drain current.



To find CS:

XCS = RS / 10 = 0.6×103 /10

XCS = 60 Ω

CS = 1/ 2∏f XCS

= 1/ (2×3.14×100×60)

CS = 26 µ f ≈ 15 µ f

To find RL:

Gain (A) = gm (RD ll RL)

Required gain: 10

RL = 4.7 KΩ



Circuit Analysis:

To find RS:

Voltage across RS, VS = ID RS

Figure 1.2.1: Common Source JFET Amplifier in Self Biased Condition

To find VS:

Since the gate current is negligibly small, the gate terminal is at D.C ground i.e,

VGS = 0

VGS = VG - VS ------ (VG = 0)

VGS = 0 - ID RS

VGS = - ID RS

Thus bias voltage VGS keeps gate negative w.r.t. source.

Operating point:

The operating point (i.e, zero signal ID and VDS) can be easily determined. Since

the parameters of the JFET are usually known, zero signal ID can be calculated from the

following relation


Also VDD = ID RD + VDS + IS RS

VDS = VDD - ID (RD + RS) ------ (ID ≈ IS)

To find CC:

XC1 = RG / 10 ------ RG=1MΩ (To make the gate negligible)

XC1 = 1 / 2∏f CC1

CC1 = 1 / 2∏f XC1

To find CS:

XCS = RS / 10

CS = 1/ 2∏f XCS

To find RL:




Design a common source JFET amplifier in Voltage divider biased condition for the given

specifications

ID=2.5mA VDS= 8V IDSS =10mA VP = -5V VDD= 30 V R1=1 MΩ R2=500KΩ

To find VGS:


2.5×10-3 = 10×10-3 1+ (VGS / 5) 2

√ (2.5/10) = 1+ (VGS / 5) ----- √ (2.5/10) (2.5/10)1/2


VGS = - 2.5 V

To find V2:

V2 = VDD R2 / R1+ R2

= (30×500×103) / (106+500×103)

V2 = 10 V

To find RS:

V2 = VGS + IS RS ----- (IS = ID)

10 = -2.5 + 2.5×10-3 RS

RS = (10 + 2.5) / 2.5×10-3

RS = 5 KΩ



Voltage divider bias or potential divider bias:

Figure 1.2.2 shows potential divider method of biasing a JFET. The circuit is very

much similar to that of biasing the transistor. The resistors R1 and R2 form a voltage

divider across drain supply VDD. The voltage V2 across R2 provides the necessary bias.

Figure 1.2.2: Common Source JFET Amplifier in Voltage Divider Method

Circuit Analysis:

To find V2:

V2 = VDD R2 / R1+ R2

Now V2 = VGS + ID RS ----- (ID = IS)

VGS = V2 - ID RS

The circuit so designed that ID RS is larger than V2 so that VGS is negative. This provides

correct bias voltage. The operating point can be found by

ID = (V2 - VGS) / RS

And VDD = ID RD + VDS + IS RS

VDS = VDD - ID (RD + RS) To find the value of coupling capacitor:

XCC1 = RG / 10

RG = R1 R2 / R1 + R2

CC1 = 1/ 2∏f XC1 To find the value of Source capacitor:

XCS = RS / 10

CS = 1/ 2∏f XCS



To find RD:

VDD = ID RD + VDS + IS RS

30 = 2.5×10-3 RD + 8+9

30 – 17 = 2.5×10-3 RD

RD = 13 / 2.5×10-3

RD = 5.2 KΩ


XCC1 = RG / 10

RG = R1 R2 / R1 + R2 = 333.33 KΩ

XCC1 = 33.33 KΩ

CC1 = 1/ 2*3.14*100*33300

CC1 = CC2 = 0.04 µ f ≈ 0.01 µ f

To find the value of Source capacitor:

XCS = RS / 10

= 5000 / 10

XCS = 500 Ω

Cs = 1/ (2*3.14*100*500)

Cs = 3.2 µ f ≈ 4.7 µ f




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the biasing of Junction Field Effect Transistor in base resistor bias method

and voltage divider bias method were studied and verified the same by using PSPICE

circuit simulation tool.



Circuit Diagram:

Design:

Output requirements: Mid-band voltage gain of the amplifier = 50. Selection of transistor: Select transistor BC 107 since its minimum guaranteed h FE (=100) is more than the required gain (=50) of the amplifier. Details of BC 107: Type: NPN silicon, application: In audio frequency. Max. Ratings : VCB= 50V VCE= 45 V VBE=6 V IC= 100mA Nominal Ratings : VCE= 5 V IC= 2mA h FE = 100 to 500 DC biasing conditions:

VCC= 12V IC= 2mA VRC= 40% of VCC=4.8V VRE= 10% of VCC=1.2V VCE= 50% of VCC= 6V

Design of RC

VRC = IC RC = 4.8 V

RC = VRC / IC = 4.8 / 2×10-3

RC =2.4 KΩ ≈ 2.2 KΩ

Design of RE

VRE = IE RE= 1.2 V

RE = VRE / IE = 1.2 / 2×10-3 ---- IC=IE

RE =600 Ω ≈ 620 Ω

Design of voltage divider R1 and R2

IB = IC / h FE = 2×10-3 / 100 = 20 µ A

IB = 20 µ A



AMPLIFYING CIRCUITS

(A) SIMPLE COMMON EMITTER AMPLIFIER CONFIGURATION GAIN & BANDWIDTH

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Aim:

To design, simulate and set up a simple Common Emitter (CE) amplifier using

bipolar junction transistor and to plot its frequency response.

Components Required:

S.No Description Range(s) Type Quantity

1 Transistor

2 Capacitors

3 Resistors

4 Power Supply

5 Bread Board

6 Signal Generator

7 CRO

8 Probe

9 Connecting wires

Theory:

RC Coupled CE amplifier is widely used in audio frequency applications in radio and TV receivers. It provides current, voltage and power gains. Base current controls the collector current of a CE amplifier. A small increase in base current results in a relatively large increase in collector current. Similarly small decrease in base current causes large decrease in collector current. The emitter-base junction must be forward biased and the collector-base junction must be reverse biased for the proper functioning of an amplifier.

In the circuit diagram, NPN transistor is connected as a common emitter ac amplifier. R1 and R2 are employed for the voltage divider bias of the transistor. Voltage divider bias provides independence from the variation in β. The input signal V in is coupled through CC1 to the base and output voltage is coupled from collector through the capacitor CC2.

The input impedance of the amplifier is Z in = R1 ll R2 ll β r e and output resistance

is Z out = RC Procedure:

1. Test all the components using a multimeter. Set up the circuit and verify dc biasing conditions. To check the dc biasing conditions, remove input signal and capacitors in the circuit.

2. Connect the capacitors in the circuit and apply a sinusoidal signal from signal generator to the circuit input. Observe the input and output waveforms on the CRO screen simultaneously.



Assume the current through R1 =10 IB and that through R2 = 9 IB to avoid loading the

potential divider by the base current.

VR2 = Voltage across R2 = VBE + VRE

VR2 = VBE + VRE = 0.7 + 1.2=1.9V -(1)

Also VR2 = 9 IB R2 = 1.9 V -----(2)

From (1) and (2) - (LHS = RHS)

9 IB R2 = 1.9 V

R2 = 1.9 / 9×20×10-6

R2 = 10.6 KΩ ≈ 10 KΩ

VR1 = Voltage across R1 = VCC - VR2

VR1 = VCC - VR2 = 12 – 1.9 = 10.1V --(1)

Also VR1= 10 IBQ R1 =10.1V ----(2)


10 IBQ R1 = 10.1 V

R1 = 10.1 / 10×20×10-6

R1 = 50 KΩ ≈ 47KΩ pot.

Design of RL (Av = -(r c – r e)) -------- (3)

Where r c = RC ll RL -------- (4)

re = 25 ×10-3 / IE = 25×10

-3 / 2×10-3 = 12.5 Ω

re = 12.5 Ω

Sine the required gain= 50, substituting we get RL = 845Ω. Use 820Ω.

Design of coupling capacitors CC1, CC2 and CC3

XC1 at the lowest frequency (say 100Hz), should be equal to one-tenth or less of

the series impedance being driven by the signal passing through the capacitor. Here the

relevant impedance is R in.

Then XC1 ≤ R in /10.

Here R in = R1 ll R2 ll h FE re ---- (5)

Where re = 12.5 Ω.

Sub all the values in equation (5), we get

R in = 1.1KΩ. Then XC1 ≤ 110 Ω.

CC1 = 1/ 2∏fL XC1

= 1/ (2×3.14×100×110)

CC1 = 14 µf ≈ 15 µf

Similarly,

XC2 ≤ Rout /10.

Where Rout = RC

Then XC2 ≤ 240 Ω

CC2 = 1/ 2∏fL XC2

= 1/ (2×3.14×100×240)

CC2 = 6.6 µf ≈ 10 µf

Design of Bypass capacitors CE

To bypass the lowest frequency (say 100Hz), XCE should be equal to one-tenth or

less of the resistance RE.

XCE ≤ RE /10;

CE ≥ 1/ 2∏fL XCE

= 1/ (2×3.14×100×62)

CE = 2.6 µf ≈ use 10 µf



3. Keeping the input amplitude constant vary the frequency of the input signal from 0 Hz to 1 MHz. Measure the output amplitude corresponding to different frequencies and enter it in tabular column.

4. Plot the frequency response characteristics on a semi-log graph sheet with gain on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding to 1/ √2 times of the maximum gain.

5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL. 6. Remove the emitter bypass capacitor CE from the circuit and repeat the steps

3 to 5 and observe that the bandwidth increases and gain decreases in the absence of CE.

Circuit Analysis for simple common emitter amplifier in Voltage Divider Bias:

To find collector Current (IC):

I1 = VCC / R1 + R2 ---- (1)

VB = VCC R2 / R1 + R2 ---- (2)

RB = R1 R2 / R1 + R2 ---- (3)

VBE = VB - VE

VB = VBE + VE ---- VE = IE RE

VB = VBE + IE RE

IE = VB – VBE / RE

(Or)

IC = VB – VBE / RE ---- (4) IE ≈ IC (IE = IC + IB (IBNegligible))

Considering Eqn. (4) IC does not depend upon β. Though IC depends upon VBE but

in practice VB >> VBE so that IC is practically independent of VBE. Thus IC in this voltage

divider bias circuit is almost independent of transistor parameters and hence good

stabilization is ensured.

To find Collector – Emitter Voltage (VCE):

Applying KVL to the Collector side,


VCE = VCC - IC RC - IE RE

VCE = VCC - IC (RC+RE) --------- IE ≈ IC

Stabilization (S):

In this circuit excellent stabilization is provided by RE

VB = VBE + IC RE --------- IE ≈ IC

If collector Current (IC) increases due to rise in temperature, causes the voltage drop

across emitter resistance RE to increase. As voltage drop across R2 is independent of IC

therefore, VBE decreases. This in-turn causes IB to decrease which in-turn restore IC to

the original value.

Stability Factor(S) = (1+ β) (1+ (RB / RE))

1+ β + (RB / RE)



Model Graph: frequency response with out CE

Model Graph: frequency response with CE



Note:

R2 = 0.1 β RE

To find load resistance:

RL = VCC – VE / 2 IE


CC = 1/ 2∏f XCC

Where, XCC = Zi / 10 = R in / 10

Zi = R1 ll R2 ll h ie

h ie = h fe × re

re = VT / IE -------- (VT = 26mV)

To find the value of bypass capacitor:

CE = 1/ 2∏f XCE

Where XCE= R E / 10



Observation:

V in =

With CE With out CE

S.No Frequency in Hz Vo in Volts

Gain (A) = 20 log(VO / V in)

Vo in Volts Gain (A) =

20 log(VO / V in)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the simple Common Emitter (CE) amplifier using bipolar junction transistor

was designed, simulated and its frequency response were plotted.

Bandwidth of the amplifier with CE = fH - fL =

Bandwidth of the amplifier with out CE = fH - fL =



Design a common source JFET amplifier in self biased condition for the given

specifications

ID =2 mA VDS= 10V VD= 45 % of

VDD = 5.4 V VGS = - 2V VDD= 12 V gm = 2.5 Gain(A)=10

Select RG = 1M Ω to make current negligible.

To find VS:

VGS = VG - VS ------ (VG = 0)

VGS = - VS

- 2 = - VS

VS = 2 V

To find RS:

RS = VS / IS ------ (IS = ID)

RS = VS / ID

= 2 / 2×10-3

RS = 1 KΩ

To find RD:

VD = ID RD

RD = VD / ID

= 5.4 / 2×10-3

RD =2.7 KΩ

To find RL:


Required gain: 10

RL = 4.7 KΩ

To find CC:

XC1 = RG / 10 ----- RG=1MΩ (To make the gate current negligible) = 1×106 / 10

XC1 = 0.1MΩ

XC1 = 1/ 2∏f CC1

CC1 = 1/ 2∏f XC1 = 1/ (2×3.14×100×0.1×106) = 0.015 µ f

CC1 = CC2 = 0.015 µ f

CC1 = CC2 ≈ 0.022 µ f



AMPLIFYING CIRCUITS

(B) COMMON SOURCE AMPLIFIER CONFIGURATION – GAIN & BANDWIDTH

---------------------------------------------------------------------------------------------------

Aim:

To design, simulate and set up a Common Source (CS) amplifier using junction

field effect transistor and to plot its frequency response.



1 Transistor

2 Capacitors

3 Resistors

4 Power Supply

5 Bread Board

6 Signal Generator

7 CRO

8 Probe

9 Connecting wires

Theory: Junction field effect transistor (JFET) is unipolar voltage controlled device. The

drain current is controlled by the voltage at gate. Like BJT’s, JFET amplifiers can also be

set up in three configurations namely Common Drain, Common Source and Common

Gate. Common Source configuration is similar to common emitter configuration of BJT..

JFETs can be biased as voltage divider bias or self bias. A self bias circuit

maintains drain current and gm relatively constant. Constant gm results in a constant

voltage gain. The design of the circuit is done in such a way that the gate to source

junction is reverse biased. The reverse biased junction provides high input impedance.

The applied input voltage slightly changes the gate potential and in turn, the drain

current varies. The output voltage varies with the drain current.

The following expression can be sued to find the gain in dB.

Gain = 20 log (VO / V in)



To find CS:

XCS = RS / 10 = 1×103 /10

XCS = 100 Ω

CS = 1/ 2∏f XCS

= 1/ (2×3.14×100×100)

CS = 16 µ f ≈ 15 µ f

Circuit Diagram:

Model Graph:



Circuit Analysis:

To find RS:

Voltage across RS, VS = ID RS

Figure 1.2.1: Common Source JFET Amplifier in Self Biased Condition

To find VS:

Since the gate current is negligibly small, the gate terminal is at D.C ground i.e,

VGS = 0

VGS = VG - VS ------ (VG = 0)

VGS = 0 - ID RS

VGS = - ID RS

Thus bias voltage VGS keeps gate negative w.r.t. source.

Operating point:

The operating point (i.e, zero signal ID and VDS) can be easily determined. Since

the parameters of the JFET are usually known, zero signal ID can be calculated from the

following relation


Also VDD = ID RD + VDS + IS RS

VDS = VDD - ID (RD + RS) ------ (ID ≈ IS)

To find CC:

XC1 = RG / 10 ------ RG=1MΩ (To make the gate negligible)

XC1 = 1 / 2∏f CC1

CC1 = 1 / 2∏f XC1

To find CS:

XCS = RS / 10

CS = 1/ 2∏f XCS

To find RL:




Procedure:

1. Set up the circuit on the breadboard. Check the DC conditions and apply the

input sinusoidal signal from signal generator to the gate.

2. Obtain the amplified output. Take the output amplitude for various frequencies

for at the input.

3. Plot the frequency response curve. Find the bandwidth of the FET amplifier.


Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the Common Source amplifier using Junction Field Effect Transistor was

designed, simulated and its outputs were plotted.

Bandwidth of the amplifier = fH - fL



Circuit Diagram: TWO STAGE RC COUPLED AMPLIFIER

Model Graph:



TWO STAGE RC COUPLED AMPLIFIER

---------------------------------------------------------------------------------------------

Aim:

To design, set up and study a two stage RC coupled CE amplifier using Bipolar

Junction Transistor.



1 Transistor

2 Capacitors

3 Resistors

4 Bread Board

5 Signal Generator

6 CRO

Theory:

More stages of RC coupled amplifiers can be used in cascade to increase the

voltage gain of an amplifier. A two stage amplifier provides an overall voltage gain of A1

and A2 are the gains of first and second stages respectively. Since each stage provides a

phase inversion, the final output is in-phase with the input.

The input impedance of the second stage is in parallel with RC of the first stage.

The voltage gain A1 of the first stage is:

A1 = RC ll Zin (Second stage) / re

Where Zin (Second stage) = R1 ll R2 ll h FE re

The Voltage gain A2 of the second stage is:

A2 = RC ll RL / re

Procedure:

1. Test all the components using multimeter and make the connections as per the

circuit diagram.

2. Apply a sinusoidal signal from the function generator to the circuit input. Observe

the input and output waveforms on the CRO screen simultaneously.

3. Keeping the input amplitude constant, vary the frequency of the input signal from

0 Hz to 1 MHz. Measure the output amplitude corresponding to different

frequencies and enter the values in tabular column.

4. Plot the frequency response characteristics on a semi log graph sheet with gain

on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding to 1/ √2

of the maximum gain.

5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL.



Design:

Output requirements: Mid band voltage gain of the amplifier = 100

Selection of Transistor: Select transistor BC 107 since its minimum guaranteed

hFE equals the required gain (=50) of the amplifier. Assume the gains A1 = 50 and

A2 = 2 since A= A1 A2.

DC biasing conditions:

VCC = 12 V IC=2mA VRC = 40% of VCC =4.8 V VRE = 10% of VCC =1.2 V

VCE = 50% of VCC =6 V

Design of first stage:

Design of RC

VRC = IC RC = 4.8 V

RC = VRC / IC = 4.8 / 2×10-3

RC =2.4 KΩ ≈ 2.2 KΩ

Design of RE

VRE = IE RE= 1.2 V

RE = VRE / IE = 1.2 / 2×10-3 ---- IC=IE

RE =600 Ω ≈ 620 Ω

Design of voltage divider R1 and R2

IB = IC / h FE = 2×10-3 / 100 = 20 µ A

IB = 20 µ A

Assume the current through R1 =10 IB and that through R2 = 9 IB to avoid loading the

potential divider by the base current.

VR2 = Voltage across R2 = VBE + VRE

VR2 = VBE + VRE = 0.7 + 1.2=1.9V -(1)

Also VR2 = 9 IB R2 = 1.9 V -----(2)


9 IB R2 = 1.9 V

R2 = 1.9 / 9×20×10-6

R2 = 10.6 KΩ ≈ 10 KΩ

VR1 = Voltage across R1 = VCC - VR2

VR1 = VCC - VR2 = 12 – 1.9 = 10.1V --(1)

Also VR1= 10 IBQ R1 =10.1V ----(2)


10 IBQ R1 = 10.1 V

R1 = 10.1 / 10×20×10-6

R1 = 50 KΩ ≈ 47KΩ pot.

Design of RL

From A1

A1 = RC ll Zin (Second stage) / re ----- (3)

Where Zin (Second stage) = R1 ll R2 ll h FE re ----- (4)

re = 25 ×10-3 / IE = 25×10

-3 / 2×10-3 = 12.5 Ω

re = 12.5 Ω

Substituting the R1, R2, h FE and re values in equation (4) and solve the equation

(3). Finally we get

A1 = 50 (approx.)



Gain of the CE amplifier is given by the expression

A2 = AV = (RC ll RL) / re

If the required gain = 2, substituting the values and solving the above equation,

We get,

RL = 23 Ω ≈ 22 Ω

Design of coupling capacitors CC1, CC2 and CC3

XC1 at the lowest frequency (say 100Hz), should be equal to one-tenth or less of

the series impedance being driven by the signal passing through the capacitor. Here the

relevant impedance is R in.

Then XC1 ≤ R in /10.

Here R in = R1 ll R2 ll h FE re ---- (5)

Where re = 12.5 Ω.

Sub all the values in equation (5), we

get R in = 1.1KΩ. Then XC1 ≤ 110 Ω.

CC1 = 1/ 2∏fL XC1

= 1/ (2×3.14×100×110)

CC1 = 14 µf ≈ 15 µf

Similarly,

XC2 ≤ Rout /10.

Where Rout = RC

Then XC2 ≤ 240 Ω

CC2 = 1/ 2∏fL XC2

= 1/ (2×3.14×100×240)

CC2 = 6.6 µf ≈ 10 µf

(Take CC2 = CC3)

Design of Bypass capacitors CE

To bypass the lowest frequency (say 100Hz), XCE should be equal to one-tenth or

less of the resistance RE.

XCE ≤ RE /10;

CE ≥ 1/ 2∏fL XCE

= 1/ (2×3.14×100×62)

CE = 2.6 µf ≈ use 10 µf



Observation:

V in =

S.No Frequency in Hz Vo in Volts Gain (A) =20 log(VO / V in)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the two stage RC coupled CE amplifier using Bipolar Junction Transistor was

designed and its outputs were obtained.

Gain of the first stage =

Gain of the second stage =

Bandwidth of the amplifier =



Circuit Diagram:

Model Graph:



COMPLEMENTARY SYMMETRY CLASS B PUSH PULL POWER AMPLIFIER

---------------------------------------------------------------------------------------------------

Aim:

To design, simulate and set up a Complementary Symmetry Class B Push Pull

Power Amplifier using bipolar junction transistor and to plot its output characteristics.



1 Transistors

2 Capacitors

3 Resistors

4 Diodes

5 Power Supply

Bread Board

6 Signal Generator

7 CRO

8 Probe

9 Connecting wires

Theory:

Class B operation means that the Q point is located at cut off region hence collector current flows only for 180˚ of the input cycle. A complementary symmetry circuit uses two transistors NPN and PNP with identical characteristics. Both the transistors are connected as emitter follower with emitters connected together. The name push pull comes from the fact that one transistor drives current through the load in one direction (pushing) while the other drives current in opposite direction (pulling). The dc bias keeps transistors near cut off region. During the positive half cycle of the input, base of NPN transistor T2 is driven positive relative to its emitter. This makes the transistor ON. At the same time, other transistor remains in OFF state. A current determined by the supply voltage and load resistor gets established in the output circuit. During the negative half cycle of the input, transistor T1 becomes ON and T2 becomes OFF state. Now, output current flows in the opposite direction. Voltage developed across RL is like the input voltage. Diodes are functioning as compensating diodes to avoid thermal run away. Procedure:

1. Set up the circuit as shown in figure after testing all the components. Observe the output waveform on the CRO screen.

2. Set the frequency of input signal at 1 KHz and load impedance at 8Ω in power meter. Take the reading on the power meter for different values of load impedance. Plot load impedance versus output power. Note the impedance for which output power is Maximum. This is the value of optimum load.



Design:

Output requirements VO = 50mW

DC biasing conditions

+VCC= 12 V -VCC= -12V VCE1 = VCE2 = 6V P dc = 0.5 mW. Selection of RL: the output of an audio amplifier is usually connected to a loud speaker whose impedance is normally 8W. Take RL = 8.2 Ω. Design of RC

P dc = IC

2 × R = 78 mW

Then IC = 78 mA

IC (RC+ RL) = VCC - VCE =12V - 6V

RC+ RL = 76Ω

Then RC = 76 – 8.2 = 67.8Ω. Use 62Ω, 2W

Design of R

Base current of the transistors IB = IC / h FE = 78 mA / 40 = 1.95 mA.

We can see from the circuit VCC – (-VEE) = 2VR + 2VD where VR is the potential across the resistor R and VD is the diode drop.

Then VR = 11.3 V Assume the current through RS is 10IB so as to avoid loading of the biasing network by the base currents. Then R = VR / 10IB = 579 Ω. Use 560 Ω Selection of coupling capacitors CC1 and CCC2

Since the frequency of interest is in the audio range, Take CC1 = CCC2 = CCC3 = 10 µ F Observation:

S.No Resistance in Ω Power in mW

1

2

3

4

5

6

7

8

9

10




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the Complementary Symmetry Class B Push Pull Power Amplifier using

bipolar junction transistor was designed, simulated and its outputs were plotted.

Optimum Load =…………………..Ω



Circuit Diagram for Half Wave Rectifier:

Circuit Diagram for Full Wave Rectifier:



CHARACTERISTICS OF HALF WAVE AND FULL WAVE RECTIFIERS

----------------------------------------------------------------------------------------------

Aim: To study the characteristics of half wave and full wave rectifier and plot its output

characteristics.



1 Resistors

2 Diodes

3 Bread Board

4 Step down transformer

5 Voltmeter

6 Ammeter

7 CRO

8 Probe

9 Connecting wires

10 Power meter

Theory:

Rectifier changes ac to dc and it is an essential part of a power supply. The unique property of a diode permitting the current to flow only in one direction is utilized rectifiers. Half wave rectifier:

Mains power supply is applied at the primary of the step down transformer. The entire positive half cycles of the stepped down ac supply pass through the diode and the entire negative half cycles get eliminated. For a half wave rectifier, V rms = V m / 2; VDC = V m / ∏

Where, V rms = rms value of input VDC = Average value of the input V m = Peak value of output

Ripple factor r = ((V rms 2 / VDC

2) – 1) 1/2. It can be seen that r=1.21 by substituting the values.



Model Graph:



Full wave rectifier:

During the +ve half cycles of secondary voltage, the diode D1 is forward biased

and D2 is reverse biased. Then current flows through the diode D1, load resistor (RL) and

upper half of the transformer winding. During –ve half cycles, diode D2 becomes forward

biased and D1 becomes reverse biased. Then current flows through the diode D2, load

resistor (RL) and lower half of the transformer winding. Load current in both the cases is

in same direction.

For a full wave rectifier, V rms = V m / √2 VDC = 2V m / ∏

Where, V rms = rms value of input VDC = Average value of the input V m = Peak value of output

Ripple factor r = ((V rms 2 / VDC

2) – 1) 1/2. It can be seen that r=0.48 by substituting the values. Procedure:

1. Wire the half wave rectifier circuit after testing all the components using a multimeter.

2. Switch ON mains supply. Observe the transformer secondary voltage waveform and output voltage waveform across the load resistor, simultaneously on the CRO screen. Note down the peak values.

3. Calculate the ripple factor using the expression. 4. Repeat the above steps to full wave rectifier circuit.



Observation:

Half Wave Rectifier:

Without Filter

S.No Amplitude in volts Time in mS

1

With Filter


1

Full Wave Rectifier:

Without Filter


1

With Filter


1




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the characteristics of half wave and full wave rectifier were studied and its

output characteristics were drawn.

Ripple factor of half wave rectifier = …………………

Ripple factor of full wave rectifier = …………….……



Circuit Diagram:

Model Graph:



SERIES VOLTAGE REGULATOR USING TRANSISTORS

----------------------------------------------------------------------------------------------

Aim: To design, simulate and set up a series voltage regulator using transistors and to

plot its output characteristics.



1 Transistor

2 Resistors

3 Bread Board

4 Zener Diode

5 Power supply

6 Voltmeter

7 Multimeter

8 Connecting wires

Theory:

Figure shows a simple series voltage regulator using a transistor and Zener diode.

The circuit called a series voltage regulator because the load current passes through the

series transistor Q1 as shown in figure. The unregulated DC supply is fed to the input

terminals and the regulated output is obtained across the load. The Zener diode provides

the reference voltage.

Operation:

The base voltage of transistor Q1 is held to a relatively constant voltage across

the Zener diode. For example, if 8V Zener (VZ=8V) is used the base voltage of Q1 will

remain approximately 8V.

V out = VZ - VBE

Case (i): If the output voltage decreases, the increased base-emitter voltage causes

transistor Q1 to conduct more, thereby raising the output voltage. As a result, the output

voltage is maintained at a constant level.

Case (ii): If the output voltage increases, the decreased base-emitter voltage causes

transistor Q1 to conduct less, thereby reducing the output voltage. Consequently, the

output voltage is maintained at a constant level.



Observation:

Line Regulation:

S.No Vin (Volts) VO (Volts)

1

2

3

4

5

6

7

8

9

10

Load Regulation:

S.No IL (milli Amps ) VL (Volts)

1

2

3

4

5

6

7

8

9

10



The advantage of this circuit is that the changes in Zener current are reduced by

a factor β. Therefore, the effect of Zener impedance is greatly reduced and much more

stabilized output is obtained.

Load regulation:

The load regulation is the change in the regulated output voltage when the load

current is changed from minimum (no load) to maximum (full load).

Load regulation is denoted by LR and it is expressed as

LR = VNL – V FL

Where,

VNL = Load voltage with no load current

V FL= Load voltage with full load current

% Load Regulation = ((VNL – V FL) / V FL) Х 100

Line regulation:

The line regulation is the ratio of change in output voltage to the input voltage.

The % line regulation is given by,

% Line Regulation= ((Change in output Voltage) / (Change in input voltage)) Х 100

Procedure:

Line Regulation

1. Make the connections as per the circuit diagram.

2. Remove the load resistor, vary the input voltage (Vi) and measure the

corresponding output voltage (VO).

3. Plot VO versus Vi which gives line regulation curve.

4. Calculate the percentage line regulation.

Load Regulation


2. Keeping the input voltage constant, vary the load resistance and measure the

corresponding load current and load voltage.

3. Plot the load regulation characteristics (VL versus IL).

4. Mark the no load and full load output voltages on this graph.

5. Calculate the percentage load regulation

Limitations:

(i) Although the changes in Zener current are much reduced yet the

output is not absolutely constant. It is because both VBE and VZ

decrease with the increase in room temperature.

(ii) The output voltage cannot be changed easily as no such means is

provided.



Design:

A series voltage regulator is required to supply a current of 1 Amps at a constant

voltage of 6V. If the supply voltage is 10V and the Zener operates in the breakdown

region, design the circuit. Assume β=50, VBE=0.5V and minimum Zener current = 10mA.

The design steps require the determination of breakdown voltage and current

limiting resistance RS.

(1) Zener breakdown voltage:

The collector-emitter terminals are in series with the load. Therefore, the load

current must pass through the transistor.

Collector current (IC) = 1A

Base current (IB) = IC / β

= 1 / 50 = 20 mA

Output Voltage Vout = VZ - VBE

6 = VZ – 0.5

VZ = 6.5 V

Hence zener diode of break down voltage 6.5 is required

(2) To find the value of RS:

Voltage across RS = V in - VZ

= 10 – 6.5 = 3.5 V

RS = Voltage across RS / (IB + IZ)

= 3.5 V / (20 + 10) mA

RS = 117 Ω




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the series voltage regulator using transistors was designed, simulated and

its output characteristics were drawn.

% Load Regulation =………….

% Line Regulation =………….



Circuit Diagram:

Model Graph:



SHUNT VOLTAGE REGULATOR USING TRANSISTORS

----------------------------------------------------------------------------------------------

Aim: To design, simulate and set up a shunt voltage regulator using transistors and to

plot its output characteristics.



1 Transistor

2 Resistors

3 Bread Board

4 Zener Diode

5 Power supply

6 Voltmeter

7 Multimeter

8 Connecting wires

Theory:

A Shunt voltage regulator provides regulation by shunting current away from the

load to regulate the output voltage. The voltage drop across series resistance depends

upon the current supply to RL. The output voltage is equal to the sum of zener voltage

(VZ) and transistor base-emitter voltage (VBE).

V out = VZ + VBE

If the load resistance decreases, the current through base of the transistor

decreases. As a result, the less collector current is shunted. Therefore the load current

becomes larger, thereby maintaining the regulated voltage across the load. Reverse

happens should the load resistance increase.

Load regulation:

The load regulation is the change in the regulated output voltage when the load

current is changed from minimum (no load) to maximum (full load).

Load regulation is denoted by LR and it is expressed as

LR = VNL – V FL

Where,

VNL = Load voltage with no load current

V FL= Load voltage with full load current

% Load Regulation = ((VNL – V FL) / V FL) Х 100



Observation:

Line Regulation:

S.No Vin (Volts) VO (Volts)

1

2

3

4

5

6

7

8

9

10

Load Regulation:

S.No IL (milli Amps ) VL (Volts)

1

2

3

4

5

6

7

8

9

10



Line regulation:

The line regulation is the ratio of change in output voltage to the input voltage.

The % line regulation is given by,

% Line Regulation= ((Change in output Voltage) / (Change in input voltage)) Х 100

Drawbacks:

A shunt voltage regulator has the following drawbacks;

1. A large portion of the total current through RS flows through transistor rather

than to the load.

2. There is a considerable power loss in RS.

3. There are problems of over voltage protection in this circuit.

Procedure:

Line Regulation


2. Remove the load resistor, vary the input voltage (Vi) and measure the

corresponding output voltage (VO).

3. Plot VO versus Vi which gives line regulation curve.

4. Calculate the percentage line regulation.

Load Regulation


2. Keeping the input voltage constant, vary the load resistance and measure the

corresponding load current and load voltage.

3. Plot the load regulation characteristics (VL versus IL).

4. Mark the no load and full load output voltages on this graph.

5. Calculate the percentage load regulation.




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the shunt voltage regulator using transistors was designed, simulated and

its output characteristics were drawn.

% Load Regulation =………….

% Line Regulation =………….



Design a Darlington pair amplifier circuit for the given specifications

VCC = 12 V IE =1mA S = 10 hfe = 100 f = 50 Hz

AV ≤ 1, A1= A11 * A12

hfe1 = hfe2; A1= (hfe) 2

Apply KVL to output loop,

VCC = VCE + VE ----- (1)

VCE = VCC / 2

= 12 / 6 = 6V

VCE = 6V ----- (2)

From equation (1),

12 = 6 + VE

VE = 12 – 6 = 6V ----- (3)

VE = IE RE ----- (4)

RE = VE / IE = 6 / 1×10-3

RE = 6 K Ω ----- (5)

The Stability factor (s),

S = (1+ β) (1+ (RB / RE))

1+ β + (RB / RE)


S = 1+RB / RE

10 = 1+RB / RE

RB = (10-1) RE

= (10-1) *(6×103)

RB = 54 K Ω



DARLINGTON PAIR AMPLIFIER

------------------------------------------------------------------------------------------

Aim:

To design, simulate and test a performance of a Darlington Pair amplifier and to

plot its frequency response characteristics.



1 Transistor

2 Capacitors

3 Resistors

4 Power Supply

5 Bread Board

6 Signal Generator

7 CRO

8 Probe

9 Connecting wires

Theory:

In some occasions, the current gain and input impedance often an emitter

follower are insufficient to meet the requirement. In order to increase, the overall values

of circuit gain (Ai) and the input impedance, two transistors are connected in series in

emitter follower configuration such a circuit is known as Darlington amplifier. Note that

emitter of the first transistor is connected to the base of the second transistor and the

collector terminals of the two transistors are connected together.



To find VB:

VB = VBE + VE

= 0.7 + 6 = 6.7 V

To find R1 and R2:

VB = VCC R2 / R1 + R2 ------ (1)

R1 + R2 = VCC R2 / VB ------ (A)

RB = R1 R2 / R1 + R2 ------ (2)

R1 + R2 = R1 R2 / RB ------ (B)

From the Equations A and B, (LHS = RHS)

VCC R2 / VB = R1 R2 / RB

R1 = RB VCC / VB

= (54×103) * 12 / 6.7

R1 = 97 K Ω

We know that,

RB = R1 R2 / R1 + R2

Sub. RB = 54 K Ω and R1 = 97 K Ω in above equation,

54×103 = 97×103 * R2 / 97×10

3 + R2


R2 = 122 K Ω ≈ 120 K Ω

To find Ci and C0:

Ci = XCi = Zi / 10


h ie = h fe × re

re = VT / IE = 26×10-3 / 1×10-3 = 26 Ω

h ie = 100 × 26 = 2.6 K Ω

XCC = R1 ll R2 ll hie / 10 ----- RB = R1 R2 / R1 + R2

= 54 KΩ ll 2.6 KΩ / 10 = 54 KΩ

XCC = 250

XCC = 1/ 2∏f CC

CC = 1/ (2×3.14×50×250)

= 12×10-6 = 12 µ f Ci ≈ 10 µ f

XC0 = 1/ 2∏f C0

XC0 = Z0 /10 = R E / 10

XC0 = 6 ×103/ 10 = 600 Ω

C0 = 1/ (2×3.14×50×600)

= 5.3×10-6 = 5.3 µ f

C0 ≈ 5 µ f



The result is that emitter current of the first transistor is base current of the

second transistor. Therefore, the current gain of the pair is equal to product of individual

current gains i.e.,

β = β1 β2

Here the high current gain is achieved with the minimum use of components. The

biasing analysis is similar to that for one transistor except that two VBE drops are to be

considered.

Thus, Voltage across R2, V2 = VCC R2 / (R1 + R2)

Voltage across RE, VE = V2 - 2 VBE

Current through RE, IE2 = V2 - 2 VBE / RE

Since the transistors are directly coupled, IE1 = IB2.

Now, IB2 = IE2 / β2, IE1 = IE2 / β2.

In practice, the two transistors are put inside single transistor housing and three

terminals E, B and C are brought out as shown in figure. This three terminal device is

known as Darlington transistor. The Darlington transistor acts like a single transistor that

has high current gain and high input impedance.

IE1 = IE2 / β2.

Applications:

When emitter follower cannot provide the required high input impedance and

current gain, the Darlington amplifier is used.

Procedure:

1. Set up the circuit on the breadboard. Check the DC conditions and apply the

input sinusoidal signal from signal generator to the gate.

2. Obtain the amplified output. Take the output amplitude for various frequencies

for at the input.

3. Plot the frequency response curve. Find the bandwidth of the FET amplifier.



Observation:

V in =


1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

Model Graph: Darlington amplifier




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the Darlington Pair amplifier was designed, simulated and its

frequency response characteristics were drawn.

Band Width of the Amplifier (BW) = fH - fL.



Design a Class A power amplifier for the given specifications

RL = 220 Ω Pa = 500mW = 0.5Watts

Output power (Po) = VCC 2 / 8 RL

Po × 8 RL = VCC 2

0.5 × (8×220) = VCC 2

VCC 2 = 880

VCC = 30V

Apply KVL to output loop,

VCE = VCC / 2

= 30 / 2 = 15V

VCE = 15V

VCC = IL RL + VCE

VCC - VCE = IL RL

IL = VCC - VCE / RL

= (30 – 15) / 220

= 0.07 Amps

The Collector Power is given by,

PC = VCC IL

= 30 × 0.07

= 2 Watts

The Maximum output power is given by,

PO (max) = Vo 2 / RL

= (15)2 / 220

= 1 Watts



CLASS A POWER AMPLIFIER

------------------------------------------------------------------------------------------

Aim:

To design, simulate and test a performance of a Class A power amplifier and to

plot its frequency response characteristics.



1 Transistor

2 Capacitors

3 Resistors

4 Power Supply

5 Bread Board

6 Signal Generator

7 CRO

8 Probe

9 Connecting wires

Theory: Class A Amplifiers

The power amplifier is said to be class A amplifier if the Q point and the input

signal are selected such that the output signal is obtained for a full input cycle.

Key Point: For this class, position of the Q point is approximately at the midpoint of the

load line. For all values of input signal, the transistor remains in the active region and

never enters into cut-off or saturation region.



The input power is given by,

Pin = Vi 2 / Zi

Vi = 0.2 Volts


h ie = h fe × re

re = VT / IE = 26×10-3 / 1×10-3 = 26 Ω

h ie = 100 × 26 = 2.6 K Ω

Zi = 19.25

Pin = 0.2 2 / 19.25 = 2mWatts

The Efficiency is given by.

η = (PO (max) / PC) × 100

= (1 /2) × 100

ηηηη = 50 %%%%



When an A.C. input signal is applied, the collector voltage varies sinusoidally

hence the collector current also varies sinusoidally the collector current flows for 360°

(full cycle) of the input signal. In other words, the angle of the collector current flow is

360° i.e. one full cycle. The current and voltage waveforms for a class A operation are

shown with the help of output characteristics and the load line, in the Figure. As shown

in the Figure, for full input cycle, a full output cycle is obtained. Here signal is faithfully

reproduced, at the output, without any distortion. This is an important feature of a class

A operation. The efficiency of class A operation is very small.

Procedure:

1. Test all the components using a multimeter. Set up the circuit and verify dc

biasing conditions. To check the dc biasing conditions, remove input signal

and capacitors in the circuit.

2. Connect the capacitors in the circuit and apply a sinusoidal signal from signal

generator to the circuit input. Observe the input and output waveforms on the

CRO screen simultaneously.

3. Keeping the input amplitude constant vary the frequency of the input signal

from 0 Hz to 1 MHz. Measure the output amplitude corresponding to different

frequencies and enter it in tabular column.

4. Plot the frequency response characteristics on a semi-log graph sheet with

gain on Y-axis and log (f) on X-axis. Mark log (fL) and log (fH) corresponding

to 1/ √2 times of the maximum gain.

5. Calculate the bandwidth of the amplifier using the expression BW = fH - fL.



Observation: V in =


1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

Model Graph: Class A Amplifier




Marks Secured

Preparation 30

Performance 40

Viva Voce 10

Record 20

Total 100

Staff Signature

Result:

Thus the Class A amplifier was designed, simulated and its frequency

response characteristics were drawn.

Band Width of the Amplifier (BW) = fH - fL.



NO SUBSTITUTE FOR HARDWORK

ecl 302 electronic circuits - i and simulation lab

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