ecen720: high-speed links circuits and systems spring 2021...tx prbs7 jitter at 32.75gb/s tj: 5.39...
TRANSCRIPT
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Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
ECEN720: High-Speed Links Circuits and Systems
Spring 2021
Lecture 11: Clocking Architectures & PLLs
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Announcements • Lab 5 Report and Prelab 6 due Mar. 31
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Agenda• Clocking Architectures
• PLLs• Modeling• Noise transfer functions
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References• High-speed link clocking tutorial paper, PLL
analysis paper, and PLL thesis posted on website
• Posted PLL models in project section• Website has additional links on PLL and
jitter tutorials• Majority of today’s PLL material comes
from Fischette tutorial and M. Mansuri’sPhD thesis (UCLA)
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High-Speed Electrical Link System
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Clocking Terminology
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Synchronous• Every chip gets same frequency AND phase• Used in low-speed busses
Mesochronous• Same frequency, but unknown phase• Requires phase recovery circuitry
• Can do with or without full CDR• Used in fast memories, internal system interfaces,
MAC/Packet interfaces
Plesiochronous• Almost the same frequency, resulting in slowly
drifting phase• Requires CDR• Widely used in high-speed links
Asynchronous• No clocks at all• Request/acknowledge handshake procedure• Used in embeddded systems, Unix, Linux[Poulton]
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I/O Clocking Architectures• Three basic I/O architectures
• Common Clock (Synchronous)• Forward Clock (Source Synchronous)• Embedded Clock (Clock Recovery)
• These I/O architectures are used for varying applications that require different levels of I/O bandwidth
• A processor may have one or all of these I/O types
• Often the same circuitry can be used to emulate different I/O schemes for design reuse
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Common Clock I/O Architecture
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• Common in original computer systems• Synchronous system by design (no active deskew)• Common bus clock controls chip-to-chip transfers• Requires equal length routes to chips to minimize clock skew• Data rates typically limited to ~100Mb/s
[Krauter]
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Common Clock I/O Cycle Time
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[Krauter]
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Common Clock I/O Limitations• Difficult to control clock skew and propagation delay
• Need to have tight control of absolute delay to meet a given cycle time
• Sensitive to delay variations in on-chip circuits and board routes
• Hard to compensate for delay variations due to low correlation between on-chip and off-chip delays
• While commonly used in on-chip communication, offers limited speed in I/O applications
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Forward Clock I/O Architecture
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• Common high-speed reference clock is forwarded from TX chip to RX chip• Mesochronous system
• Used in processor-memory interfaces and multi-processor communication• Intel QPI• Hypertransport
• Requires one extra clock channel
• “Coherent” clocking allows low-to-high frequency jitter tracking
• Need good clock receive amplifier as the forwarded clock is attenuated by the channel
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Forward Clock I/O Limitations
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• Clock skew can limited forward clock I/O performance• Driver strength and loading
mismatches• Interconnect length
mismatches
• Low pass channel causes jitter amplification
• Duty-Cycle variations of forwarded clock
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Forward Clock I/O De-Skew
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• Per-channel de-skew allows for significant data rate increases
• Sample clock adjusted to center clock on the incoming data eye
• Implementations• Delay-Locked Loop and Phase
Interpolators• Injection-Locked Oscillators
• Phase Acquisition can be • BER based – no additional
input phase samplers• Phase detector based
implemented with additional input phase samplers periodically powered on
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Forward Clock I/O Circuits
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• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit• DLL/PI• Injection-Locked Oscillator
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Embedded Clock I/O Architecture
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• Can be used in mesochronousor plesiochronous systems
• Clock frequency and optimum phase position are extracted from incoming data stream
• Phase detection continuously running
• CDR Implementations• Per-channel PLL-based• Dual-loop w/ Global PLL &
• Local DLL/PI• Local Phase-Rotator PLLs
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Embedded Clock I/O Limitations
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• Jitter tracking limited by CDR bandwidth• Technology scaling allows
CDRs with higher bandwidths which can achieve higher frequency jitter tracking
• Generally more hardware than forward clock implementations• Extra input phase samplers
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Embedded Clock I/O Circuits
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• TX PLL
• TX Clock Distribution
• CDR• Per-channel PLL-based• Dual-loop w/ Global PLL &
• Local DLL/PI• Local Phase-Rotator PLLs• Global PLL requires RX
clock distribution to individual channels
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Xilinx 0.5-32Gb/s Transceiver Clocking
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• LC-PLL with 2 LC-VCOs used to cover high data rates (8-32Gb/s)
• Ring-PLL used for lower data rates• CML clock distribution with active inductive loads used
for low jitter
Active Inductor based Clock Distribution
Frac-N LC PLL1, 2
Ring PLL
DCCIQ CAL
Receiver
DCCTransmitter
Channels 1-4
I/Q1, I/Q2
∑
VCOLB
PPF
VCOHB
2PI (D,X,S)
Technology CMOS 16nm FinFET Power Supply (Vavcc, Vavtt, Vaux) 0.9 V, 1. 2V, 1.8 V
Frequency range 500 Mb/s – 32.75 Gb/s Transceiver Quad area 2.625 mm × 2.218 mm
LC PLL range 8-16.375 GHz Ring PLL range 2-6.25 GHz
TX PRBS7 jitter at 32.75Gb/s TJ: 5.39 ps, RJ: 190 fs 32.75Gb/s RX JTOL @ 30MHz
@ 100MHz 0.45 UI 0.6 UI
Channel loss at 32.75Gb/s 30 dB Measured BER at 32.75Gb/s < 10-15
Power at 32.75Gb/s with DFE 577mW/ch (17.6pJ/b)
[Upadhyaya VLSI 2016]
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PLLs• PLL modeling
• PLL noise transfer functions
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PLL Block Diagram
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[Perrott]
• A phase-locked loop (PLL) is a negative feedback system where an oscillator-generated signal is phase AND frequency locked to a reference signal
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PLL Applications• PLLs applications
• Frequency synthesis• Multiplying a 100MHz reference clock to 10GHz
• Skew cancellation• Phase aligning an internal clock to an I/O clock
• Clock recovery• Extract from incoming data stream the clock frequency and
optimum phase of high-speed sampling clocks
• Modulation/De-modulation• Wireless systems• Spread-spectrum clocking
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Forward Clock I/O Circuits
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• TX PLL
• TX Clock Distribution
• Replica TX Clock Driver
• Channel
• Forward Clock Amplifier
• RX Clock Distribution
• De-Skew Circuit• DLL/PI• Injection-Locked Oscillator
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Embedded Clock I/O Circuits
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• TX PLL
• TX Clock Distribution
• CDR• Per-channel PLL-based• Dual-loop w/ Global PLL &
• Local DLL/PI• Local Phase-Rotator PLLs• Global PLL requires RX
clock distribution to individual channels
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PLL Design Challenges
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• Board-level reference clock frequencies don’t scale often• 156MHz is a common frequency
• RX CDR bandwidth is hard to scale with PAM4 signaling and ADC-based front-ends • Typically 2-4MHz
• PLL bandwidth must be kept less than 10MHz for stability and to filter reference jitter
• VCO phase noise at low-frequency offsets due to flicker noise must be suppressed
32.75Gbps Transceiver PLL Simulated Jitter Numbers
Receiver Type PLL PN @1MHz CDR BW RJ RJ in UIAnalog based RX -92.4dBc/Hz 12.7MHz 160.7fs 5.26mUIADC based RX -92.4dBc/Hz 2MHz 407fs 13.3mUI
[Turker ISSCC 2019]
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Charge Pump PLL
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• Charge pump PLL is a common implementation• Type-2 (2 integrators) allows for ideally zero phase error between
the input and feedback phase• Requires a stabilizing zero that is realized with the filter resistor• A secondary capacitor C2 is often added for additional filtering to
reduce reference spurs• Modeled as a third-order system
UP
DQ
R
DQ
R
PFD
DNVctrl
R
C1
C2
VCO
1/NDivider
out
in
fb
ICP
ICP
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Linear PLL Model
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inKVCO
sKPD
1N
e
Phase Detector
F(s)Vctrl
fb
out
Loop Filter VCO
Divider
𝐾𝐼2𝜋
𝐹 𝑠
1𝐶 𝑠 1
𝑅𝐶
𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
𝐻 𝑠𝜙 𝑠𝜙 𝑠
𝐾 𝐾𝐶 𝑠 1
𝑅𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
For Charge Pump PLL:
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Understanding PLL Frequency Response• Linear “small-signal” analysis is useful for understand PLL dynamics if
• PLL is locked (or near lock)• Input phase deviation amplitude is small enough to maintain operation in
lock range• Frequency domain analysis can tell us how well the PLL tracks the input
phase as it changes at a certain frequency• PLL transfer function is different depending on which point in the loop
the output is responding to
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Input phase response VCO output response
[Fischette]
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Input Noise Transfer Function
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Input Phase Noise:
n,inKVCO
sKPD
1N
e
Phase Detector
F(s)Vctrl
fb
out
Loop Filter VCO
Divider
𝐻 𝑠𝜙 𝑠𝜙 𝑠
𝐾 𝐾𝐶 𝑠 1
𝑅𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
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Input Noise Transfer Function
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Input Phase Noise: 𝐻 𝑠𝜙 𝑠𝜙 𝑠
𝐾 𝐾𝐶 𝑠 1
𝑅𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
Parameter
Fref 156MHz
N 90
Fvco 14GHz
Icp 100uA
R 22.7k
C1 7.0pF
C2 500fF
Kvco 2π*1GHz/V
f3dB 5.9MHz
Phase Margin 60°
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VCO Noise Transfer Function
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VCO Phase Noise:
Voltage Noise on VCO Inputs:
inKVCO
sKPD
1N
e
Phase Detector
F(s)Vctrl
fb
out
Loop Filter VCO
Divider
vn,vco
n,vco
𝐻 𝑠𝜙 𝑠𝜙 𝑠
𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
𝑇 𝑠𝜙 𝑠𝑣 𝑠
𝐾 𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
KVCO is different if the input is at the Vcntrl input (KVCO) or supply (KVdd)
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VCO Noise Transfer Function
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Parameter
Fref 156MHz
N 90
Fvco 14GHz
Icp 100uA
R 22.7k
C1 7.0pF
C2 500fF
Kvco 2π*1GHz/V
f3dB 5.9MHz
Phase Margin 60°
VCO Phase Noise:
Voltage Noise on VCO Inputs:
𝐻 𝑠𝜙 𝑠𝜙 𝑠
𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
𝑇 𝑠𝜙 𝑠𝑣 𝑠
𝐾 𝑠 𝑠 𝐶 𝐶𝑅𝐶 𝐶
𝑠 𝐶 𝐶𝑅𝐶 𝐶 𝑠 𝐾 𝐾
𝑁𝐶 𝑠 𝐾 𝐾𝑁𝑅𝐶 𝐶
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28GHz PLL Phase Noise Example
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• Charge pump noise dominates at low frequencies• VCO noise at mid-band and high frequencies• Output buffers outside loop dominate at high frequencies
With ~100fs target, no single dominant source -every component contributes
Phas
e No
ise (d
Bc/H
z)
Frequency Offset (Hz) [Turker ISSCC 2019]
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PLL Noise Transfer Function Take-Away Points
• The way a PLL shapes phase noise depends on where the noise is introduced in the loop
• Optimizing the loop bandwidth for one noise source may enhance other noise sources
• Generally, the PLL low-pass shapes input phase noise, band-pass shapes VCO input voltage noise, and high-pass shapes VCO/clock buffer output phase noise
33
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Oscillator Noise
34
Jitter
[McNeill]
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Oscillator Phase Noise Model
35
dBc/Hz PowerCarrier
Density Spectral Noise
log10fL
f
f
ff
QPFkTfL fo
sig
3/12
12112log10Leeson’s Model:
• For improved model see Hajimiri papers
[Perrott]
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Open-Loop VCO Jitter
• Measure distribution of clock threshold crossings• Plot as a function of delay T
36
[McNeill]
T
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Open-Loop VCO Jitter
• Jitter is proportional to sqrt(T)• is VCO time domain figure of merit
37
TTOLT
[McNeill]
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VCO in Closed-Loop PLL Jitter
38
• PLL limits for delays longer than loop bandwidth L
LL f 21
[McNeill]
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Ref Clk-Referenced vs Self-Referenced
39
[McNeill]
Ref Clock for Frequency Synthesis PLL
• Generally, we care about the jitter w.r.t. the ref. clock (x)• However, may be easier to measure w.r.t. delayed version of output clk
• Due to noise on both edges, this will be increased by a sqrt(2) factor relative to the reference clock-referred jitter
CDR Example
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Converting Phase Noise to Jitter
40
• Actual integration range depends on application bandwidth• fmin set by assumed CDR tracking bandwidth• fmax set by Nyquist frequency (f0/2)
• Most exact approach
• RMS jitter for T accumulation
• As T goes to ∞ 22 2
0
2 20To oR S f df
[Mansuri]
02 22
20
2
2
where is the system jitter transfer function
f
T syso
sys
S f H f df
H f
𝜎8𝜔
𝑆 𝑓 𝑠𝑖𝑛 𝜋𝑓Δ𝑇 𝑑𝑓
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112Gb/s PAM4 PLL Phase Noise Measurement
41[Turker ISSCC 2019]
0
0
0
EL1
EL1
LoopBW 3 kHz
Frequency Offset (Hz)1e6 1e81e7 1e101e9
Phas
e N
oise
(dB
C/H
z)
-60
-80
-100
-120
-140
Measured Phase Noise at 28GHz TX Output <100fs Integrated RJRMS
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PLL Linear Phase Model
42
outref
out(s)ref(s)
20log10
3dB = 1.47Mrad/s
out(s)vcon(s)
20log10
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PLL Linear Phase Model:Frequency Step Response
43
outref
ref(s)=Frequency Step Input: s2 = Mrad/sec
32s2
No Cycle Slips Observedwith Linear Model
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PLL Behavioral Model• From my MSc thesis:
http://www.ece.tamu.edu/~spalermo/docs/msc_thesis_sam_palermo.pdf• Written in SpectreHDL• Also look at CppSim: http://www.cppsim.com/
44
// Multi-Band Phase Locked Loop Frequency Synthesizer Macromodel// Main Spectre File// Samuel Palermosimulator lang=spectreinclude "/home/samuel/research/pll/macromodels/pd/dig_pfd/dig_pfd.def"include "/home/samuel/research/pll/macromodels/lpf/lpf.def"ahdl_include "/home/samuel/research/pll/macromodels/vco/vco.def"ahdl_include "/home/samuel/research/pll/macromodels/vco/switch_vco.def"ahdl_include+ "/home/samuel/research/pll/macromodels/divider/divider.def"include "/home/samuel/research/pll/macromodels/vco/reference.def"// Power Supplyvdd dd 0 vsource dc=1// Reference Signalxref 0 control fref referencevcontrol control 0 vsource type=pwl wave=[0 0.64 1u 0.64]// Digital Tri-State Phase/Frequency Comparatorxdig_pfd 0 dd fref fvco up upbar down downbar dig_pfd// Charge Pumpiup dd 1 isource dc=25uidown 2 0 isource dc=25ugup 1 vd up 0 relay vt1=0 vt2=1 ropen=100M rclosed=1mgupbar 1 0 upbar 0 relay vt1=0 vt2=1 ropen=100M rclosed=1mgdown vd 2 down 0 relay vt1=0 vt2=1 ropen=100M rclosed=1mgdownbar dd 2 downbar 0 relay vt1=0 vt2=1 ropen=100M rclosed=1m// Loop Filterxfilter 0 vd lpfgvdgnd vd 0 vd_gnd 0 relay vt1=0 vt2=1 ropen=100M rclosed=10 // Voltage Controlled Oscillator//xvco vd out vco (gain=40e6 fc=256e6)xvco 0 vd out nv_temp vd_gnd+ switch_vco (u=0.8 d=-0.8 gain=40e6 fc=256e6)// Dividerxdivider 0 out fvco buffer n_temp divider (divisor=32)op dc
timedom tran stop=20u step=20p ic=all maxstep=20p skipdc=yes relref=alllocalsimulator lang=spice.ic vd=0save vd control fref fvco nv_temp vd_gnd.OPTIONS rawfmt=psfbin save=selected diagnose=yes vabstol=.01 + reltol=.99
***********************************************************************// Digital Phase Frequency Detector Macromodel// Samuel Palermosubckt dig_pfd (gnd dd fref fvco up upbar down downbar)ahdl_include "/home/samuel/research/pll/macromodels/pd/dig_pfd/dff.def"ahdl_include+ "/home/samuel/research/pll/macromodels/pd/dig_pfd/nand.def"xdffup gnd dd fref up upbar r dffxdffdown gnd dd fvco down downbar r dffxnand gnd up down r nandends dig_pfd
***********************************************************************// D Flip Flop Macromodel// Samuel Palermomodule dff(gnd, D, CLK, Q, QBAR, R) ()node [V, I] gnd, D, CLK, Q, QBAR, R ;{
real Q_temp;real QBAR_temp;initial {
Q_temp=0;QBAR_temp=1;}
analog {if ($threshold (V(CLK, gnd)-1, 1)) {
if (V(D,gnd)==1) {Q_temp=1;
QBAR_temp=0;}else {
Q_temp=0;QBAR_temp=1;
}}if (V(R, gnd)==0) {
Q_temp=0;QBAR_temp=1;
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PLL Frequency Step Response:Linear vs Behavioral Model
45
ref(s)=Frequency Step Input: s2 = Mrad/sec
32s2
No Cycle Slips Observedwith Linear Model
Cycle Slips
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Next Time• CDRs
• The following slides provide more details on PLL circuits. This 620 material may useful for the project, but won’t be covered in detail on Exam 2.
46
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Open-Loop PLL Transfer Function
47
ignoring C1:
with C1:
[Mansuri]
(2nd order)
(3rd order)
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Open-Loop PLL Transfer Function
48
with C1 (3rd order)w/o C1 (2nd order)
[Mansuri]
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Closed-Loop PLL Transfer Function
49
ignoring C1:
[Mansuri]
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PLL Natural Frequency and Damping Factor
50
22 2 nnss Standard 2nd-order denominator:
Damping Factor:
Natural Frequency:
21
23 1 aandB
VCOPD
n
VCOPD
n
KKN
KKNa
412 2
Loop Bandwidth:
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Damping Factor Impact
• If damping factor is too low, frequency peaking occurs• Damping factor ~1 is usually preferred
• Excessively high damping also causes peaking• Need 3rd order model to observe this
51
[Fischette]
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Damping Factor Impact
• Peaking in frequency domain leads to ringing in the time domain
52
ref(s)=Frequency Step Input: s2
KPD = 25uA/2KVCO = 240MHz/V
N = 32n = 1 (normalized)
= 0.1
= 0.5
= 0.707 = 1
= 2
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Charge-Pump PLL Circuits• Phase Detector
• Charge-Pump• Loop Filter• VCO• Divider
53
ref
fb
out
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Phase Detector
• Detects phase difference between feedback clock and reference clock• The loop filter will filter the phase detector output, thus to characterize
phase detector gain, extract average output voltage (or current for charge-pump PLLs)
54
ref
fb
e
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Analog Multiplier Phase Detector
• If 1=2 and filtering out high-frequency term
55
tA 11 cos
tA 22 cos
tAAtAA
2121
2121 cos
2cos
2
is mixer gain
cos
221AAty
• Near lock region of /2:
2221AAty
221AAKPD
[Razavi]
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XOR Phase Detector
56
• Sensitive to clock duty cycle[Razavi]
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XOR Phase Detector
57
[Perrott]
Width is same for both leading and lagging phase difference!
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Cycle Slipping• If there is a frequency difference between the input
reference and PLL feedback signals the phase detector can jump between regions of different gain• PLL is no longer acting as a linear system
58
[Perrott]
(negative feedback operation)(positive feedback operation)
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Cycle Slipping
• If frequency difference is too large the PLL may not lock59
[Perrott]
Cycle Slipping
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Phase Frequency Detector (PFD)• Phase Frequency Detector allows
for wide frequency locking range, potentially entire VCO tuning range
• 3-stage operation with UP and DOWN outputs
• Edge-triggered results in duty cycle insensitivity
60
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PFD Transfer Characteristic
• Constant slope and polarity asymmetry about zero phase allows for wide frequency range operation
61
UP=1 & DN=-1
[Perrott]
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PFD Deadzone• If phase error is small, then short output pulses are produced by PFD• Cannot effectively propagate these pulses to switch charge pump• Results in phase detector “dead zone” which causes low loop gain and
increased jitter• Solution is to add delay in PFD reset path to force a minimum UP and
DOWN pulse length
62
[Fischette]
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PFD Operation
63[Fischette]
Min. Pulse Width
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Charge-Pump PLL Circuits• Phase Detector
• Charge-Pump• Loop Filter• VCO• Divider
64
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Charge Pump
• Converts PFD output signals to charge• Charge is proportional to PFD pulse widths
65
I
I
VCO ControlVoltage
C1
R
C2
Charging
Discharging
VDD
VSS
UP
DOWN
CPI
21
PFD-CP Gain:
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Simple Charge Pump
• Issues• Switch resistance can impact UP/DN current matching as a function of Vctrl• Clock feedthrough and charge injection from switches onto Vctrl• Charge sharing between current source drain nodes’ capacitance and Vctrl
66
[Razavi]
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Charge Pump Mismatch
• PLL will lock with static phase error• Extra “ripple” on Vctrl
• Results in frequency domain spurs at the reference clock frequency offset from the carrier
67
[Razavi]
Ideal locked condition, but CP mismatch Actual locked condition w/ CP mismatch
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Charge Pump w/ Improved Matching
• Amplifier keeps current source Vds voltages constant resulting in reduced transient current mismatch
68
[Young JSSC 1992]
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Charge Pump w/ Reversed Switches• Swapping switches
reduces charge injection• MOS caps (Md1-4) provide
extra charge injection cancellation
• Helper transistors Mx and My quickly turn-off current source
• Dummy brand helps to match PFD loading
69
[Ingino JSSC 2001]
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Charge-Pump PLL Circuits• Phase Detector
• Charge-Pump• Loop Filter• VCO• Divider
70
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Loop Filter
• Lowpass filter extracts average of phase detector error pulses
71
I
I
VCO ControlVoltage
C1
R
C2
Charging
Discharging
VDD
VSSF(s)
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Loop Filter Transfer Function
72
• Neglecting secondary capacitor, C2
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Loop Filter Transfer Function
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• With secondary capacitor, C2
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Why have C2?• Secondary capacitor smoothes control voltage ripple• Can’t make too big or loop will go unstable
• C2 < C1/10 for stability• C2 > C1/50 for low jitter
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Control Voltage Ripple
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Filter Capacitors• To minimize area, we would like to use highest density caps
• Thin oxide MOS cap gate leakage can be an issue• Similar to adding a non-linear parallel resistor to the capacitor• Leakage is voltage and temperature dependent• Will result in excess phase noise and spurs
• Metal caps or thick oxide caps are a better choice• Trade-off is area
• Metal cap density can be < 1/10 thin oxide caps
• Filter cap frequency response can be relatively low, as PLL loop bandwidths are typically 1-50MHz
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Charge-Pump PLL Circuits• Phase Detector
• Charge-Pump• Loop Filter• VCO• Divider
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Voltage-Controlled Oscillator
• Time-domain phase relationship
77
VDDVDD/20
0 1KVCO
tvKtt cVCOoutout 00
dtdt tvKtt cVCOoutout Laplace Domain Model
out(t)
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Voltage-Controlled Oscillators (VCO)• Ring Oscillator
• Easy to integrate• Wide tuning range (5x)• Higher phase noise
• LC Oscillator• Large area• Narrow tuning range (20-30%)• Lower phase noise
78
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Barkhausen’s Oscillation Criteria
• Sustained oscillation occurs if
• 2 conditions:• Gain = 1 at oscillation frequency 0• Total phase shift around loop is n360 at oscillation frequency 0
79
jHjH
1Closed-loop transfer function:
1jH
n
[Sanchez]
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Ring Oscillator Example
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[Sanchez]
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Ring Oscillator Example
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[Sanchez]
• 4-stage oscillator• A0 = sqrt(2)• Phase shift = 45
• Easier to make a larger-stage oscillator oscillate, as it requires less gain and phase shift per stage
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LC Oscillator Example
221
22211
221
22
12
11
1
1
1
CRCL
LRjsZ
sCRsCLsLRsZ
S
Seq
S
Seq
LC tank impedance
• Oscillation phase shift condition satisfied at the frequency when the LC (and R) tank load displays a purely real impedance, i.e. 0 phase shift
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LC Oscillator Example• Transforming the series loss
resistor of the inductor to an equivalent parallel resistance
83
SPP
SP R
LRCCLRLL
221
1221
2
1 ,,1
PPCL1
1
RP
[Razavi]
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LC Oscillator Example
84
12 PmRg
PPCL1
1
Loop Gain
• Phase condition satisfied at
• Gain condition satisfied when
[Razavi]
• Can also view this circuit as a parallel combination of a tank with loss resistance 2RP and negative resistance of 2/gm
• Oscillation is satisfied when
Pm
Rg
1
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Supply-Tuned Ring Oscillator
85
thc
stageDVCO VV
nCnTT
22
stagec
VCOVCO nCV
fK2
[Sidiropoulos VLSI 2000]
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Current-Starved Ring Oscillator
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[Sanchez]
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Capacitive-Tuned Ring Oscillator
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Symmetric Load Ring Oscillator
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[Maneatis JSSC 1996 & 2003]
• Symmetric load provides frequency tuning at excellent supply noise rejection
• See Maneatis papers for self-biased techniques to obtain constant damping factor and loop bandwidth (% of ref clk)
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LC Oscillator• A variable capacitor
(varactor) is often used to adjust oscillation frequency
• Total capacitance includes both tuning capacitance and fixed capacitances which reduce the tuning range
89
fixedtunePPPosc CCLCL
11
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Varactors• pn junction varactor
• Avoid forward bias region to prevent oscillator nonlinearity
90
• MOS varactor• Accumulation-mode devices have better Q than inversion-mode
[Perrott]
n-well[Razavi]
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Charge-Pump PLL Circuits• Phase Detector
• Charge-Pump• Loop Filter• VCO• Divider
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Loop Divider
• Time-domain model
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tN
t outfb 1
tN
tN
t outoutfb 1dt1
[Perrott]
out(t) fb(t)
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Basic Divide-by-2
• Divide-by-2 can be realized by a flip-flip in “negative feedback”
• Divider should operate correctly up to the maximum output clock frequency of interest PLUSsome margin
93
[Perrott]
[Fischette]
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Divide-by-2 with TSPC FF
• Advantages• Reasonably fast, compact size, and no static power• Requires only one phase of the clock
• Disadvantages• Signal needs to propagate through three gates per input cycle• Need full swing CMOS inputs• Dynamic flip-flop may have issues at very low frequency operation (test
mode) depending on process leakage94
True Single Phase Clock Flip-FlopDivider Equivalent CircuitNote: output inverter not in left schematic
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Divide-by-2 with CML FF
95
• Advantages• Signal only propagates through two CML gates per input cycle• Accepts CML input levels
• Disadvantages• Larger size and dissipates static power• Requires differential input• Need tail current biasing
• Additional speedup (>50%) can be achieved with shunt peaking inductors
[Razavi]
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Binary Dividers:Asynchronous vs Synchronous
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Asynchronous Divider
Synchronous Divider
• Advantages• Each stage runs at lower frequency,
resulting in reduced power• Reduced high frequency clock
loading• Disadvantage
• Jitter accumulation
• Advantage• Reduced jitter
• Disadvantage • All flip-flops work at maximum
frequency, resulting in high power• Large loading on high frequency
clock[Perrott]
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Jitter in Asynchronous vs Synchronous Dividers
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Asynchronous
Synchronous
• Jitter accumulates with the clock-to-Q delays through the divider
• Extra divider delay can also degrade PLL phase margin
• Divider output is “sampled” with high frequency clock
• Jitter on divider clock is similar to VCO output
• Minimal divider delay[Perrott]
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Dual Modulus Prescalers
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2/3
MC=0 3MC=1 2
15/16
Synchronous 3/4 Asynchronous 4• For /15, first prescaler circuit divides by 3 once and 4 three times
during the 15 cycles
[Razavi]
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Injection-Locked Frequency Dividers
• Superharmonic injection-locked oscillators (ILOs) can realize frequency dividers
• Faster and lower power than flip-flop based dividers• Injection locking range can be limited
99
LC-oscillator type (/2) Ring-oscillator type (/3)
[Verma JSSC 2003, Rategh JSSC 1999] [Lo CICC 2009]
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Example PLL Design Procedure• Design procedure for a 100-300MHz frequency synthesizer• Step 1 – Determine VCO Tuning Range
• Needs to be at least the output frequency range plus some margin (10-20%) dependent on PVT tolerance
100
*300MHz - 100 Range Tuning VCO
• *Note if you want the frequency extremes (100 or 300MHz) you probably want to add some margin here
• Step 2 – Determine Loop Division Ratio, N• This is a function of what reference clocks you have access to,
loop bandwidth, dominant noise sources32N
• Step 3 – Determine Damping Factor• Damping factors between 0.5 and 2 are reasonable, with 0.7 or 1
commonly chosen707.0
21
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Example PLL Design Procedure• Step 4 – Determine natural frequency, n
• This is a function of the desired loop bandwidth and also the damping factor
• Maximum loop bandwidth should be less than 1/10th the input reference clock for the loop to act as a continuous-time system
101
MHz125.332
100MHz Frequency ReferenceInput Lowest
• Set the loop bandwidth with some margin - 75% of max value s
MraddB 47.1kHz5.312275.03
• For a damping factor of 0.707
skrads
MraddB
n 71406.2
47.1
06.23
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Example PLL Design Procedure• Step 5 – Determine KVCO
• This is a function of the VCO and charge pump operating voltage range
• Here I use a combination of discrete tuning caps, resulting in multiple frequency bands over the total frequency range
102
Freq
uenc
y (M
Hz)
VCO Control Voltage
Channel 4 (235 - 300MHz)
Channel 2 (145 - 210MHz)
Channel 1 (100 - 165MHz)
Kvco = 40MHz/V
100
145
190
235
165
210
255
300
Channel 3 (190 - 255MHz)
Voltage Range = 1.6V
sV
MradKVCO 2551.6V
MHz652
• Step 6 – Determine Charge Pump Current & Filter Cap
pF
skradsVMradA
C
AI
2.62714322
25525
25Set
21
• Step 7 – Determine Filter R and Secondary Cap
kpF
skradC
Rn
8.312.62714
707.022
1
pFCpFCC 622.610 2
12