ecen720: high-speed links circuits and systems spring 2021 · 2021. 1. 22. · sam palermo analog &...
TRANSCRIPT
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Sam PalermoAnalog & Mixed-Signal Center
Texas A&M University
ECEN720: High-Speed Links Circuits and Systems
Spring 2021
Lecture 2: Channel Components, Wires, & Transmission Lines
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Announcements• HW1 due Jan 27
• Lab• Lab begins on Jan 27 via Zoom• Prelab 1 due on Jan 29• Lab 1 report and Prelab 2 due on Feb 3• TA Ruida Liu
• [email protected]• Office Hours M 3PM-5PM, Zoom
• Reference Material Posted on Website• TDR theory application note • S-parameter notes
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Agenda• Channel Components• IC Packages, PCBs, connectors, vias, PCB Traces
• Wire Models• Resistance, capacitance, inductance
• Transmission Lines• Propagation constant• Characteristic impedance• Loss• Reflections• Termination examples• Differential transmission lines
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Channel Components
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Edge connector
Packaged SerDes
Line card trace
Backplane trace
Via stub
The ChannelTx IC
Pkg Line cardtrace
Edge connector
Line cardvia
Backplanevia
Backplane16” trace
Edge connector
Line cardtrace
Rx IC
Pkg Backplanevia
Line cardvia
[Meghelli (IBM) ISSCC 2006]
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IC Packages• Package style depends
on application and pin count
• Packaging technology hasn’t been able to increase pin count at same rate as on-chip aggregate bandwidth• Leads to I/O constrained
designs and higher data rate per pin
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Package Type Pin CountSmall Outline Package (SOP) 8 – 56Quad Flat Package (QFP) 64 - 304Plastic Ball Grid Array (PBGA) 256 - 420Enhanced Ball Grid Array (EBGA) 352 - 896Flip Chip Ball Grid Array (FC-BGA) 1089 - 2116
SOP
PBGA
QFP
FC-BGA
[Package Images - Fujitsu]
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IC Package Examples• Wirebonding is most
common die attach method
• Flip-chip packaging allows for more efficient heat removal
• 2D solder ball array on chip allows for more signals and lower signal and supply impedance
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Standard Wirebond Package
Flip-Chip/Wirebond Package
Flip-Chip/Solder Ball Package
[Package Images - Fujitsu]
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IC Package Model
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Bondwires• L ~ 1nH/mm•Mutual L “K”• Ccouple ~ 20fF/mm
Package Trace• L ~ 0.7-1nH/mm•Mutual L “K”• Clayer ~ 80-90fF/mm•Ccouple ~ 40fF/mm
[Dally]
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IC Package Model Comparisons
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• FCB packaging allows for much less chip interface impedance
[Intel]
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Printed Circuit Boards• Components soldered on
top (and bottom)
• Typical boards have 4-8 signal layers and an equal number of power and ground planes
• Backplanes can have over 30 layers
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PCB Stackup• Signals typically on top and
bottom layers
• GND/Power plane pairs and signal layer pairs alternate in board interior
• Typical copper trace thickness• “0.5oz” (17.5um) for signal layers• “1oz” (35um) for power planes
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[Dally]
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Connectors• Connectors are used
to transfer signals from board-to-board
• Typical differential pair density between 16-32 pairs/10mm
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[Tyco]
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Connectors• Important to maintain proper differential
impedance through connector
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• Crosstalk can be an issue in the connectors
[Tyco]
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Vias• Used to connect PCB layers
• Made by drilling a hole through the board which is plated with copper• Pads connect to signal layers/traces• Clearance holes avoid power planes
• Expensive in terms of signal density and integrity• Consume multiple trace tracks• Typically lower impedance and create
“stubs”
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[Dally]
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Impact of Via Stubs at Connectors
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• Legacy BP has default straight vias• Creates severe nulls which kills signal integrity
• Refined BP has expensive backdrilled vias
Edge connector
Packaged SerDes
Line card traceBackplane trace
Via stub
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PCB Trace Configurations• Microstrips are signal
traces on PCB outer surfaces• Trace is not enclosed
and susceptible to cross-talk
• Striplines are sandwiched between two parallel ground planes• Has increased isolation
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[Johnson]
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Wire Models• Resistance
• Capacitance
• Inductance
• Transmission line theory
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Wire Resistance• Wire resistance is determined by material
resistivity, ρ, and geometry
• Causes signal loss and propagation delay
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whl
AlR 2r
lAlR
[Dally]
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Wire Capacitance• Wire capacitance is determined
by dielectric permittivity, ε,and geometry
• Best to use lowest εr• Lower capacitance• Higher propagation velocity
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swC 12log
2rr
C rsC log
hsswC
4log2
[Dally]
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Wire Inductance• Wire inductance is determined by material
permeability, µ, and closed-loop geometry
• For wire in homogeneous medium
• Generally
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CL
H/m104 70
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Wire Models• Model Types
• Ideal• Lumped C, R, L• RC transmission line• LC transmission line• RLGC transmission line
• Condition for LC or RLGC model (vs RC)
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LRf20
Wire R L C >f (LC wire)AWG24 Twisted Pair 0.08Ω/m 400nH/m 40pF/m 32kHzPCB Trace 5Ω/m 300nH/m 100pF/m 2.7MHzOn-Chip Min. Width M6 (0.18µm CMOS node) 40kΩ/m 4µH/m 300pF/m 1.6GHz
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RLGC Transmission Line Model
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t
txILtxRIx
txV
,,,
t
txVCtxGVx
txI
,,,
0 dx As (1)
(2)
General Transmission Line Equations
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Time-Harmonic Transmission Line Eqs.
• Assuming a traveling sinusoidal wave with angular frequency, ω
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xILjRdx
xdV
xVCjGdx
xdI
• Differentiating (3) and plugging in (4) (and vice versa)
xVdx
xVd 22
2
xIdx
xId 22
2
• where is the propagation constant -1m CjGLjRj
(5)
(6)
Time-Harmonic Transmission Line Equations
(3)
(4)
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Transmission Line Propagation Constant
• Solutions to the Time-Harmonic Line Equations:
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xrxfrf eVeVxVxVxV 00
• What does the propagation constant tell us?• Real part () determines attenuation/distance (Np/m)• Imaginary part () determines phase shift/distance (rad/m)• Signal phase velocity
xrxfrf eIeIxIxIxI 00
where -1m CjGLjRj
(m/s)
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Transmission Line Impedance, Z0• For an infinitely long line, the voltage/current ratio is Z0 • From time-harmonic transmission line eqs. (3) and (4)
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0 CjG
LjRxIxVZ
• Driving a line terminated by Z0 is the same as driving an infinitely long line
[Dally]
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Lossless LC Transmission Lines• If Rdx=Gdx=0
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LC
LCjj
0
CLZ
LC
0
1
No Loss!
• Waves propagate w/o distortion• Velocity and impedance
independent of frequency• Impedance is purely real
[Johnson]
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Low-Loss LRC Transmission Lines• If R/L and G/C
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Frequency-Dependent Loss Mechanisms
• The resistive (R) and dielectric (D) loss terms cause a signal propagating down a transmission-line to become attenuated with distance
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xDReV
xV 0
• Resistive loss term is due to conductor skin effect• Dielectric loss term is due to dielectric absorption• Both terms increase with frequency, although at
different rates
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Skin Effect (Resistive Loss)• High-frequency current density falls
off exponentially from conductor surface
• Skin depth, , is where current falls by e-1 relative to full conductor• Decreases proportional to
sqrt(frequency)• Relevant at critical frequency fs
where skin depth equals half conductor height (or radius)• Above fs resistance/loss increases
proportional to sqrt(frequency)
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d
eJ
21
f
2
2
h
fs
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sDC f
fRfR
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02
s
DCR f
fZ
R
For rectangular conductor:
[Dally]
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Skin Effect (Resistive Loss)
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[Dally]
MHzfmR sDC 43 ,7 5-mil Stripguide
kHzfmR sDC 67 ,08.0 30 AWG Pair
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02
s
DCR f
fZ
R
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Dielectric Absorption (Loss)• An alternating electric field
causes dielectric atoms to rotate and absorb signal energy in the form of heat
• Dielectric loss is expressed in terms of the loss tangent
• Loss increases directly proportional to frequency
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CG
D tan
LCf
CLfCGZ
D
DD
tan2
tan22
0
[Dally]
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Total Wire Loss
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[Dally]
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Advanced Board Dielectrics
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~1.6dB/in@ 56GHz
50GHz• Megtron 6 25dB loss is 12.5”• Tachyon 25dB loss is 15.6”• PTFE (Teflon) 25dB loss is 22.7”• Cabled interconnects can support ~1.5m
[Samtec]
~1.1dB/in@ 56GHz
~2dB/in @ 56GHz
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Cabled Backplane
• Cabled backplane with short daughter cards can support ~1m distances at 224Gb/s
[Ghiasi IEEE802.3 2017]
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Reflections & Telegrapher’s Eq.
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T
iT ZZ
VI
0
2
0
0
0
00
0
2
,
ZZZZ
ZVI
ZZV
ZVI
IIIZVI
T
Tir
T
iir
Tfri
f
0
0
ZZZZ
VV
IIk
T
T
i
r
f
rr
Termination Current:
• With a Thevenin-equivalent model of the line:
• KCL at Termination:Telegrapher’s Equation or Reflection Coefficient
[Dally]
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Termination Examples - Ideal
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RS = 50Z0 = 50, td = 1nsRT = 50
050505050
050505050
5.05050
501
rS
rT
i
k
k
VVV
in (step begins at 1ns)
source
termination
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Termination Examples - Open
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RS = 50Z0 = 50, td = 1nsRT ~ ∞ (1M)
050505050
15050
5.05050
501
rS
rT
i
k
k
VVV
in (step begins at 1ns)
source
termination
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Termination Examples - Short
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RS = 50Z0 = 50, td = 1nsRT = 0
050505050
1500500
5.05050
501
rS
rT
i
k
k
VVV
in (step begins at 1ns)
source
termination
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Arbitrary Termination Example
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RS = 400Z0 = 50, td = 1nsRT = 600
778.05040050400
846.05060050600
111.050400
501
rS
rT
i
k
k
VVV
in (step begins at 1ns)
sourcetermination
0.111V0.205V
0.278V0.340
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Lattice Diagram
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RS = 400
RT = 600Z0 = 50, td = 1ns
in (step begins at 1ns)
Rings up to 0.6V(DC voltage division)
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Termination Reflection Patterns
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RS = 25, RT = 25krS & krT < 0Voltages Converge
RS = 25, RT = 100krS < 0 & krT > 0Voltages Oscillate
RS = 100, RT = 25krS > 0 & krT < 0Voltages Oscillate
RS = 100, RT = 100krS > 0 & krT > 0Voltages Ring Up
source
termination
sourcetermination
source
termination
source
termination
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Termination Schemes
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• No Termination• Little to absorb line energy• Can generate oscillating
waveform• Line must be very short
relative to signal transition time• n = 4 - 6
• Limited off-chip use
• Source Termination• Source output takes 2 steps up• Used in moderate speed point-
to-point connections
LCnlnTt triproundr 2
LClt porch 2
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Termination Schemes
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• Receiver Termination• No reflection from receiver• Watch out for intermediate
impedance discontinuities• Little to absorb reflections at driver
• Double Termination• Best configuration for min
reflections• Reflections absorbed at both driver
and receiver• Get half the swing relative to
single termination• Most common termination scheme
for high performance serial links
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Differential Signaling
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• Differential signaling advantages• Self-referenced • Common-mode noise rejection• Increased signal swing• Reduced self-induced power-supply noise
• Requires 2x the number of signaling pins relative to single-ended signaling• But, smaller ratio of supply/signal (return) pins• Total pin overhead is typically 1.3-1.8x (vs 2x)
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Odd & Even Modes
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[Hall]
• Even mode• When equal voltages drive both lines, only one mode propagates called even more
• Odd mode• When equal in magnitude, but out of phase, voltages drive both lines, only one
mode propagates called odd mode• For a differential pair (odd mode), a virtual reference plane exists between
the conductors that provides a continuous return current path• Electric field is perpendicular to the virtual plane• Magnetic field is tangent to the virtual plane
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Balanced Transmission Lines• Even (common) mode
excitation• Effective C = CC • Effective L = L + M
• Odd (differential) mode excitation• Effective C = CC + 2Cd • Effective L = L – M
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21
21
2
dcodd
ceven
CCMLZ
CMLZ
[Dally]
2 ,2 evenCModdDIFF
ZZZZ
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PI-Termination
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1RZeven
2||2|| 221 RZRRZ evenodd
oddeven
evenodd
ZZZZR 22
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T-Termination
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12 2RRZeven
oddeven
odd
ZZR
RZ
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1
2
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Next Time• Channel modeling• Time domain reflectometer (TDR)• Network analysis
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