Modern Science & Art University

Faculty of Engineering

Department of Electrical Communication & Electronic Systems

Engineering

VLSI Design

ECE445

Lab Manual

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Table of Contents

Lab#1: Introduction to Xilinx and Modelsim .......................................... 3

Lab#2: Designing a 2x1 Multiplexer in VHDL ..................................... 10

Lab#3: Designing a 2x4 Decoder in VHDL .......................................... 11

Lab#4: Designing a structural Design connecting an ALU to an Encoder

in VHDL .................................................................................................. 12

Lab#5: Designing a 4-bit shift register with parallel load in VHDL ..... 13

Lab#6: Signed Mathematical Block ....................................................... 14

Lab#7: Frequency Divider block as part of a Hierarchal Design .......... 16

Lab#8: 1 Second Count 0-9 Asynchronous Counter on 7-Segment

Display ..................................................................................................... 17

Lab#9: 4*4 Matrix Keypad Interface via MM74C922 Keypad Encoder

................................................................................................................. 18

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Lab#1: Introduction to Xilinx and Modelsim

Creating a VHDL project in “Xilinx ISE tool”

Step 1: Open the IDE by double clicking on the icon shown:

Step 2: Select File => New Project

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Step 3: Name your project a descriptive name, save it into your directory (avoid C:) & click Next

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Step4: In the wizard shown below, make sure the Family, Device, & Simulator fields are as

shown below:

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The project will then open as seen below:

Creating a VHDL file and adding it to the project

Step 1: Select Project => New Source

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Select VHDL Module and choose a descriptive file name i.e. related to your design. The file

name must be the same as the entity of your design. Make sure that the Add to project box is

ticked.

Click Next then choose a suitable Architecture Name then Next then Finish.

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Proceed with your coding and then follow the below instructions to compile and simulate

your design.

Step1: Select you VHDL file from the top left box in the IDE as shown

Make sure that implementation in the View tab is chosen as seen above.

To compile and synthesize your design, double click on Synthesize – XST and wait to see this

sign.

To simulate choose Simulation from the View tab shown in the previous image, the following

will then appear.

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Select the VHDL file that you want to simulate, expand the Modelsim Simulator shown at the

end of the previous image and double click on Simulate Behavioral Model.

You will then be taken to your simulator that you chose in your project settings at the very

beginning, to start your simulation.

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Lab#2: Designing a 2x1 Multiplexer in VHDL

It is required to design a single bit input 2x1 Multiplexer in VHDL. Start with

coming up with the Boolean expressions from the blocks truth table, then create a

new VHDL project and implement your design. Upon, completion of the coding,

syntax check and synthesis, simulate your design.

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Lab#3: Designing a 2x4 Decoder in VHDL

It is required to design a 2x4 Decoder in VHDL. Start with coming up with the

Boolean expressions from the blocks truth table, then create a new VHDL project

and implement your design. Upon, completion of the coding, syntax check and

synthesis, simulate your design.

Repeat the design but this time using conditional statements.

DEC_IN1 DEC_IN2 DEC_O3 DEC_O2 DEC_O1 DEC_O0

0 0 0 0 0 1

0 1 0 0 1 0

1 0 0 1 0 0

1 1 1 0 0 0

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Lab#4: Designing a structural Design connecting an ALU to

an Encoder in VHDL

Code and simulate the structural design shown below. Create a new VHDL project

and implement your design. Make sure you code each block in a separate file, yet

in the same project.

S1 S0 ALU_O

0 0 ALU_IN1 + ALU_IN2

0 1 ALU_IN1 - ALU_IN2

1 0 ALU_IN1 AND ALU_IN2

1 1 ALU_IN1 OR ALU_IN2

Others XXXXX

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Lab#5: Designing a 4-bit shift register with parallel load in

VHDL

Design a 4-Bit asynchronous shift register with parallel load. The block diagram is

shown below. Upon completion of the coding, syntax check and synthesis,

simulate your design.

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Lab#6: Signed Mathematical Block

Design an asynchronous N-bit negative edge triggered signed ALU that performs

the operations listed in the table below. The ALU is to work at a frequency of 2Hz

knowing that the available clock source is 50 MHz . It is therefore required to design

a frequency divider block as part of the top level design shown below.

S (SEL) Operation

00 ALU_IN1 + ALU_IN2

01 ALU_IN1 - ALU_IN2

10 ALU_IN2 / 4

11 ALU_IN1 NOR ALU_IN2

OTHERS No Operation

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Use the below space for Lab#6 design

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Lab#7: Frequency Divider block as part of a Hierarchal

Design The SPARTAN3E development kit has an onboard 50 MHz Oscillator. The aim of

this exercise is to download the shift register block designed in Lab#5 onto the

development board. To reduce the speed of the clock that feeds the register, it is

required to design a frequency divider block that divides the oscillator frequency

by 50000000 to result in a 1Hz frequency. Below is the top level design block

diagram.

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Lab#8: 1 Second Count 0-9 Asynchronous Counter on 7-

Segment Display It is required to design an asynchronous 0-9 counter that displays the counts on a

single common cathode 7-segment display. The top level design is shown in the

figure below. Make use of the clock divider block designed in Lab#7.

Upon completion of the coding, syntax check and synthesis, simulate your design.

After verifying your design, write the “.ucf” file and generate the bit stream file.

Finally download the bit stream file to the development kit and monitor the output.

In preparation for Lab#9, go through the datasheet of the following component:

MM74C922 Keypad Encoder

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Lab#9: 4*4 Matrix Keypad Interface via MM74C922 Keypad

Encoder It is required to design a system that displays each keypad press onto a single

common cathode seven segment display. The top level design is shown in the

figure below. Make use of the 7-Segment decoder block designed in Lab#8 but

keep in mind that the file will need modifications.

Upon completion of the coding, syntax check and synthesis, simulate your design.

After verifying your design, write the “.ucf” file and generate the bit stream file.

Finally download the bit stream file to the development kit and monitor the output.

Symbols like # can be displayed as H & * can be displayed as -.

Suggest an improvement to the design that would make it more reliable and secure.