ECE331 Lecture 19S12Cxx Assembly Language

CSM12C128 Evaluation ModuleHC(S)12 Programmer’s (Register) Model

HC(S)12 Addressing Modes

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General block diagram for the 9S12Cxxx family

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Full processor functionality as shown in the block diagram is available with the (relatively expensive) 80-pin Quad Flat Pack (QFP) package.

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• Our CSMB12C128 development module (Designed by Axiom Manufacturing) has a 60-pin external interface.

• Unfortunately, it does not plug directly into a breadboard, so a breadboard adapter was made for us by John LaBaio at RHIT Ventures.

• Since only 60 pins are available, not all of the 9S12C128 I/O pins are available on our CSMB12C128 module.

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9S12C128 Pins available on CSMB12C128 CSMB12C128 module. This is module. This is the top view of the top view of the module the module pinout. pinout.

You will need to refer to this page many times as you interface I/O devices throughout this course!

CSMB12C128 Module Features

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A few of the I/O pins that are available:• PA7:0 and PB7:0 – Each of the eight Port A or eight Port B pins may be

configured as either a digital input or output. These two ports serve as multiplexed (time-shared) address and data pins when the microcontroller is operated in expanded mode.

• PAD7:0 (AN7:0) – Each of the eight “Port AD” pins may be configured as either analog input or as digital input/output.

• PT7:0 – Each of the eight “Port T” pins may be configured as timer input capture, timer output compare, or digital input/output.

• PM5:0 – “Port M” pins PM5:3 may be configured as digital input or output, in addition, Port M can be used for the following special functions:

• PM5:2 => Serial Peripheral Interface (SPI) bus• PM1:0 => CAN serial communication bus

Do NOT use PM0 or PM1 for general digital I/O, since these two pins are hardwired to the CAN interface chip on the CSMB12C128 module, and there are no on-board jumpers to break this connection.

• PS1:PS0 => These two “PORT S” pins are used as Serial (Asynchronous) Communication Interface (TX and RX)

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The Inside Story:

CSM12C128 ModuleCSM12C128 Module Circuit Diagram

(This diagram is in the class AFS PDF document folder))

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Connecting two I/O pins to a switch and an LED on the Project Board

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CSM12C128 J1 Connector

12

34

56

78

910

1112

13 15 17 19 21 23 25 27 2930

31322826242220181614

33 35 37 39

34 36 38 4041 43 45 47 49 51 53 55 57

42 44 46 48 50 52 54 56 5859

60

Vx

PE

1/IR

QG

ND

RE

SE

TP

S1/

TX

DM

OD

C/B

KG

DP

S0/

RX

DP

P7/

KW

P7/

PW

M7/

SC

K2

PP

0/K

WP

0P

AD

07/A

N07

PP

1/K

WP

1P

AD

06/A

N06

PT

0/P

W0/

IOC

0P

T1/

PW

0/IO

C1

PM

4/M

OS

IP

M2/

MIS

OP

M5/

SC

KP

M3/

SS

PA

7P

A6

PA

5P

P2/

KP

P2/

PW

M2

PA

4P

P3/

KP

P3/

PW

M3

PJ6

/KW

J6P

J7/K

WJ7

PA

D03

/AN

03O

AD

02/A

N02

PA

D01

/AN

01P

AD

00/A

N00

PA

D04

/AN

04P

AD

05/A

N05

PA

3P

A2

PA

1P

A0

PP

4/K

PP

4/P

WM

4P

P5/

KP

P5/

PW

M5

PS

2/R

XD

1P

S3/

TX

D1

PB

7P

B6

PB

5P

B4

PB

3P

B2

PB

1P

B0

PM

1/T

XC

AN

0

PE

0/X

IRQ

PE

2/R

WP

E3/

LST

RB

PE

4/E

CLK

PT

2/IO

C2

PT

3/IO

C3

PT

4/IO

C4

PT

5/IO

C5

PT

6/IO

C6

PM

0/R

XC

AN

0P

T7/

IOC

7

R 2

510 ohm s

Vcc = +5 V

Data LED

S W 1CSMB12C128board

R 3

10k

DataSwitch

R 1

10k

Wire NEATLY on left side of breadboard– Wires and component leads cut short, pressed down, do not cross over any part.

Leave NO chance for short circuits!

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9S12C128 Memory Map(Note: When the processor is RESET, the 9S12C128 microcontroller’s “RAM position

register” is initialized such that RAM is actually mapped to 0x0400 – 0x0FFF)

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Programmer’s Register Model of CPU12 Core

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Status Register Flag Bits

• Status Register (CCR) = S X H I N Z V C• S = “STOP Instruction Disable Flag”

– Out of RESET, this bit is set to 1.– Clearing this flag enables the STOP instruction.– When a STOP instruction executes (if S = 0), the

processor’s clock oscillator is shut down, and the processor enters a low-power consumption “Sleep Mode” until the processor is awakened by an interrupt or a RESET event.

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• X-bit - Nonmaskable Interrupt Mask Bit– Out of RESET, X = 1.– Clearing X enables interrupts on the XIRQ* interrupt

input line.– Once cleared, the X bit CANNOT be reset by software to

disable XIRQ interrupts. Thus the XIRQ input is said to be “non-maskable”.)

– The only way to set X = 1 is via RESET.• I-bit - Maskable Interrupt Mask Bit

– Out of RESET, I = 1.– Clearing I (via the CLI instruction) enables interrupts on

the IRQ* interrupt input line.– The I bit CAN be set back to 1 at any time by the software

via the SEI instruction. Thus the IRQ input is said to be maskable.

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Arithmetic Flags Z N C V H• Z …. Zero Flag

– Set if result = 0• N …. Negative Flag

– Indicates sign of result (1 => negative, 0 => pos)– Follows MSB of result

• C …. Carry Flag – Set if Carry occurs during addition operation– Set if Borrow occurs during subtract or compare operation

• V …. Overflow Flag– Set if two’s complement overflow occurs

• H …. Half Carry Flag– Set if carry out of Bit #3 occurs during add operation– Not affected by subtract or compare operations

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Signed (Two’s Complement) Overflow Detection

• For Addition–If addend and augend are of unlike signs

=> no overflow possible (V=0).

–If addend and augend are of like sign, and the sign bit of resulting sum disagrees =>overflow (V=1).

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• For Subtraction– If subtrahend and subtractor are of like sign

=> no overflow possible (V = 0).

– If subtrahend and subtractor are of unlike signs, and the sign bit of the resulting difference is NOT consistent with

(a) pos – neg should = pos; (b) neg – pos should = neg) => overflow (V = 1).

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Flag Setting ExamplesExample #1

• LDAA #$38 ADDA #$A9

=> $38 + $A9 = $E1 (A contains $E1) H = 1 (carry out of lower 4 bit nybble). C = 0 (no carry out of MSB of result) Z = 0 (result not 0) N = 1 (result negative) V = 0 (adding numbers of opposite sign => no overflow is possible.)

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Example #2

• LDAA #$9A ADDA #$A9

=> $9A + $A9 = $43 (A contains $43) H = 1 (carry out of lower 4 bit nybble. C = 1 (carry out of MSB of result) Z = 0 (result not 0) N = 0 (result positive) V = 1 (adding two negative numbers, and sum is positive => overflow)

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Example #3

• LDAA #$FC ADDA #$04 => $FC + $04 = $00 (A contains $00) H = 1 (carry out of lower 4 bit nybble. C = 1 (carry out of MSB of result) Z = 1 (result is 0) N = 0 (result positive) V = 0 (Adding numbers of unlike sign => no overflow is possible.)

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Example #4• LDAA #$FC SUBA #$04 => $FC - $04 = $F8 (A contains $F8) H = X (H is not affected by subtract or compare, X simply remains in the state it was in.) C = 0 (no borrow out of MSB was requested) Z = 0 (result is not 0) N = 1 (result negative) V = 0 (neg – pos = neg => no overflow).

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Example #5

• LDAA #$70 SUBA #$80 => $70 - $80 = $F0 (A contains $F0) H = X (H is not affected by subtract or compare, X simply remains in the state it was in.) C = 1 (Borrow out of MSB was requested) Z = 0 (result is not 0) N = 1 (result negative) V = 1 (pos – neg = neg => overflow).

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Example #6• LDAA #$80 CMPA #$70 => $80 - $70 = $10 (But A contains $80 because CMPA does NOT alter A!) H = ? (H is not affected by subtract or compare, H simply remains in the state it was in.) C = 0 (No borrow out of MSB was requested) Z = 0 (result is not 0) N = 0 (result positive) V = 1 (neg – pos = pos => overflow).

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Example #7• LDAA #$E2 CMPA #$E2 => $E2 - $E2 = 0 (BUT A contains $E2) H = ? (H is not affected by subtract or compare, H simply remains in the state it was in.) C = 0 (NO Borrow out of MSB was requested) Z = 1 (result is 0) N = 0 (result positive) V = 0 (overflow not possible when subtracting numbers of like sign)

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Addressing Modes – Tell the processor where to find data.1. Immediate Addressing

• Requires “#” prefix in front of the immediate operand • In this addressing mode the data itself is placed IMMEDIATELY after the instruction

OP CODE in program memory.• Ex: Mem Instr Immed.

Addr OpCd Operand Assy Code (hex) (hex) (hex) 4000 86 40 LDAA #64 ;without preceding “$” ;a value defaults to decimal

• 4002 86 64 LDAA #$64 4004 CE 00 64 LDX #$64 ;X is 16-bit reg, ;so 2 bytes data needed

LBL: EQU $1234 ;LBL equated to $1234 4007 CE 12 34 LDX #LBL

400A CE 12 2E LDX #LBL-2*3 ; Simple arithmetic ;expression allowed

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16-bit integer data storage• Each memory location in the HC(S)12 address space is one byte (8 bits)

wide; only 8-bits of data can be stored in a memory location. Memory is said to be “byte-addressable”.

• Whenever a 16-bit integer must be encoded on a Freescale microcontroller, as in “LDX #$1234”, it is stored in two adjacent memory locations, with the HIGH byte at the LOWER addressed memory location. This is called the “Big Endian” convention (the “big” end goes first!). Note: Intel microcontrollers use the “Little Endian” convention!

Hex Hex Addr Contents ORG $4000 LDX #$1234

4000 CE ;LDX Immediate addr mode OP CODE4001 12 ;High byte of 16-bit immed operand stored here4002 34 ;Low byte of 16-bit immed operand stored here

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2. Direct (Extended) Addressing Modes• One (two) bytes placed after the OP CODE to

indicate the “effective memory address” from or to which data are read or written.

• One byte is needed to indicate an address between $00 - $FF (Direct addressing)

• Two bytes needed to indicate an address between $0000 - $FFFF (Extended addressing)

• These modes are indicated by the absence of the “#” prefix.

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Direct and Extended addressing modes are used to access RAM memory locations as well as I/O PORT registers

• Simple Parallel I/O via 8-pin Port T (PT7:0)– DDRT ($242) Data Direction Register for Port T

• Writing a 1 to Bit #X in DDRT will make the corresponding I/O pin, PTX, an output. (Note: X is an integer between 0 and 7)

• Writing a 0 to Bit #X in DDRT will make the corresponding I/O pin, PTX, an input

• Ex: writing $F0 to DDRT makes PT7:4 outputs, PT3:0 inputs

– PTT ($240) Data I/O Register for Port T• Reading the PTT register will bring in data from the pins configured as

inputs• Writing the PTT register will send out data to the pins configured as

outputs, and this data will be held (latched) there until new data is written to the PTT register.

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PTAD (AN7:0) 8-bit Analog and Digital I/O Port

• DDRAD ($272) Data Direction Reg (like DDRT)• PTAD ($270) Data I/O Reg (like PTT)• ATDDIEN ($8D) Digital Input Enable Register

– This extra register is needed because PTAD pins can also be used as analog inputs to the A/D converter.

– If DDRADx = 0, then a “1” must be written into Bit #X of ATDDIEN to make the corresponding line Anx (or PTADx) a digital input line as opposed to an analog A/D input line.

– Thus, assuming that DDRAD = $00, writing $C0 into ATDDIEN will make AN7:6 digital input lines, and AN5:0 will be analog A/D inputs,

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Direct and Extended Addr Modes used to make AN6 output follow AN7 input

• Addr Mach. Code Assy LanguageATDDIEN: EQU $8D ;Digital Input Enable Reg for PTADPTAD: EQU $270 ;PTAD Data I/O Register

DDRAD: EQU $272 ;PTAD Data Direction Reg.ORG $4000

4000 86 80 LDAA #$80;The following line is Direct Addr Mode, since; the address of ATDDIEN is < $FF.

4002 5A 8D STAA ATDDIEN ; Make AN7 A Digital Input 4004 86 40 LDAA #$40

;Following 2 lines use Extended Addr Mode, since; the addresses of DDRAD and PTAD are > $FF.

4006 7A 02 72 STAA DDRAD ;Make AN7 an input, AN6 an Output 4009 B6 02 70 AGN: LDAA PTAD ;Read state of AN7 into Bit #7 of A 400C 44 LSRA ;Shift Bit #7 to Bit #6 of Accum A. 400D 7A 02 70 STAA PTAD ;Write state of AN7 out to AN6. 4010 06 40 09 JMP AGN ;Loop back and read again!

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Where did I get the Op Codes?• Answer: From the CPU12 manual

document: S12CPUV2.pdf (available for download from the class folder.)

• For example, study the CPU12 manual’s description of the LDAA, STAA, ASLA, and JMP instructions. Note that this description explains how each of the arithmetic flags are affected, what the op codes are for each addressing mode, how many bytes are present in the instruction, and the cycle-by-cycle bus activity (see Section 6.6 of CPU12 Manual).

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3. Inherent Addressing Mode

• Some instructions do not need to refer to an external memory location outside of the CPU12 core.

• The data they operate on is inherently known, and is in a CPU register that is INSIDE the processor core.

• Such instructions require only a 1 (or 2) byte op code.

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Examples of Inherent Mode Instructions

• CLI – Clear I-bit in Status Register (Enable IRQ interrupts)

• DEX – Decrement X register• INCA – Increment (add 1 to) Accumulator A.• RTS – Return from Subroutine • PSHA – Push Accumulator A on the Stack• ABA – Add B to A, putting result in A• LSRA – Logically shift right Accumulator A• MUL – 8-bit multiply (A x B -> A:B)

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4. (PC) Relative Addressing Mode• Used by branching (transfer of control) instructions• They indicate their target (transfer) address as an 8 or 16-bit

signed offset from the value of the program counter (PC) at the time the instruction is executed.

• Often, the target address of the branch is not far from the branch instruction (within +127 or -128 bytes of the op code that follows the branch instruction), so a single byte (8-bit) PC-relative offset can often be used, which is more economical than using extended addressing which would require two bytes to indicate the target address.

• However, “long branch” instructions featuring a 16-bit (2-byte) PC relative offset are also available for branching further than +127 or -128 bytes from the current value of the PC.

• Use of PC Relative addressing promotes Position Independent Code (PIC), where the same machine code can be loaded into memory at any starting position and will still run correctly.

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Conditional Branch Instructions

• Conditional Branch instructions of the form “Bxx” (whose target address is indicated by a signed 8-bit PC-relative offset) or “LBxx” (whose target address is indicated by a signed 16-bit PC-relative offset) examine the state of one or more flags to decide whether to “Branch or NOT Branch” to a target address.

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• The complete set of “Bxx” conditional branch instructions is summarized in the following table from the CPU12 manual.

• Just put an “L” prefix in front of these instructions to make them “Long Branch” (16-bit PC-relative offset) instructions.

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Example of Conditional Branching – LED Follows switch

Addr Machine Code Assembly Code ORG $4000

DDRT: EQU $242 PTT: EQU $240 4000 18 0B 40 02 42 MOVB #$40,DDRT ;SW on PT5 ;LED on PT6 4005 B6 02 40 LOOP_HR: LDAA PTT4008 84 20 ANDA #$20 ;If SW high, A = $20 ;If SW low, A = $00400A 27 07 BEQ SWDOWN400C 18 0B 40 02 40 SWUP: MOVB #$40,PTT ;Turn ON LED4011 20 F2 BRA LOOP_HR4013 79 02 40 SWDOWN: CLR PTT ;Turn OFF LED4016 20 ED BRA LOOP_HR

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Square Wave Generating Example

(Calls subroutineDELAY10MS to generate a square wave with

approximately 20 ms period on output pin PM1)

Assembled using Metrowerks IDE (with “Absolute Assembly” option requested)

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5 5 ORG $4000 ;This program waits until switch on PM2 6 6 0000 0250 PTM: EQU $250 ;is closed, then it generates 20 ms 7 7 0000 0252 DDRM: EQU $252 ;Square wave on PM1 output. 8 8 0000 0254 PERM: EQU $254 ;PTM pull-up enable reg 9 9 ;See Fig 3.19 of S12C32PIMV1.pdf 10 10 a004000 CF3F 00 Entry: LDS #$1000 ;Init Stk Ptr --- The first byte pushed will 11 11 ;be stored at $0FFF (highest RAM locn) 12 12 a004003 7902 54 CLR PERM ;Disable PTM input pullups 13 13 a004006 180B 0202 MOVB #2, DDRM ;Make PM1 output, PM2 input. 00400A 52 14 14 a00400B B602 50 WT_SW_LOW: LDAA PTM ;A SW is connected to PM2 15 15 a00400E 8404 ANDA #4 ;If SW on PM2 high,A=4; if SW low,A=0 16 16 a004010 26F9 BNE WT_SW_LOW ;Loop here until SW is pressed. 17 17 a004012 180B 0202 NEW_CYCLE: MOVB #2, PTM ;Make PM1 high 004016 50 18 18 a004017 1640 23 JSR DELAY10MS ;Call Subroutine DELAY10MS to wait 10 ms

;JSR pushes PC (which currently holds;addr of next instr) onto stack, then

loads;PC with entry addr of subr

DELAY10MS. 19 19 a00401A 7902 50 CLR PTM ;Make PM1 Low 20 20 a00401D 1640 23 JSR DELAY10MS ;Wait 10 ms 21 21 a004020 0640 12 JMP NEW_CYCLE ;Repeat this forever. 22 22 a004023 34 DELAY10MS: PSHX ;Save X on stack 23 23 a004024 CEFF FF LDX #$FFFF 24 24 a004027 09 WAIT_HR: DEX ;Wait by counting X down 25 25 a004028 26FD BNE WAIT_HR ;from $FFFF to 0. 26 26 a00402A 30 PULX ;Restore X from stack 27 27 a00402B 3D RTS ;Return from Subroutine

;Pop two bytes off stack and put in PC

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Role of Stack Pointer Register “SP”

• SP “points to” (holds the address of) the last item pushed on the stack.

• Stack grows “down” (toward address 0).• If SP is initialized to address $1000 (via LDS #$1000),

and then a byte is pushed on the stack (PSHA), SP will first be decremented by 1, and THEN the byte in A will be written to the address in SP = $0FFF. No data is written to $1000.

• If a byte is pulled from the stack (PULA), first the address in SP will be used to read the data; THEN the SP is incremented.

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• SP must always point to memory locations where RAM is available.

• If a 16-bit address is pushed on the stack (JSR) or a 16-bit register is pushed on the stack (PSHX), the high byte is always stored at the lower address and the low byte at the higher address (Big Endian format is observed even while stacking data).

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Stack Map – After LDS #$1000 Address Contents SP -> 1000

0FFF 0FFE 0FFD

0FFC 0FFB 0FFA

Note: SP initialized at $1000, one location above the end of RAM. SP always points to the “last item pushed on stack” (except for when the stack is empty), and the stack grows down toward address $0000.

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Stack Map After JSR at $4017

Address Contents 1000

0FFF 1A ;PC low byte (Return Addr) SP -> 0FFE 40 ;PC high byte (Return Addr) 0FFD

0FFC 0FFB 0FFA

Note: JSR pushes current value of the PC, which points to the OP CODE of the instruction that is just after the JSR. Then JSR loads the entry point of the subroutine (found in the two bytes following the JSR op code) into the PC, so execution jumps to the beginning of the subroutine.

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After PSHX in DELAY10MS Subrtn

Address Contents 1000

0FFF 1A ;PC low byte (Return Addr) 0FFE 40 ;PC high byte (Return Addr) 0FFD XL ;Low Byte in X

SP -> 0FFC XH ;High Byte in X 0FFB 0FFA

Note: X register has been saved on stack.

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Stack Map After PULX in Subroutine

Address Contents

1000 0FFF 1A ;PC low byte (Return Addr) SP -> 0FFE 40 ;PC high byte (Return Addr) 0FFD

0FFC 0FFB 0FFA

Note: X reg has been restored from stack

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After RTS

Address Contents SP -> 1000

0FFF 0FFE 0FFD

0FFC 0FFB 0FFA

Note: RTS instruction pulls $401A off the stack into the PC, so execution returns from subroutine and the instruction just beyond the JSR (CLR PTM) runs next. Also, the SP is now back where it started! Stack empty.

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Just after second JSR (at $401D)

Address Contents 1000

0FFF 20 ;Low byte of PC (Return addr) SP -> 0FFE 40 ;High Byte of PC (Return addr) 0FFD 0FFC 0FFB 0FFA

Current PC value (address of instruction just after JSR) is pushed onto stack as the “return address”

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After PSHX in DELAY10MS Subrtn

Address Contents 1000

0FFF 20 ;Low byte of PC (Return addr) 0FFE 40 ;High Byte of PC (Return addr) 0FFD XL ;Low Byte of X SP-> 0FFC XH ;High Byte of X 0FFB 0FFA

Note: X is saved on stack since the body of the subroutine will make use of X.

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After PULX in DELAY10MS subroutine

Address Contents 1000

0FFF 20 ;Low byte of PC (Return addr) SP -> 0FFE 40 ;High Byte of PC (Return addr) 0FFD 0FFC 0FFB 0FFA

NOTE: X register has been restored from stack.

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After RTS

Address Contents SP -> 1000

0FFF 0FFE 0FFD 0FFC 0FFB 0FFA

NOTE: RTS unstacks $4020 into PC, the addr of next instruction beyond JSR (JMP New_Cycle). Execution returns from subroutine to this instr. Stack now Empty.

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Metrowerks True-Time Simulator Demonstration

• Select “Simulator” instead of “Monitor” before the green “Debug” arrow button is pressed.

• Hit RESET button to start program at entry point initialized into the Reset Vector, at ($FFFE,$FFFF)

• Right click in the “Memory” window and select “Address”. Set address to 1000, to display stack area in memory (grows DOWNWARD from 0F00)

• Single Step by clicking on “Single Step” button (or hitting <F11>)

• Watch CPU registers change as you single step.• Watch SP register change, and also watch data get

pushed onto, then pulled from, the stack, as you step into and out of DELAY10MS subroutine.

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• You will NOT want to single step through the entire subroutine, since it has a LARGE wait loop, so set break point near end of subroutine, say at the PULX. Do this by right clicking on PULX and selecting “Set Breakpoint”. A red arrow appears to the left of this instruction.

• Now hit the Green “Start/Continue” arrow button in order to run the simulator at speed until it comes out of the wait loop and hits the breakpoint.

• From this point, you may continue single-stepping (pressing the Single Step button), and watching the SP register change as you do so.

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Monitoring an Output Port with the “IOLED” Simulator Object

• Click on “Component – Open – IOLED”• Right Click to select “Setup”. Set PORT to 250 and

DDR to 252 (hex addresses for PORT M).• Remove breakpoint from PULX by right clicking on

the PULX and selecting “Remove Breakpoint”• Set breakpoint at each of the JSR DELAY10MS

instructions in calling program. • Hit Reset button and then hit Start/Continue button.

The first breakpoint will be reached and LED corresponding to PM1 will be lit (Red). Hit Start/Continue again and PM1 LED will go off (Green). This process repeats forever.

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Debouncing Switches

• Whenever ANY mechanical switch is operated (either closed or opened), its contacts will bounce (chatter) close – open – close – open - close, etc. for several milliseconds before the switch contacts finally remain stable in their closed or opened state.

• Sometimes this is a problem, other times it is not.

04/18/23 ECE331 Lecture 1 (KEH) 70

Hardware Debouncing SPDT Switch

Q = 1S\

R\

+5 V

+5 V

10 kΩ

10 kΩ

SPDT Push Button Switch

Note: Cross-Coupled NAND gates form an SR latch with active-low inputs

NO

NC

Wiper

(SPDT => Single Pole, Double Throw)

As button is pressed, and wiper moves to “NO” position, the first bounce clears SR latch output (Q -> 0), then successive bounces at “NO” make no further change in Q! Later when button is released, first bounce on “NC” sets Q -> 1; further bounces on “NC” make no further change in Q.

NC => Normally closed contact

NO => Normally open contact

04/18/23 ECE331 Lecture 1 (KEH) 71

Hardware Debouncing SPST Switch+5 V

10 kΩ

10 μFSPST

Pushbutton

Switch

74HC14 Schmitt Inverter with Vt+=3V, Vt-=2V VoutVin

When SW pressed, first contact closure shorts capacitor, making Vin = 0, and thus Vout goes high. Then as SW bounces off contact for a ms or so, Vin begins to charge toward 5 V with a time constant of Tau = 10 kΩ*10 μF = 0.1 second, thus Vin does not rise above Vt+ before the next contact bounce, and thus Vout remains high!

04/18/23 ECE331 Lecture 1 (KEH) 72

Software Debouncing SPST Switch

Vout

(To 9S12C128

Input Pin)

“Bouncy” SPST Switch Configuration

When SW pressed, Vout will go low, but then it will “chatter” for a few ms (high-low-high-low, etc.)

+5V

10kΩ

When SW released, Vout will go high, but then it will “chatter”For a few ms (low-high-low-high, etc.)

SW

In some software applications, this chatter may not be important, but if the program is to increment a counter, or to respond in some other way when Vin rises – there is a problem!

04/18/23 ECE331 Lecture 1 (KEH) 73

Example where software debouncing is needed: Reliably toggling (changing state of) LED

Make PM2 input, PM1 output(SW on PM2, LED on PM1)

PM1 = 0

PM2=0?

PM2=1?

PM1 = ~PM1

Wait until SW is pressed

Wait until SW is released

Toggle LED

Turn LED off

04/18/23 ECE331 Lecture 1 (KEH) 74

Why does LED fail to toggle reliably?

• Answer: Contact bounce!• Contact bouncer occurs on “make” or “break”

of the switch contacts.• The “software” solution?• Call a wait routine (that waits longer than the

maximum contact bounce time) just after contacts found to be closed, and also just after contacts found to be released!

04/18/23 ECE331 Lecture 1 (KEH) 75

Make PM2 input, PM1 output(SW on PM2, LED on PM1)

PM1 = 0

PM2=0?

PM2=1?

PM1 = ~PM1

Wait until SW is pressed

Wait until SW is released

Toggle LED

Turn LED off

Wait 50 ms

Wait 50 ms

Wait for contact bouncing to die out

Wait for contact bouncing to die out.

NoYes

No

Yes

04/18/23 ECE331 Lecture 1 (KEH) 76

PTM: EQU $250 ;Toggles LED reliably DDRM: EQU $252 ;Each time SW is RELEASED! PERM: EQU $254 Entry: LDS #$3F00 ;Init Stk Ptr CLR PERM ;Disable PTM input pullups MOVB #2,DDRM ;Make PM1 output, PM2 input. CLR PTM ;Turn OFF LED, which is connected to PM1.WT_SW_LOW: LDAA PTM ;A SW is connected to PM2 ANDA #4 ;If SW on PM2 high,A=4; if SW low,A=0 BNE WT_SW_LOW ;Loop here until SW is pressed (SW goes low) JSR DELAY10MS ;Wait for contact bouncing to die out.WT_SW_HIGH: LDAA PTM ANDA #4 BEQ WT_SW_HIGH ;Loop here until SW is released JSR DELAY10MS ;Wait for contact bouncing to die out. LDAA PTM ;State of LED on Bit 1 EORA #2 ;Invert state of LED (Toggle LED) STAA PTM BRA WT_SW_LOW;************ End of main program*********************DELAY10MS: PSHX ;Save X on stack LDX #$FFFFWAIT_HR: DEX ;Wait by counting X down BNE WAIT_HR ;$FFFF to 0. PULX ;Restore X from stack RTS ;Return from Subroutine

04/18/23 ECE331 Lecture 1 (KEH) 77

Indexed Addressing Modes• So far we have discussed the following addressing

modes:– Immediate (LDAA #$12, LDX #$1234)– Direct (LDAA $12, STAA $12)– Extended (LDAA $1234, STAA $1234)– Inherent (INCA, RTS)– PC Relative (BEQ NearTarg, LBEQ FarTarg)

• Only the indexed addressing modes remain to be covered! (But there are EIGHT of them!)

• The indexed addressing modes use either the X, Y, SP, or PC 16-bit CPU registers as “index registers” along with additional information to form the effective address of the data.

04/18/23 ECE331 Lecture 1 (KEH) 78

• Indexed addressing modes consist of an op code followed by one postbyte plus 0, 1, or 2 extension bytes.

• Postbyte and extension byte(s) indicate:– Which index register is to be used (X, Y, SP, or PC)– Whether a value in an accumulator is used as an

offset– Specify size of increment or decrement– Specify use of 5-, 9-, or 16-bit offsets.

• Postbyte encoding found in Table 3.2 of CPU12 manual, as shown on next page

04/18/23 ECE331 Lecture 1 (KEH) 79

04/18/23 ECE331 Lecture 1 (KEH) 80

1. 5-Bit Constant Offset Indexed Addressing

• 5-bit signed constant offset (-16, +15) is contained in the postbyte itself.

• No extension bytes => 2-byte instruction• Effective Address of data=(Index Reg) + offset• Value in the index register is not affected.• Examples (Assuming X = $4020):

A6 00 LDAA 0,X ;($4020) -> A ;”($4020 )” means contents of $4020

6A 0C STAA 12,X ;A -> $402C; 69 10 CLR -16,X ;0 -> $4010 6C 05 STD 5,X ;A -> $4025 and B -> $4026

04/18/23 ECE331 Lecture 1 (KEH) 81

04/18/23 ECE331 Lecture 1 (KEH) 82

2. 9-bit constant offset index addressing

• Uses a 9-bit signed constant offset (-256, 255) that is added to the index register to form the effective address of the data.

• MSB of 9-bit constant offset in LSB of postbyte.• Rest of 9-bit constant offset is in ONE extension byte

=> 3-byte instruction.• Example (assume X = $4020):

– A6 E0 80 LDAA $80,X ;($40A0) -> A– 6C E1 E0 STD -$20,X ;A -> $4000 and B -> $4001

04/18/23 ECE331 Lecture 1 (KEH) 83

04/18/23 ECE331 Lecture 1 (KEH) 84

3. 16-bit constant offset indexing

• Indexed addressing mode uses a 16-bit constant offset (-32768,32767) that is added to the index register to form the effective address of the data.

• Offset is placed in TWO extension bytes after the postbyte => 4-byte instruction.

• Examples (assume X = $4020)E6 E2 10 00 LDAB $1000,X ;($5020) -> B

• 05 E2 50 00 JMP $5000,X ;Jump to addr $9020

04/18/23 ECE331 Lecture 1 (KEH) 85

04/18/23 ECE331 Lecture 1 (KEH) 86

Assembly Directive Examples• EQU – “Equate” used to define equivalence between a label and a value

– MySymbol: EQU $1234• DC.B – “Define Constant Byte” (or its equivalent FCB – “Form Constant

Byte”) allocates a constant byte, or a list of bytes, or a string of ASCII codes (into Flash ROM --- Not into RAM!)– MyByte1: DC.B $12 – MyByteTable: DC.B $12, 34, ‘Text’, $0A, $0D

• DC.W – “Define Constant Word” (or its equivalent FDB – “Form Double Byte”) allocates a word (pair of bytes), or a list of words into Flash ROM (NOT into RAM)– MyWord1: DC.W $1234– MyWordTable: DC.W $1234, 10, 3000, $3BAD

• DS.B N – “Define N-byte Space” (or its equivalent RMB N – “Reserve N Memory Bytes”) allocates N bytes of RAM.– My_RAM_Var1: DS.B 1 ;allocate one byte of RAM storage– My_RAM_Array: DS.B 10; alllocate 10 bytes of RAM storage

04/18/23 ECE331 Lecture 1 (KEH) 87

Application of Constant Offset Indexing

;*** Example program that adds 10 bytes in the constant array "DatList" ORG RAMStart; Use DS.B (or RMB) to allocate one word-sized (2-byte) data variable in RAM.result_wd ds.b 2 ;DS.B n "Define Space (n bytes)" allocates n bytes of RAM ;result_wd rmb 2 ;Note RMB n "Reserve Memory (n Bytes) is equivalent! ORG ROMStart;Use DC.B (or FCB) to allocate a 10-byte data constant table in ROMDatList: DC.B $12, $EF, $01, $F0, $85 ;DC.B => "Define Constant (byte-size)" FCB $01, $15, $78, $50, $00 ;FCB => "Form Constant Byte", ;FCB is equivalent to DC.B!Entry: ldx #DatList ;Index Reg X points to first byte in list ldd #0 ;Reg D = A:B will accumulate 16-bit result . Init D=0. nxt_nr: addb 0,x ;Add next byte in list to low byte of Reg D (B) bcc no_inc_a ;Decide whether to increment high byte of Reg D (A) inca no_inc_a: inx ;Make X point to the next element in the list cpx #DatList+10 ;Check to see if all 10 elements have been added. bne nxt_nr std result_wd ;Store final 16-bit result in RAM variable “result_wd”.dyn_hlt: bra dyn_hlt

04/18/23 ECE331 Lecture 1 (KEH) 88

4. 16-bit constant indirect addressing• Adds 16-bit instruction-supplied offset to index register (X,

Y, SP, or PC) to form the address of a memory location that contains the high byte of the effective address. The next sequential memory location contains the low byte of the effective address.

• 16-bit offset requires two extension bytes => 4-byte instruction.

• Example: Assume X = $4020, ($4022)=$12, ($4023) = $34, ($1234) = $45– A6 E3 00 02 LDAA [2,X] ; $45 -> A– 6A E3 00 02 STAA [2,X] ; A -> $1234– 05 E3 00 02 JMP [2,X] ;Jump to $1234– 05 02 JMP 2,X ;Jump to $4022

• Note “[IA]” => Effective address found at IA:IA+1, where IA = offset + Index Register contents.

04/18/23 ECE331 Lecture 1 (KEH) 89

04/18/23 ECE331 Lecture 1 (KEH) 90

Application of 16-bit indirect index addressing (“Menu Picking”)

org $4000 ;Desired program numberJump_table: fdb prog0 ;is entered into two

fdb prog1 ;switches on PM1:PM0. fdb prog2 ;This is a table of program fdb prog3 ;starting addresses.Entry: …………….

LDAB PTM ;read in program # to jump to ANDB #$03 ;on switches on PM1:PM0.

LSLB ;Multiply program nr by 2 by shifting B left TFR B,X ;Sign Extend(B) -> X JMP [Jump_table,X] ;Jump to desired programprog0: ……prog1: …..prog2: …..prog3: …..

04/18/23 ECE331 Lecture 1 (KEH) 91

5. Auto pre-incremented and pre-decremented indexed addressing

• These modes automatically increment or decrement the index register by a specified constant (1,8) or (-1,-8) just BEFORE the data is accessed. Note the index register contents are MODIFIED by this addressing mode.

• This constant is encoded inside 4 -bits of the postbyte, so the total instruction length is only 2 bytes.

• The index register can be specified as X, Y, or SP, but NOT the PC, as it makes no sense to automatically modify the PC!

• These instructions are used for sequentially accessing data elements in an array, where each element is of equal length (1 to 8 bytes long).

04/18/23 ECE331 Lecture 1 (KEH) 92

Examples of pre-incremented and pre-decremented indexed addressing Org $4000

Datlist: DC.W $1234, $2345, $34, $45, $5678400A CE 40 00 Entry: LDX #Datlist ;X = $4000400D EC 21 LDD 2,+X ;$2345 -> D,X=$4002400F EC 21 LDD 2,+X ;$0034 -> D, X=$40044011 EC 2E LDD 2,-X ;$2345 -> D, X=$40024013 EC 2E LDD 2,-X ;$1234 -> D, X=$4000

. . . . . . .

04/18/23 ECE331 Lecture 1 (KEH) 93

04/18/23 ECE331 Lecture 1 (KEH) 94

6. Auto post-incremented and post-decremented indexed addressing

• These modes automatically increment or decrement the index register by a specified constant (1,8) or (-1,-8) just AFTER the data is accessed. Note the index register contents are MODIFIED by this addressing mode.

• This constant is encoded inside 4 -bits of the postbyte, so the total instruction length is only 2 bytes.

• The index register can be specified as X, Y, or SP, but NOT the PC, as it makes no sense to automatically modify the PC!

• These instructions are used for sequentially accessing data elements in an array, where each element is of equal length (1 to 8 bytes long).

04/18/23 ECE331 Lecture 1 (KEH) 95

Examples of post-incremented and post-decremented indexed addressing

Org $4000Datlist: DC.W $1234, $2345, $34, $45, $5678

400A CE 40 00 Entry: LDX #Datlist ;X = $4000400D EC 31 LDD 2,X+ ;$1234 -> D, X=$4002400F EC 31 LDD 2,X+ ;$2345 -> D, X=$40044011 EC 3E LDD 2,X- ;$0034 -> D, X=$40024013 EC 3E LDD 2,X- ;$2345 -> D, X=$4000

. . . . . . .

04/18/23 ECE331 Lecture 1 (KEH) 96

04/18/23 ECE331 Lecture 1 (KEH) 97

Ex #1: Stack Manipulation with Auto-Indexed Addressing Modes

LDS #$0F00 ;Start of system stack areaSTAA 1,-SP ;Same as PSHA, A->$0EFF, S=$0EFF STX 2,-SP ;Same as PSHX, XH->$0EFD, XL->$0EFE, S=$0EFDLDX 2,SP+ ;Same as PULX, ($0EFD)->XH,($0EFE)->XL, S=$0EFFLDAA 1,SP+ ;Same as PULA, ($0EFF)->A, S = $0F00

;Or user may set up separate program stack area and use ;X or Y as the stack pointer!

LDY #$0E00 ;Start of user program stack areaSTAA 1,-Y ;Push A onto user stack: A->$0DFF, Y=$0DFF STX 2,-Y ;Push X: XH->$0DFD, XL->$0DFE, Y=$0DFDLDX 2,Y+ ;Pull X: ($0DFD)->XH,($0DFE)->XL, Y=$0DFFLDAA 1,Y+ ;Pull A: ($0DFF)->A, Y = $0E00

04/18/23 ECE331 Lecture 1 (KEH) 98

Ex #2: Memory-to-Memory Array Moving

;Move a 10-word table from ROM into RAM ORG RAMStart

DatListRAM: DS.W 10 ;Here is 10-word RAM destination area ORG ROMStartDatListROM: DC.W $1234, $EF, $0178, $0BAD, $FEED DC.W $01, $1567, $78, $50, $1023

Entry: LDX #DatListROM LDY #DatListRAM LDAA #10 ;Let Acc A be loop counterNxtWd: MOVW 2,X+, 2,Y+ ;Move next word element DECA BNE NxtWd ;Loop if all 10 words not moveddynhalt: BRA dynhalt

04/18/23 ECE331 Lecture 1 (KEH) 99

7. Accumulator Offset Indexed Addressing

• In this mode the effective address is the sum of the values in the index register and an 8-bit or 16-bit unsigned offset in one of the accumulators (A,B, or D)

• Since the identity of the accumulator used is encoded in the postbyte, this instruction is only 2 bytes in length.

• They permit a variable offset into an array to be modified in a loop, while the index register points to the start of the array.

• Examples: A6 E5 LDAA B,X 6D E6 STY D,X 18 0A E4 ED MOVB B,X, A,Y

04/18/23 ECE331 Lecture 1 (KEH) 100

Code Lookup Table Example;This program translates the input byte read from Port T into a new coded byte and puts ;the coded value in CodedValue result location. $00 put in result location if code is not in table.;Examples: Port T SW = $9A => DecodedValue = $0B; Port T SW = $55 => DecodedValue = $00

ORG $0400 ;RAMSTART = $0400CodedValue: DS.B 1 ;Coded Value put here, $00 if no code found

ORG $4000 ;ROMSTART = $4000CodeTable: DC.B $12,$34,$56,$78,$9A,$BC,$DECodeValue: DC.B $03,$05,$07,$09,$0B,$10,$13Entry: LDX #CodeTable

LDY #CodeValueCLR DDRT ;8 switches on Port TLDAA PTT ;Load in code word from switchesLDAB #7 ;Seven elements in table

CheckNxtEntry: DECBBLO NoMatchFound

CMPA B,XBEQ MatchFoundBRA CheckNxtEntry

MatchFound: LDAA B,YSTAA CodedValue ;Put decoded value in result location

(CodedVaue)BRA Done

NoMatchFound: CLR CodedValue ;Put $00 in result location (CodedValue)Done: BRA Done

04/18/23 ECE331 Lecture 1 (KEH) 101

04/18/23 ECE331 Lecture 1 (KEH) 102

8. Accumulator D Indirect Addressing• This indirect indexed mode adds the value in D to the

value in the index register to form the address of a memory location M.

• The byte found at address M and the byte found at address M+1 form the address of the data.

• The identity of the register is placed in the postbyte, so the overall instruction length is 2 bytes.

• Example: If D = $10, X = $5000, ($5010) = $40, ($5011) = $50, and ($4050) = $12A6 E7 LDAA [D,X] ;A is loaded with $12

04/18/23 ECE331 Lecture 1 (KEH) 103

04/18/23 ECE331 Lecture 1 (KEH) 104

Computed GOTO exampleAssume D holds one of the values $0000, $0002, or $0004 (determined by the program at some time before the code below is executed.)JMP [D,PC] ;(Go to PROG1 if D=0, PROG2 if D=2, PROG3 if D=4)

GOTOPROG1 DC.W PROG1 ;Starting Address of Program 1

GOTOPROG2 DC.W PROG2 ;Starting Address of Program 2

GOTOPROG3 DC.W PROG3 ;Starting Address of Program 3

…………..

PROG1 NOP ;This is where Program 1 begins

………....

PROG2 NOP ;This is where Program 2 begins

............

PROG3 NOP ;This is where Program 3 begins

…………