ece1769: introduction to cad and synthesisjzhu/courses/behsyn/notes/intro_handout.pdf · design...

ECE1769: Introduction to CAD and Synthesis

Jianwen Zhu

Electrical and Computer Engineering

University of Toronto

[email protected]

http://www.eecg.toronto.edu/˜jzhu

ECE1769 Copyright c© Jianwen Zhu, 2002, ECE, Univ. of Toronto 1

Outline

Introduction to CAD

Introduction to behavioral and logic synthesis

Course logistics

Summary


Chip Market in Y2K

Chip sales reach $205 billion

Chip sales grow 38.9% over 1999

• Greatest growth with communication and internet infrastructure

• Japanese market: 38.9%

• Asia/Pacific market: 20.9%

• America market: 30%

• European market:24.1%

Data source: Semiconductor Industry Association


Why Computer Aided Design?

Moore’s law: the quest for integration and performance

chip complexity grows exponentially every year

Imagine the labor of handcrafting 1-billion transistor chip

CAD is enabling technology: defining the design methodology

Design management

Design specification

Design synthesis

Design verification


Y-chart (Gajski, 1983)

Behavioral Domain

Structural Domain

Geometric Domain

System level

Architecture level

Logic level

Circuit level

Cocurrent program

Sequential program

FSM andBool. function

Differential equation transitors

gates

cotroller/datapath

CPUs, cores

leaf cell

standard cell arrays

macros

floorplan andassembly


Y-chart Abstraction Levels

System level

tasks implemented by processing elements

Architecture level (micro-architecture to be exact)

operations implemented by resources

Logic level:

boolean functions implemented by gates

Circuit level

analog functions implemented by transistors


Y-chart Modeling Views: Behavioral Domain

Abstract function

System level characterized by:Plethora of computational models for concurrency

Dataflow, Petri-Net, Hoare’s CSP, Harel’s Statechart, ...

Architecture level characterized by: Algorithm

Logic level characterized by:Finite state machine

Discrete and Boolean function

Circuit level characterized by:Differential equationsImpulse response for linear time-invariant systems

Convex functions


Y-chart Modeling Views: Structural Domain

Interconnection of parts

System level characterized by: parallel architecture

CPUs

ASIPs and ASICs

Architecture level characterized by: micro architecture

controller

datapath

Logic level characterized by: network of gates

Circuit level characterized by: network of transistors


Y-chart Modeling Views: Geometric Domain

Physical objects with size and position

System level characterized by: floorplan

Architecture level characterized by: floorplan

Logic level characterized by: placed and routed layout

Circuit level characterized by: cell layout


Y-chart Example: Architecture Level

else

end if;

:= MEM(PC);:= PC + 1;:= SP − 1;:= DBUF;

DBUFMEM(SP)SPPC

if IR(3) = ’0’ thenPC := PC + 1;

Address bus

Data bus

SP

mux1

PC

mux2

+ / −

DBUF

MEMControl

Unit

1

DBUF

MEM

Data bus

Addressbus

mux1

PC

SP

mux2

ADD/SUB

Behavior Structural

Geometric


Design Tools: Specification

Design Modeling at different level of abstraction

System level specification

Matlab, block diagrams, C++, SystemC/SpecC?

Architecture level specification

HDLs, C

Logic level specification

HDLs, schematic, EDIF

Physical level specification

CIF, GDSII, LEF/DEF etc.


Design Tools: Synthesis

Bridging the gap between different views of an abstraction

Behavior view 7→ structural view

System level synthesis

System model 7→ parallel architecture

Architecture synthesis (Behavioral,

high-level) Algorithm 7→

micro-architecture

Logic synthesis

FSM 7→ gate network

Structural view 7→ geometric view

Cell synthesis:

transistor network 7→ layout

Module generation:

SRAM/ROM/PLA/Datapath

netlist 7→ regular layout

Placement and routing: randow

logic/chip assemblylogic network 7→ layout


Design Tools: Verification

Functional verification: is what Ispecify what I want?

Simulation: system level, gate

level, switch level, circuit level

Model checking

Implementation verification: iswhat I implement what I specify?

BDD-based equivalence checking

Logic-vs-layout checking (LVS)

Design rule checking (DRC)

Electrical rule checking (ERC)

Performance verification: is what Iimplement good enough?

Static timing analysis

Power analysis

Signal integrity

Power/ground integrity

Manufacture verification: is what imanufacture fault-free?

ATPG-based

BIST-based


Trend in Computer Aided Design

1980s: Capture-and-Simulate paradigm

1990s: Describe-and-Synthesis paradigm

Trend in the new millennium: the System-on-chip dilemma

Complexity challenge: 7→ higher levels of abstraction

Hardware/software codesign

Digital/analog codesign

Deep submicron challenge: 7→ lower levels of abstraction

interconnect becomes dominant, yet interconnect is evasive at high level

Noise emerges as a new performance metric: crosstalk, IR drop, parasitic

inductance...

IP-based Paradigm? Platform-based Paradigm?


Outline

Introduction to CAD


Course logistics

Summary


Synthesis Focus

This course focuses on

the synthesis aspect of CAD

at architecture and logic level

Covered in other courses

ECE 1387 (Prof. Rose): More on physical synthesis

ECE 1767 (Prof. Veneris): Design for Test and Testability

ECE 1768 (Porf. Najm) Reliability of Integrated Circuits


A Generic Synthesis System

Frontend

Architecture-independent optimization

Behavioral synthesis

Logic synthesis

Technology-independent optimization

Technology mapping

Quality metric analyzer

Exporter

QMAnalyzer

RTLLib.

Gate Lib.

Spec

Frontend

IR

Netlist

Optimization

TimingConstr. Backend

LogicSynthesis

BehavioralSynthesis

MicroArch

Netlist Sign−off

RTL Sign−off


Frontend

Goal: convert a Behavioral specification suitable for human

manipulation into a form suitable for machine manipulation

Parser: Abstract syntax tree

Semantic analyzer: type checking and inference

Control/dataflow analyzer: intermediate form


Architecture-independent optimization

Goal: performs function-preserving transformation of the

intermediate form to improve performance

Examples:

Constant propagation

Dead code elimination

Common subexpression elimination

Partial redundancy elimination

Strength reduction

Tree-height reduction

The list goes on and on ...

Subject of optimizing compiler course, refer to the Muchnick’s book


Behavioral and Logic Synthesis

Goal: maps functional view to structural view

Methodology

Divide synthesis problem into a set of smaller subproblems, called phases

Formulate each phase as a constraint optimization problem that reads:Given .... (certain subject);

Come up with .... (certain result) Such that some ... (certain figure of merits) isminimized (maximized)

Subject to ... (certain constraint)

Combining the result of all phases, while try to minimize phase coupling


Synthesis at the Temporal Domain

A program has to be implemented in many clock cycles due to:

Data dependency

Resource limitation

Goal: map each operation to a control step

Such that data dependency is honored, AND:

Time constrained formulation:

the amount of resource (area) used is minimized

Resource constrained formulation:

the expected cycle (speed) count is minimized


Synthesis at the Spatial Domain

Resource can be shared to save area

Register allocation: map each value to a register

Register/memory bank allocation: map each register to a bank

Functional unit binding: map each operator to a resource

Interconnect binding: map each data transfer to a bus


The RTL sign-off

Controller: an FSM is extracted

random-logic based

micro-program based

stack-assisted state machine

Datapath: a network of bitslicedcomponents is extracted

Functional units: arithmetic and

logic units

Storage units: registers, register

files

Steering units: multiplexors and

bus drivers


Logic Synthesis: Logic Minimization

Two-level minimization

Karnaught map method

Quine-McClasky method

Cubical approach: espresso

Useful for PLA, PLD etc.

Classic, will not be covered in this

course

Multi-level minimization

Given: a AND-OR network

Obtain: a functional equivalent

AND-OR network

Such that: area or critical path

delay is minimized

Useful for standard cell and FPGA

technologies


Logic Synthesis: Technology Mapping

Given a generic AND-OR logic network

Obtain a network of gates from a technology library

Such that

They are functionally equivalent

Area of critical path delay is minimized


Logic Synthesis: Sequential Synthesis

Classic optimization (will not becovered)

State encoding

State minimization

Retiming

Given: a sequential network

Obtain: a retimed sequential

network

Such that the critical path delay is

minimized


The Netlist Sign-off

Netlist consisting of cells from a given technology library

Static analyzed timing for performance guarantee

Testbench with a satisfactory code coverage

Timing constraint (SDF) for timing-driven P&R


Outline

Introduction to CAD


Course logistics

Summary


Course Organization

Three components

Lecture: deals with concept and theory

Project: learn by doing

Reading and presentation: expose to the frontier of research

Grading

Project: 60%

Final (take home): 30%

Class participation and final presentation: 10%


Other Information

References:

De Micheli 1994: suggest to buy

Gajski et. al. 1992

Synopsys online documentation

Office hour: by appointment

Course web page: http:

//www.eecg.toronto.edu/˜jzhu/courses/behsyn


Summary

This course is aboutConcept

Defining abstractions

Representing and manipulating

abstractions

TheoryFormulation: design problem -¿optimization problem

Algorithm: making the dumb

(computer) a good designer

Practice

Construct EDA tools by yourself

This course is NOT about

Introduction to VLSI:please take the prerequisite first

Use of of CAD tools:please take the VLSI methodology

course

Secret tricks of EDA tooltweaking:

please go to vendor’s training course


ece1769: introduction to cad and synthesisjzhu/courses/behsyn/notes/intro_handout.pdf · design...

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