ece 486/586 computer architecture lecture # 6web.cecs.pdx.edu/~zeshan/ece586_lec6.pdf · byte order...
TRANSCRIPT
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ECE 486/586
Computer Architecture
Lecture # 6
Spring 2019
Portland State University
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Lecture Topics
• Instruction Set Principles
– Memory Addressing
• Alignment
• Byte Order
– Addressing Modes
– Operations in the Instruction Set
Reference:
• Appendix A: Sections A.2, A.3, A.4, A.5
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Memory Addressing
• Byte Addressing– Each byte has a unique address
• Word Addressing– Half-word: 16-bit (or 2 bytes)
– Word: 32-bit (or 4 bytes)
– Double word : 64-bit (or 8 bytes)
– Quad word: 128-bit (or 16 bytes)
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Memory Addressing
• Two issues– Alignment
– Byte order (Big Endian vs. Little Endian)
• Alignment specifies whether there are any boundaries for word addressing
• Byte order specifies how multiple bytes within a word are mapped to memory addresses
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Memory Addressing
• Alignment– Must half word, words, double words begin mod 2, mod 4,
mod 8 boundaries?
160 161 162 163 164 165 166 167
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Memory Addressing
• Alignment– Or are there no alignment restrictions?
160 161 162 163 164 165 166 167
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Alignment: Why Care?
• Non-aligned memory references may cause multiple memory accesses
• Consider a system in which memory reads return 4 bytes and a reference to a word spans a 4-byte boundary: two memory accesses are required
• Complicates memory and cache controller design
• Assemblers typically force alignment for efficiency
160 161 162 163 164 165 166 167
First Access Second Access
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Memory Alignment
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Byte Order
• Little Endian:– The least significant byte within a word (or half word or double
word) is stored in the smallest address
MSB
160 161 162 163 164 165 166 167
byte 1 byte 0
161 160
LSB
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Byte Order
• Little Endian:– The least significant byte within a word (or half word or double
word) is stored in the smallest address
• Example: A word (5827A6FD)16 is stored at address 180 in little-endian format. Show the contents of bytes 180 through 183.
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Byte Order
• Little Endian:– The least significant byte within a word (or half word or double
word) is stored in the smallest address
• Example: A word (5827A6FD)16 is stored at address 180 in little-endian format. Show the contents of bytes 180 through 183.
Address Value
180 FD
181 A6
182 27
183 58
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Byte Order
• Big Endian:– The most significant byte within a word (or half word or double
word) is stored in the smallest address
MSB
160 161 162 163 164 165 166 167
byte 1 byte 0
160 161
LSB
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Byte Order
• Big Endian:– The most significant byte within a word (or half word or double
word) is stored in the smallest address
• Example: A word (5827A6FD)16 is stored at address 180 in big-endian format. Show the contents of bytes 180 through 183.
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Byte Order
• Big Endian:– The most significant byte within a word (or half word or double
word) is stored in the smallest address
• Example: A word (5827A6FD)16 is stored at address 180 in big-endian format. Show the contents of bytes 180 through 183.
Address Value
180 58
181 27
182 A6
183 FD
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Byte Order in Real Systems
• Pros/Cons– Often exaggerated
– Little Endian
• Character strings appear “backwards” in registers
• Intuitive when incrementing from LSB to MSB
• Big Endian: Motorola 68000, Sun Sparc, PDP-11
• Little Endian: VAX, Intel IA32
• Configurable: MIPS, ARM
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Addressing Modes
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Addressing Modes
• Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI
• Example (usage of auto-increment mode): – With auto-increment mode:
Add R1, (R2)+
– Without auto-increment mode
Add R1, (R2)
Add R2, #1
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Addressing Modes
• Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI
• Example (usage of displacement mode): – With displacement mode:
Add R4, 100(R1)
– Without displacement mode
Add R1, #100
Add R4, (R1)
Sub R1, #100
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Addressing Modes
• Addressing modes can reduce instruction counts but at a cost of added CPU design complexity and/or increase average CPI
• Example (usage of displacement mode): – With displacement mode:
Add R4, 100(R1)
– Without displacement mode
Add R1, #100
Add R4, (R1)
Sub R1, #100
Support most frequently used addressing modes (make the common case fast)
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Frequency of Addressing Modes
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Displacement Values are Widely Distributed
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Immediate Operand Frequency
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Distribution of Immediate Values
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Type and Size of Operands
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Operations in the Instruction Set
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Most Frequent 80x86 Instructions
Most widely executed instructions are the simple operations of an instruction setOptimize the common case => make the common instructions run as fast as possible