ece 456 computer architecture lecture #3 - function & structure instructor: dr. honggang wang
TRANSCRIPT
Dr. Wang Lecture #2 2
Administrative Issues (9/14/09, Mon.)
• Project proposal – due Monday, October 21
• Homework #1– due Monday, September 30
• Today’s topic– Review Lecture #2 (Interrupt)
– Lecture #3
Dr. Wang Lecture #2 3
Review of Lecture #2
In the last lecture, we covered the
– number systems concepts and conversions (review)
– concept of computer architecture & computer organization
– von Neumann architecture
– interrupts and multiple interrupts
– contemporary computer architecture = von Neumann architecture + interrupts
Dr. Wang Lecture #2 4
Topics
• Concept of computer function & structure
• Function: – program view: instruction cycle
– computer view: basic functions
• Structure:– hierarchical system structure
– interconnection structures: bus and multiple-bus
Dr. Wang Lecture #2 5
Structure and Function
• Structure is the way in which the components are interrelated
• Function is the operation of each individual component as part of the structure
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Computer Basic Functions
• Data processing• Data storage• Data movement
– input/output, data communications
• Control– the control of the
above three functions– control unit
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Computer Program Execution Function
• Program execution: repeating the process of instruction execution
•
Instruction cycle:
Dr. Wang Lecture #2 9
Instruction Cycle with Interrupts
Computer Program Execution Function
Fetch cycle Execute cycle Interrupt cycle
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Instruction Fetch Cycle
• Processor fetches an instruction from a memory location pointed by PC
• Unless told otherwise, the PC increments after each instruction fetch
• Fetched instruction is loaded into IR• Processor interprets the instruction in IR and
execute cycle begins
Computer Program Execution Function
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Discussion Questions
Under what situation,1. the PC’s increment is not 1?
2. the PC is not incremented in sequence?
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Instruction Execute Cycle
• Processor-memory– data transfer between CPU and memory
– data storage
• Processor-I/O– data transfer between CPU and I/O module
• Data processing– arithmetic or logic operations
• Control– alternation of instruction sequence
• Combinatorial actions
Computer Program Execution Function
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Example (1)• Both data & instructions are stored in a 16-bit memory
– Integer
– Instruction
• CPU registers: PC, IR, AC, MBR, MAR• Operation codes
– 0001: load AC from memory
– 0010: store AC to memory
– 0101: add to AC from memory
Computer Program Execution Function
S0 1 15
Opcode Address 0 153 4
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Example (2)
M(940) + M(941)
M(941)
Computer Program Execution Function
fetch execution
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How does the operation process look like if MAR
and MBR are used?
Step 1:a. The PC contains 300, the
address of the first instruction. This value is loaded in to the MAR.
b. The value in location 300 (which is the instruction with the value 1940 in hexadecimal) is loaded into the MBR, and the PC is incremented. These two steps can be done in parallel.
c. The value in the MBR is loaded into the IR.
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Steps 2 - 6• Step 2:
– The address portion of the IR (940) is loaded into the MAR.
– The value in location 940 is loaded into the MBR.– The value in the MBR is loaded into the AC.
• Step 3 – Step 6???
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Instruction Cycle State Diagram with Interrupts
Computer Program Execution Function
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Agenda• Concept of computer function & structure
• Function: – basic functions
– instruction cycle
• Structure: the way in which the components are interrelated
– hierarchical system structure
– interconnection structures: bus and multiple-bus
Dr. Wang Lecture #2 21
Hierarchical Structure
Computercommunicationlines
peripherals
Main Memory
Input/Output
Central Processing Unit
Computer
Control Unit
ALURegisters
CPU
Internal CU BusCU
RegistersCU
Decoders
Control Memory
Sequencing Logic
Control Unit
L1
L2
L3
L4
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Interconnection Structures• Interconnection structure: the collection of paths
connecting the various modules• Bus / multiple-bus structures are the most common• Its design depends on the exchanges made between
modules
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Bus Interconnection Structure
• Bus• Elements of bus design• Interconnection structure
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Bus
• A bus is a communication pathway connecting two or more devices– a shared transmission medium
– usually broadcasts
– transmits the signal of one device at a time
– often consists of multiple separate communication lines
– bus width: number of lines
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Bus Interconnection Structure
• Bus• Elements of bus design
– bus types
– methods of arbitration
– timing
– bus width
• Interconnection structure
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Bus Types (1)
• Multiplexed– data and address transmission share the same set of lines
– using Address Valid Control line
– pros & cons: • fewer lines, thus space/cost is saved
• more complex control, potential performance reduction
• Dedicated– Functional dedication
– Physical dedication
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Bus Types (2): Functional Dedication
• The use of separate dedicated – data lines
– address lines
– control lines
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Data Bus
• Moving data/instructions between system modules
• Data bus width is a key determinant of system performance
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Address Bus
• Designate source or destination of data on data bus• Address bus width determines the maximum memory
capacity• Format:
– higher-order bits for identifying a module on the bus
– lower-order bits for identifying a location inside that module
– example:
A7: 0 - the memory module 1 - the I/O module
A0
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Control Bus
• Control the access to and the use of the data lines and address lines
• Control signals: – memory read/write
– I/O read/write
– transfer ACK
– bus request/grant
– interrupt request/ACK
– clock & reset
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Bus Types (3): Physical Dedication• The use of multiple buses, each of which connects
only a subset of modules
• Pros & cons:– less bus contention, high throughput
– increased size & cost
Processor
Memory Bus Main Memory
ExternalMemory
I/O BusI/O
ModuleI/O
Module
I/O device
I/O device
…...
Dr. Wang Lecture #2 32
Method of Arbitration
• Centralized arbitration– a bus controller / arbiter controls bus access
– be separate or a part of processor
• Distributed arbitration– each module has access control logic
– all modules cooperate together to share the bus
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Timing
• Coordination of events on the bus
• According to the way to determine the occurrence of one event on the bus,– synchronous timing
• is determined by a clock
• is simple to implement & test, but less flexible
– asynchronous timing• follows and depends on the occurrence of a previous event
• is flexible and can tolerate mixed rates and technologies
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Synchronous Timing (1)
• Control bus lines include a clock line– a clock transmits a regular sequence of alternating 1s and
0s of equal duration upon it
– a clock cycle: a single transmission of 1-0
– all devices on bus can read it
– All events start at the beginning of a clock cycle
Dr. Wang Lecture #2 36
Asynchronous Timing (1)
The occurrence of one event on the bus follows and depends on the occurrence
of a previous event
Dr. Wang Lecture #2 38
Bus Width
• Data bus width affects system performance– the wider the data bus, the greater the number of bits
transferred at one time
• Address bus width affects memory capacity– the wider the address bus, the greater the range of
memory locations that can be referenced
Dr. Wang Lecture #2 39
Bus Interconnection Structure
• Bus• Elements of bus design
– bus types
– methods of arbitration
– timing
– bus width
• Interconnection structure
Dr. Wang Lecture #2 40
Single Bus Structure
• Advantages: simple, convenient, flexible• Problems:
– propagation delay– bottleneck
CPUMain
memoryI/O
moduleI/O
module
System Bus
…...
I/O device
I/O device
…...
Dr. Wang Lecture #2 41
2 - Bus Structure
Processor
Memory Bus Main Memory
ExternalMemory: Tape/Disk
I/O BusI/O Module
I/O Module
I/O device
I/O device
…...
Dr. Wang Lecture #2 42
3 - Bus Structure (1)
Processor
MemoryMemory
I/O BusI/O Module
I/O Module
I/O device
I/O device
…...
Data Bus Instruction Bus
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3 - Bus Structure (2): Mezzanine
ProcessorMemory
SCSI/LAN
System Bus
Bridge
High-speed I/O busGraphics/Video
Expansion bus interface
Expansion (low-speed I/O) bus FaxModem
Serial
Dr. Wang Lecture #2 44
4 - Bus Structure
Processor
MemoryMemory
I/O Module
I/O Module
Output device
Outputdevice
…...
Data Bus Instruction Bus
Input BusOutput Bus
Input device
Inputdevice
…...
Dr. Wang Lecture #2 45
Summary of Lecture #3
• Concept of computer function & structure
• Computer basic functions (4 kinds) and program
execution function (instruction cycle)
• 4-level hierarchical computer structure
• Computer interconnection structures
– bus and its design elements
– single and multiple bus structures
Dr. Wang Lecture #2 46
Next Topics
• Memory Systems
– Characteristics of memory systems
– Memory hierarchy
– Error correction in memory
– More……
Wireless Transmission Fundamentals (Physical Layer) Professor Honggang Wang Email: [email protected]
ECE 456 Computer Architecture Lecture #2 - Architecture & Organization Instructor: Dr. Honggang Wang