ece 448: spring 2014 lab 3 fpga design flow based on xilinx ise and isim. using seven-segment...
TRANSCRIPT
ECE 448: Spring 2014Lab 3
FPGA Design Flow Based on Xilinx ISE and Isim.
Using Seven-Segment Displays, Buttons, and Switches.
Part 1: Distribution and testing of FPGA boards
Part 2: Seven Segment Displays
Part 3: User Constraints File
Part 4: Buttons and Switches
Part 5: Introduction to FPGA Design Flow based on Xilinx ISE
Part 6: Introduction to Lab 3
Part 7: Class Exercise
Agenda for today
Part 1
Distribution and Testing
of FPGA Boards
Part 2
Seven Segment Displays
Seven Segment Displays
4-Digit Seven Segment Display
Patterns for Decimal Digits
Patterns for Hexadecimal Digits
Connection to FPGA Pins
Multiplexing Digits
Time-Multiplexed Seven Segment Display
Counter UPCOUNTER UP
Counter UP
q(k-1..k-2)
AN
Counter UP
SEG(6..0)
Counter UP
Counter UPrst
clkOC
SSD_DRIVER
OC – One’s Complement
Size of the counter
1 ms ≤ 2k * TCLK ≤ 16 ms
fCLK = 100 MHz
k = ?
Part 3
User Constraint File (UCF)
User Constraint File (UCF)
• File contains various constraints for Xilinx– Clock Period– Circuit Locations– Pin Locations
• Every pin in the top-level unit needs to have a pin in the UCF
User Constraint File (UCF) - SSD# Seven Segment Displays
NET "SEG<0>" LOC = "T17" | IOSTANDARD = "LVCMOS33";
NET "SEG<1>" LOC = "T18" | IOSTANDARD = "LVCMOS33";
NET "SEG<2>" LOC = "U17" | IOSTANDARD = "LVCMOS33";
NET "SEG<3>" LOC = "U18" | IOSTANDARD = "LVCMOS33";
NET "SEG<4>" LOC = "M14" | IOSTANDARD = "LVCMOS33";
NET "SEG<5>" LOC = "N14" | IOSTANDARD = "LVCMOS33";
NET "SEG<6>" LOC = "L14" | IOSTANDARD = "LVCMOS33";
NET "AN<0>" LOC = "N16" | IOSTANDARD = "LVCMOS33";
NET "AN<1>" LOC = "N15" | IOSTANDARD = "LVCMOS33";
NET "AN<2>" LOC = "P18" | IOSTANDARD = "LVCMOS33";
NET "AN<3>" LOC = "P17" | IOSTANDARD = "LVCMOS33";
User Constraint File (UCF) - LEDs
# LEDs
NET "LED<0>" LOC = "U16" | IOSTANDARD = "LVCMOS33";
NET "LED<1>" LOC = "V16" | IOSTANDARD = "LVCMOS33";
NET "LED<2>" LOC = "U15" | IOSTANDARD = "LVCMOS33";
NET "LED<3>" LOC = "V15" | IOSTANDARD = "LVCMOS33";
NET "LED<4>" LOC = "M11" | IOSTANDARD = "LVCMOS33";
NET "LED<5>" LOC = "N11" | IOSTANDARD = "LVCMOS33";
NET "LED<6>" LOC = "R11" | IOSTANDARD = "LVCMOS33";
NET "LED<7>" LOC = "T11" | IOSTANDARD = "LVCMOS33";
# Buttons
NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33";
User Constraint File (UCF) CLOCK
Part 4
Switches and Buttons
Buttons
Connection of Buttons to FPGA Pins
Debouncing Buttons
Bouncing period typically smaller than 10 ms
key bounce, tBOUNCE key bounce, tBOUNCE
Using DEBOUNCE_RED to Generate Short Pulses (1)
RED – Rising Edge Detector
Using DEBOUNCE_RED to Generate Short Pulses (2)
# Buttons
NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS
NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU
NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL
NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND
NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR
User Constraint File (UCF) Buttons
SW SW_SIG
Using Switches
8
User Constraint File (UCF) Switches
# Switches
NET "SW<0>" LOC = "T10" | IOSTANDARD = "LVCMOS33";
NET "SW<1>" LOC = "T9" | IOSTANDARD = "LVCMOS33";
NET "SW<2>" LOC = "V9" | IOSTANDARD = "LVCMOS33";
NET "SW<3>" LOC = "M8" | IOSTANDARD = "LVCMOS33";
NET "SW<4>" LOC = "N8" | IOSTANDARD = "LVCMOS33";
NET "SW<5>" LOC = "U8" | IOSTANDARD = "LVCMOS33";
NET "SW<6>" LOC = "V8" | IOSTANDARD = "LVCMOS33";
NET "SW<7>" LOC = "T5" | IOSTANDARD = "LVCMOS33";
Part 5
Hands-on Session on
FPGA Design Flow
based on Xilinx ISE
and Xilinx ISim
Part 6
Introduction to Lab 3
Movie Ticket Dispensing Machine
Stage 1: Choose a Movie
BTNU (UP)
BTNDDOWN
BTNR(RIGHT)
BTNLLEFT
BTNS (Enter)
Default
BTNS (Enter)
Stage 2: Choose Ticket Quantity
Use UP and Down buttons to change the quantity
18 + 13.5 + 9 + 9 = 49.50
Stage 3: Entering Bills
$1 UP
$5DOWN
$20RIGHT
$10LEFT
Blink for 5 sec
Total Amount
Change
Part 7
Lab Exercise
16-bit Binary Up-Down Counter
Fig 1. Block Diagram
rst
clk
Debouncer
rst
clk
REDBTNU
rst
clk
Debouncer
rst
clk
REDBTND
UP/ DOWN COUNTER
en_UP
en_DOWN
C_3..0 hex0hex1
SSD_DRIVER
hex2hex3
C_7..4C_11..8C_15..12
rst
SEG
AN
SEG_6..0
AN_3..0
clkrst
Counter UPCOUNTER UP
Counter UP
q(k-1..k-2)
AN
Counter UP
SEG(6..0)
Counter UP
Counter UPrst
clkOC
SSD_DRIVER
OC – One’s Complement