ECE 448: Spring 12

Lab Midterm Exam Review

Part 1: Detailed discussion of a selected midterm from Spring 2011.

Part 2: Review & discussion of common mistakes made by students in Lab 1-3

Part 3: Lab demos and grading

Agenda for today

Selected midterm from Spring 2011

Common mistakes made by students in Lab 1-3

Assert condition:o The message is written when the condition is FALSE.

assert initial_value <= max_value report "initial value too large" severity error;

Mistakes in Lab 1

Use of Test vector table and Output Comparison

Test Vector Table:

CONSTANT test_vector_table: test_vectors :=( (operation => AND_OP, a=>'0', b=>'0', y=>'0'), (operation => AND_OP, a=>'0', b=>'1', y=>'0'), (operation => AND_OP, a=>'1', b=>'0', y=>'0'), (operation => AND_OP, a=>'1', b=>'1', y=>'1'),

(operation => OR_OP, a=>'0', b=>'0', y=>'0'), (operation => OR_OP, a=>'0', b=>'1', y=>'1'), (operation => OR_OP, a=>'1', b=>'0', y=>'1'), (operation => OR_OP, a=>'1', b=>'1', y=>'1'), (operation => XOR_OP, a=>'0', b=>'0', y=>'0'), (operation => XOR_OP, a=>'0', b=>'1', y=>'1'), (operation => XOR_OP, a=>'1', b=>'0', y=>'1'),

(operation => XOR_OP, a=>'1', b=>'1', y=>'0'), (operation => XNOR_OP, a=>'0', b=>'0', y=>'1'), (operation => XNOR_OP, a=>'0', b=>'1', y=>'0'),

(operation => XNOR_OP, a=>'1', b=>'0', y=>'0'), (operation => XNOR_OP, a=>'1', b=>'1', y=>'1'));

Providing Input:

test_operation <= test_vector_table(i).operation;test_a <= test_vector_table(i).a;test_b <= test_vector_table(i).b;

Comparing Output:

IF test_y /= test_vector_table(i).y THEN error_cnt := error_cnt + 1;

Choosing proper libraries:

o USE ieee.numeric_std.all;

o USE ieee.std_logic_unsigned.all ;

o USE ieee.std_logic_signed.all ;

Opcodes:

o Rotation right with Carry by 2

o Arithmetic Shift Right by 3 with Rounding

o Variable Rotation Right

o Variable Logic Shift Left

o Variable Arithmetic Shift Right with Rounding

o Variable Logic Shift Right

Mistakes in Lab 2

• Difference between Dataflow, Structural and Behavioral coding styleso Dataflow: Concurrent statements

o Structural: Components and Interconnects

o Behavioral: Processes

• Difference between Combinational and Sequential logico Combination: Not dependent on Clock

o Sequential: Dependent on Clock (Registers, Shift registers. Counters, State machines)

o Use of Genericso Shift Register

Mistakes in Lab 3

Variable left shift

Use of Generics and For Generate:Variable 16-bit rotator

TYPE array1 IS ARRAY (0 to 4) OF STD_LOGIC_VECTOR(15 DOWNTO 0);TYPE array2 IS ARRAY (0 to 3) OF STD_LOGIC_VECTORS(15 DOWNTO 0);

SIGNAL Al : array1;SIGNAL Ar : array2;

BEGINAl(0) <= A;G: FOR i IN 0 TO 3 GENERATE

ROT_I: fixed_rotator_left_16 GENERIC MAP (L => 2** i) PORT MAP (

a => Al(i) ,y => Ar(i));

MUX_I: mux2to1_16 PORT MAP (w0 => Al(i),

w1 => Ar(i), s => B(i), f => Al(i+1));

END GENERATE;C <= Al(4);

END variable_rotator_16;

Shift Register With Parallel Load

D(3)

D Q

Clock

Enable

SinD(2)

D Q

D(1)

D Q

D(0)

D Q

Q(0)Q(1)Q(2)Q(3)

Load

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY shiftn ISGENERIC ( N : INTEGER := 8 ) ;PORT ( D : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

Enable : IN STD_LOGIC ;Load : IN STD_LOGIC ;Sin : IN STD_LOGIC ;Clock : IN STD_LOGIC ;Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftn ;

N-bit shift register with parallel load (1)

Q

Enable

Clockshiftn

N

D

Load

Sin

N

ARCHITECTURE behavioral OF shiftn ISSIGNAL Qt: STD_LOGIC_VECTOR(N-1 DOWNTO 0);

BEGINPROCESS (Clock)BEGIN

IF rising_edge(Clock) THENIF Enable = ‘1’ THEN

IF Load = '1' THENQt <= D ;

ELSEQt <= Sin & Qt(N-1 downto 1);

END IF;END IF ;

END PROCESS ;Q <= Qt;

END behavior al;

N-bit shift register with parallel load (2)

Q

Enable

Clockshiftn

N

D

Load

Sin

N

Lab 4 Demos