ece 415/515 analog integrated circuit design...telescopic+class-ab stage v bias2 v bias5 • note...
TRANSCRIPT
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ECE 415/515 –ANALOG INTEGRATED CIRCUIT DESIGN
OPAMP DESIGN AND SIMULATION
© Vishal Saxena
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OPAMP DESIGN PROJECT
VCM
vin/2
-vin/2
R1
R1
R2
R2
CL
CL
VCMvout
VCM
vin
CL
RL
vout
(a) (b)
ECE415/EO ECE515
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DESIGN SPECIFICATIONS
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TWO-STAGE OPAMP
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TWO-STAGE OPAMP: MILLER COMPENSATION
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MILLER COMPENSATION EQUATIONS
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TWO-STAGE OPAMP: ZERO-NULLING R
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VOLTAGE BUFFER COMPENSATION
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COMMON-GATE COMPENSATION
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CLASS-A STAGE: SLEWING
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CLASS-AB STAGE: FLOATING MIRROR
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TELESCOPIC+CLASS-AB STAGE
Vbias2
Vbias5
• Note that in this schematic, Indirect compensation is used.• Cc is connected between
vout and an internal low-impedance node
• For Miller compensation, connect Cc between nodes 1 and 2.
• Vbias5 is generated using a replica bias circuit
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FOLDED-CASCODE STAGE
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FOLDED-CASCODE WITH CLASS-AB OUTPUT
• Note that in this schematic, Indirect compensation is used.• Cc is connected
between vout and aninternal low-impedance node
• For Miller compensation, connect Cc between nodes 1 and 2.
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FC+CLASS-AB+RAIL-TO-RAIL INPUT
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GAIN ENHANCEMENT
• Note that in this schematic, Indirect compensation is used.• Cc is connected
between vout and aninternal low-impedance node
• For Miller compensation, connect Cc between nodes 1 and 2.
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CADENCE SPECTRE STB ANALYSIS
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SPECTRE STB ANALYSIS
• The STB analysis linearizes the circuit about the DC operating point and computes the loop-gain, gain and phase margins (if the sweep variable is frequency), for a feedback loop or a gain device [1].
• Refer to the Spectre Simulation Refrence [1] and [2] for details.
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EXAMPLE SINGLE-ENDED OPAMP SCHEMATIC
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STB ANALYSIS TEST BENCH
• Pay attention to the iprobe component (from analogLib)• Acts as a short for DC, but breaks the loop in stb analysis
• Place the probe at a point where it completely breaks (all) the loop(s).
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DC ANNOTATION
• Annotating the node voltages and DC operating points of the devices helps debug the design• Check device gds to see if its in triode or saturation regions
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SIMULATION SETUP
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BODE PLOT SETUP
• Results->Direct Plot-> Main Form
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OPEN-LOOP RESPONSE (BODE PLOTS)
• Here, fun=152.5 MHz, PM=41.8°• Best to use the stb analysis with circuit is in the desired feedback configuration
• Break the loop with realistic DC operation points
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SMALL STEP RESPONSE
Observe the ringing (PM was 41°)
Compensate more (↑ Cc and/or ↑ gm2)
10mV
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LARGE STEP RESPONSE
Note the slewing in the output
Class-A: I2/CL
Class-AB: ISS/CC
500mV
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XF ANALYSIS (FOR CMRR, PSRR)
• For CMRR and PSRR plots, you can use xf analysis.
• Set up your testbench sources for the supplies (of course), but also a source
representing the common mode voltage.
• Then run an xf analysis and tell it where the output of the circuit.
• You can then plot the transfer function from every source to the differential
output of the circuit.
http://www.designers-guide.org/books/dg-spice/ch3.pdf
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XF ANALYSIS
• XF analysis
simultaneously
computes individual
transfer functions from
every independent
source to a single
output.
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TWO-STAGE OPAMP COMPENSATION
TECHNIQUES
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MILLER COMPENSATION
1
2
vmv p vout
Vbias4
Vbias3
CC
10pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
CL
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
750Ω
iC fb
iC ff
Compensation capacitor (Cc) between the output of
the gain stages causes pole-splitting and achieves
dominant pole compensation.
An RHP zero exists at
Due to feed-forward component of the compensation current (iC).
The second pole is located at
The unity-gain frequency is
A benign undershoot in step-response due to the RHP
zeroAll the op-amps presented have been designed in AMI C5N 0.5μm CMOS process with scale=0.3 μm and Lmin=2. The op-amps drive a 30pF off-chip load offered by the test-setup.
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DRAWBACKS OF MILLER COMPENSATION
1
2
vm v p vout
Vbias4
Vbias3
CC
10pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
CL
M3 M4
M1 M2
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
220/2
100/2
100/2
x10
• The RHP zero decreases phase margin Requires large CC for compensation
(10pF here for a 30pF load!).
• Slow-speed for a given load, CL.
• Poor PSRR Supply noise feeds to the output through
CC.
• Large layout size.
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INDIRECT (AHUJA) COMPENSATION
1
2
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
220/2
100/2
100/2
x10
VDD
Vbias3
Vbias4
vm
vp
vout
Cc
CL
ic
MCGA
M3 M4
M1
M6TL
M6BL
M6TR
M6BR
M8T
M8B
M7
M2
M9
M10T
M10B
An indirect-compensated op-amp
using a common-gate stage.
• The RHP zero can be eliminated by blocking the feed-forward compensation current component by using A common gate stage, A voltage buffer, Common gate “embedded” in the cascode diff-
amp, or A current mirror buffer.
• Now, the compensation current is fed-back from the output to node-1 indirectly through a low-Z node-A.
• Since node-1 is not loaded by CC, this results in higher unity-gain frequency (fun).
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INDIRECT (CASCODE) COMPENSATION
1
2
vm v p vout
CC
1.5pF
Unlabeled NMOS are 10/2.
Unlabeled PMOS are 44/2.
VDD VDD
VDD
30pF
CL
Vbias2
Vbias3
Vbias4
A
50/2
50/2
110/2
M1 M2
M6TL
M6BL
M6TR
M6BR
M3T
M3B
M4T
M4B
M8T
M8B
M7
ic
1
2vm v p
vout
CC
1.5pF
Unlabeled NMOS are 10/2.Unlabeled PMOS are 22/2.
VDD VDD
VDD
30pF
CL
Vbias3
Vbias4
A
100/2
100/2
220/2
M1B M2B
M5T
M5B
M3
M1T
M4
M2T
M8T
M8B
M7
Vbias5
30/2
30/2
ic
Indirect-compensation using
cascoded diff-pair.
Indirect-compensation using
cascoded current mirror load.
Employing the common gate device “embedded” in the cascode structure for indirect compensation
avoids a separate buffer stage.
Lower power consumption.
Also voltage buffer reduces the swing which is avoided here.
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INDIRECT COMPENSATION: MODELING
A1 A2
Cc
1 2
vin vout
Differential
AmplifierGain Stage
Rc
A
ic
Block Diagram
Small signal analytical model
RC is the resistance
attached to node-A.
ic
vout
sCc
Rc
1
+
-
+
-
1 2
gm1vs gm2v1R1 C1 R2 C2 vout
Cc
Rc
The compensation
current (iC) is indirectly
fed-back to node-1.
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The small-signal model
for a common gate
indirect compensated op-
amp topology is
approximated to the
simplified model seen in
the last slide.
Resistance roc is
assumed to be large.
gmc>>roc-1, RA
-1,
CC>>CA
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INDIRECT COMPENSATION: EQUATIONSj
z1
un
p1p2p3
LHP zero
• Pole p2 is much farther away from fun.
• Can use smaller gm2=>less power!
• LHP zero improves phase margin.
• Much faster op-amp with lower power and
smaller CC.
• Better slew rate as CC is smaller.
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EFFECT OF LHP ZERO ON SETTLING
-40
-20
0
20
40
60
80
Mag
nitu
de (
dB)
102
104
106
108
0
45
90
135
180
Pha
se (
deg)
Bode Diagram
Frequency (Hz)
0 0.2 0.4 0.6 0.8 1 1.2
x 10-7
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1Closed Loop Step Response
Time (sec)
Am
plit
ude
Small step-input settling in follower
configuration
• In certain cases with indirect compensation, the
LHP-zero (ωz,LHP) shows up near fun.• Causes gain flattening and degrades PM
• Hard to push out due to topology restrictions
• Ringing in closed-loop step response• Used to be a benign undershoot with the RHP zero, here it can
be pesky
• Is this settling behavior acceptable?
• Watch out for the ωz,LHP for clean settling
behavior!
• When using indirect compensation be aware of the LHP-zero induced transient settling issues
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REFERENCES1. The Designer’s Guide to SPICE and Spectre: http://www.designers-
guide.org/books/dg-spice/
2. Spectre User Simulation Guide, pages 160-165: http://www.designers-
guide.org/Forum/YaBB.pl?num=1170321868
3. M. Tian, V. Viswanathan, J. Hangtan, K. Kundert, “Striving for Small-Signal
Stability: Loop-based and Device-based Algorithms for Stability Analysis of
Linear Analog Circuits in the Frequency Domain,” Circuits and Devices, Jan
2001. http://www.kenkundert.com/docs/cd2001-01.pdf
4. https://secure.engr.oregonstate.edu/wiki/ams/index.php/Spectre/STB
5. Saxena V, Baker R.J., “Indirect feedback compensation of CMOS op-amps,”
IEEE WMED 2006.
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REFERENCES6. Saxena V, Baker R.J., “Indirect compensation techniques for three-stage
CMOS op-amps,” IEEE MWSCAS 2009.
7. Saxena V., Baker R.J., “Indirect compensation techniques for three-stage
fully-differential op-amps,” IEEE MWSCAS 2010.
8. Saxena V. “Indirect Feedback Compensation Technique for Multi-Stage
Operational Amplifiers,” MS Thesis, Boise State University, 2007.