ecadlab.pdf

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Auroras Scientific & Technological Institute

Gagillapur(V), Quthubullapur (M), R. R Dist,Hyderabad-43.

The Complete Manual for ECAD LAB

Written

By

ECE Department


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Content

Page no

1) Gates 3

2) DFF 7474 4

3) Decade counter 7490 and decade counter 7490 (beh) 6

4) 4-bit counter 7493 9

5) Shift Register 7495 12

6) Universal shift Register 74195 14

7) 3x8 decoder 74138 16

8) 4 bit comparator 7485 18

9) 8x1 mux 74151 and 1x8 DE-Multiplexer (BEH Style) 21

10) 16x1 mux 74150 23

11) 16x4 RAM 74189 25

12) Stack using 16x4 RAM 74189 Queue using 16x4 RAM 74189 27


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3

1) gates

AND

OR

XOR

NOT

NAND

NOR

---Add Truth tables and VHDL codes for All gates Separately.


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2) Ic7474 (DFF with async active low clr and set)

Circuit Diagram:

Truth table:

block diagram:

D Q

Clk


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library ieee;

use ieee.std_logic_1164.all;

entity dff is

port(d,clk,set,clr:in std_logic;

q:buffer std_logic;

qbar:out std_logic);

end dff;architecture df of dff is

begin

process(clk,set,clr)

begin

if (clr = '0') then

q


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3) decade counter 7490

circuit diagram:

block diagram:

LOGIC DIAGRAM:


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Truth table:

count Q0 Q1 Q2 Q3

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 0 1

6 0 1 1 07 0 1 1 1

8 1 0 0 0

9 1 0 0 1

library ieee;


entity ic7490 is

port(clk,s1,s2,r1,r2:in std_logic;

q1,q2,q3,q4:out std_logic);

endic7490;

architecture decount of ic7490 is

component jkffport(j,k,clk,set,clr:in std_logic;

q:buffer std_logic);

end component;

component rsffport(r,s,clk,set,clr:in std_logic;


end component;

signal se,cl,q11,q22,q33,q44:std_logic;

signal one,qb44,q55:std_logic;

begin

one


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--------------------------------------------------------------------

jk flip-flop---neg edge with set and clr

---------------------------------------------------------library ieee;


entity jkff is

port(j,k,clk,set,clr:in std_logic;

q:buffer std_logic);endjkff;

architecture jkf of jkff is

begin

process(clk,set,clr)

begin

if (clr = '0') then

q


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4)binary ripple counter 7493

pin diagram:

block diagram:

Logic diagram:


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Truth table:

count Q0 Q1 Q2 Q3

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0

3 0 0 1 1

4 0 1 0 05 0 1 0 1

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

10 1 0 1 0

11 1 0 1 1

12 1 1 0 0

13 1 1 0 1

14 1 1 1 0

15 1 1 1 1

library ieee;

use ieee.std_logic_1164.all;entity ic7493 is

port(clk,r1,r2:in std_logic;


endic7493;

architecture bincount of ic7493 is

component jkffport(j,k,clk,set,clr:in std_logic;

q:bufferstd_logic);

end component;

signal cl,q11,q22,q33,q44:std_logic;

signal one:std_logic;

begin

one


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-------------------------------------------------------------------

4-bit UP counter with enable signal and asynchronous RESET

Behavioral model

-----------------------------------------------------------library IEEE;

use IEEE.std_logic_1164.all;

entity AsynCounter4 is

port( CLK, RESET, EN : in std_logic;

count : out std_logic_vector(3 downto 0) ) ;

endAsynCounter4;

architecture arch_AsynCounter4 of AsynCounter4 is

signal count_t : std_logic_vector(3 downto 0) ;

begin

process(RESET,CLK)

begin

if (RESET = '1') then

count_t


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5) shift register ic7495

Pin diagram:

library ieee;


entity ic7495 is

port(ds,p0,p1,p2,p3,s,cp1bar,cp2bar:in std_logic;


endic7495;

architecture sftrg of ic7495 is



end component;

signal d0,d1,d2,d3,db0,db1,db2,db3,clk:std_logic;signal one,q11,q22,q33,q44:std_logic;

begin

one


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db0


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6) universal shift register ic74195

block diagram:


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library ieee;


--use ieee.std_logic_unsigned.all;

--use ieee.std_logic_arith.all;

--use ieee.numeric_std.all;

entity ic74195 is

port(j,kbar,a,b,c,d,sh_ld,clk,clbar:in std_logic;qa,qb,qc,qd,qdbar:buffer std_logic);

endic74195;

architecture unisftrg of ic74195 is



end component;

signal da,db,dc,dd,clkbar:std_logic;

signal dba,dbb,dbc,dbd,one:std_logic;

begin

one


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7) 3-8 decoder 74138


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library ieee;


entity ic74138 is

port(a:in std_logic_vector (2 downto 0);

en1bar,en2bar,en3:in std_logic;

o:out std_logic_vector(7 downto 0));

endic74138;

architecture decoder3x8 of ic74138 is

signal enable:std_logic;

begin

enable o o o o o o o o o


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8) 4 bit comparator 7485

library ieee;


entity ic7485 isport(a,b:in std_logic_vector (3 downto 0);

altbin,agtbin,aeqbin:in std_logic;

altbout,agtbout,aeqbout:out std_logic);

endic7485;

architecture comp4bit of ic7485 is

begin

process(a,b,altbin,agtbin,aeqbin)

begin

altbout


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altbout


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elsif(iaeb='1')then

agb


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9) 8x1 mux 74151

library ieee;


entity ic74151 is

port(d:in std_logic_vector (7 downto 0);

s,c,b,a:in std_logic;

y:buffer std_logic;

w:out std_logic);

endic74151;

architecture mux8x1 of ic74151 is

signal sel:std_logic_vector (2 downto 0);

begin

sel


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if(s='1') then y y y y y y y y y y Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) Y(7 downto 0) U) ;

end case ;

end process;

endarch_demux8x1 ;


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10)16x1 mux 74150

library ieee;


entity ic74150 is

port(e:in std_logic_vector (15 downto 0);

gbar,d,c,b,a:in std_logic;

w:out std_logic);

endic74150;

architecture mux16x1 of ic74150 is

signal sel:std_logic_vector (3 downto 0);

begin

sel


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begin

if(gbar='1') then w w w w w w w w w w w w w w w w w w


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11)16x4 RAM 74189

library ieee;


use ieee.std_logic_unsigned.all;

--use ieee.std_logic_arith.all;

--use ieee.numeric_std.all;

entity ic74189 is

port(addr: in std_logic_vector (3 downto 0);

datin:in std_logic_vector (3 downto 0);

cs,we:in std_logic;

datout:out std_logic_vector(3 downto 0));

endic74189;

architecture ram of ic74189 is

type RAMtype is array(0 to 15) of std_logic_vector(3 downto 0);

signal RAM1:RAMtype:=(others=>(others=>'0'));

signal wena: std_logic;

begin

wena


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process (wena,addr,datin)

begin

if wena'event andwena = '1' then

RAM1(conv_integer(addr)) 'Z');

end if;end if;

end if;

end process;

-- Write Functional Section

process(Clock, Write)

begin

if (Clock'event andClock='1') then

if Enable='1' then

if Write='1' then


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tmp_ram(conv_integer(Write_Addr))


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if (wr = '0') then

nwrds


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else

addr

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