ec2357-lm

VLSI LAB MANUAL

CONTENTS

1. Study of Simulation using tools.

2. Study of Synthesis tools.

3. Place and Root and Back annotation for FPGAs.

4. Basic logic gates

5. Half adder and full adder

6. Half Subtractor and full Subtractor, 4 bit multipliers, 4 bit

adder

7. Encoder and decoder

8. Multiplexer and demultiplexer

9. Flip-Flops, PRBS generators, accumulators

10. Counters

11. Registers

12. Design of a 10 bit number controlled oscillator

VLSI Lab Manual

1

VLSI DESIGN FLOW

VLSI Lab Manual

2

ASIC DESIGN FLOW

VLSI Lab Manual

3

Fig 1:Waveform Editor - Initialize Timing Dialog Box

VLSI Lab Manual

4

Expt.No: STUDY OF SIMULATION TOOLS

Date :

AIM:

To study the Simulation tools.

THEORY:

Creating a Test Bench for Simulation:

In this section, you will create a test bench waveform containing input

stimulus you can use to simulate the counter module. This test bench

waveform is a graphical view of a test bench. It is used with a simulator

to verify that the counter design meets both behavioral and timing design

requirements. You will use the Waveform Editor to create a test bench

waveform (TBW) file.

1. Select the counter HDL file in the Sources in Project window.

2. Create a new source by selecting Project _ New Source.

3. In the New Source window, select Test Bench Waveform as the

source type, and type test bench in the File Name field.

4. Click Next.

5. The Source File dialog box shows that you are associating the test

bench with the source file: counter. Click Next.

6. Click Finish. You need to set initial values for your test bench

waveform in the Initialize Timing dialog box before the test bench

waveform editing window opens.

7. Fill in the fields in the Initialize Timing dialog box using the

information below:

Clock Time High: 20 ns.

Clock Time Low: 20 ns.

Input Setup Time: 10 ns.

Output Valid Delay: 10 ns.

Initial Offset: 0 ns

Global Signals: GSR (FPGA)

Leave the remaining fields with their default values.

VLSI Lab Manual

5

8. Click OK to open the waveform editor. The blue shaded areas are

associated with each input signal and correspond to the Input Setup Time

in the Initialize Timing dialog box. In this tutorial, the input transitions

occur at the edge of the blue cells located under each rising edge of the

CLOCK input.

Fig 2: Waveform Editor - Test Bench

Fig 3:Waveform Editor - Expected Results

VLSI Lab Manual

6

9. In this design, the only stimulus that you will provide is on the

DIRECTION port. Make the transitions as shown below for the

DIRECTION port:

Click on the blue cell at approximately the 300 ns clock transition.

The signal switches to high at this point.

Click on the blue cell at approximately the 900 ns clock transition.

The signal switches back to low.

Click on the blue cell at approximately the 1400 ns clock

transition. The signal switches to high again.

10. Select File _ Save to save the waveform. In the Sources in Project

window, the TBW file is automatically added to your project.

11. Close the Waveform Editor window.

Adding Expected Results to the Test Bench Waveform:

In this step you will create a self-checking test bench with expected

outputs that correspond to your inputs. The input setup and output delay

numbers that were entered into the Initialize Timing dialog when you

started the waveform editor are evaluated against actual results when the

design is simulated. This can be useful in the Simulate Post- Place &

Route HDL Model process, to verify that the design behaves as expected

in the target device both in terms of functionality and timing.

To create a self-checking test bench, you can edit output transitions

manually, or you can run the Generate Expected Results process:

1. Select the testbench.tbw file in the Sources in Project window.

2. Double-click the Generate Expected Simulation Results process.

This process converts the TBW into HDL and then simulates it in a

background process.

3. The Expected Results dialog box will open. Select Yes to post the

results in the waveform editor.

4. Click the “+” to expand the COUNT_OUT bus and view the transitions

that correspond to the Output Valid Delay time (yellow cells) in the

Initialize Timing dialog box.

5. Select File _ Save to save the waveform.

6. Close the Waveform Editor.Now that you have a test bench, you are

ready to simulate your design.

VLSI Lab Manual

7

Simulating the Behavioral Model (ISE Simulator): If you are using ISE Base or Foundation, you can simulate your design

with the ISE Simulator. If you wish to simulate your design with a

ModelSim simulator, skip this section and proceed to the “Simulating the

Behavioral Model (ModelSim)” section.

Fig 4:Simulator Processes for Test Bench

Fig 5:Behavioral Simulation in ISE Simulator

VLSI Lab Manual

8

To run the integrated simulation processes in ISE:

1. Select the test bench waveform in the Sources in Project window. You

can see the Xilinx ISE Simulator processes in the Processes for Source

window.

2. Double-click the Simulate Behavioral Model process. The ISE

Simulator opens and runs the simulation to the end of the test bench.

3. To see your simulation results, select the test bench tab and zoom in

on the transitions. You can use the zoom icons in the waveform view, or

right click and select a zoom command.The ISE window, including the

waveform view.

4. Zoom in on the area between 300 ns and 900 ns to verify that the

counter is counting up and down as directed by the stimulus on the

DIRECTION port.

5. Close the waveform view window. You have completed simulation of

your design using the ISE Simulator. Skip past the ModelSim section

below and proceed to the “Creating and Editing Timing and Area

Constraints”section.

Simulating the Behavioral Model (ModelSim):

If you have a ModelSim simulator installed, you can simulate your design

using the integrated ModelSim flow. You can run processes from within

ISE which launches the installed ModelSim simulator.

To run the integrated simulation processes in ISE:

1. Select the test bench in the Sources in Project window. You can

see ModelSim Simulator processes in the Processes for Source

window in Fig 6.

VLSI Lab Manual

9

Fig 6: Simulator Processes for Test Bench

Fig 7:Behavioral Simulation in ModelSim

VLSI Lab Manual

10

2. Double-click the Simulate Behavioral Model process. The ModelSim

simulator opens and runs your simulation to the end of the test bench.

The ModelSim window, including the waveform, should look like Fig 7.

To see your simulation results, view the Wave window.

1. Right-click in the Wave window and select a zoom command.


counter is counting up

and down as directed by the stimulus on the DIRECTION port.

3. Close the ModelSim window.

RESULT:

VLSI Lab Manual

11

Figure: RTL Viewer - Detailed View

VLSI Lab Manual

12

Expt.No: STUDY OF SYNTHESIS TOOLS

Date :

AIM:

To study the Synthesis tools.

THEORY:

Now that you have created the source files, verified the design‟s behavior

with simulation,and added constraints, you are ready to synthesize and

implement the design.

Implementing the Design:

1. Select the counter source file in the Sources in Project window.

2. In the Processes for Source window, click the “+” sign next to

Implement Design. The Translate, Map, and Place & Route processes

are displayed. Expand those processes as well by clicking on the “+” sign.

You can see that there are many sub-processes and options that can be

run during design implementation.

3. Double-click the top level Implement Design process.ISE determines

the current state of your design and runs the processes needed to pull your

design through implementation. In this case, ISE runs the Translate, Map

and PAR processes. Your design is now pulled through to a placed-and-

routed state. This feature is called the “pull through model.”

4. After the processes have finished running, notice the status markers in

the Processes for Source window. You should see green checkmarks next

to several of the processes, indicating that they ran successfully. If there

are any yellow exclamation points, check the warnings in the Console tab

or the Warnings tab within the Transcript window. If a red X appears next

to a process, you must locate and fix the error before you can continue.

Verification of Synthesis:

Your synthesized design can be viewed as a schematic in the Register

Transfer Level (RTL) Viewer. The schematic view shows gates and

elements independent of the targeted Xilinx® device.

1. In the Processes for Source window, double-click View RTL

Schematic found in the Synthesize - XST process group. The top

VLSI Lab Manual

13

level schematic representation of your synthesized design opens in

the workspace.

VLSI Lab Manual

14

2. Right-click on the symbol and select Push Into the Selected Instance

to view the schematic in detail.

The Design tab appears in the Sources in Project window, enabling you to

view the design hierarchy. In the schematic, you can see the design

components you created in the HDL source, and you can “push into”

symbols to view increasing levels of detail.

3. Close the schematic window.

RESULT:

VLSI Lab Manual

15

Figure 1: Floorplanner View - Detailed View

VLSI Lab Manual

16

Figure 2: Design Summary View

Expt.No: STUDY OF PLACE AND ROOT AND BACK

Date : ANNOTATION FOR FPGAS.

AIM: To study the Place and Root and Back annotation for FPGAs.

THEORY:

After implementation is complete, you can verify your design before

downloading it to a device.

Viewing Placement:

In this section, you will use the Floor planner to verify your pin outs and

placement. Floor planner is also very useful for creating area groups for

designs.

1. Select the counter source file in the Sources in Project window.

2. Click the “+” sign to expand the Place & Route group of processes.

3. Double-click the View/Edit Placed Design (Floorplanner) process.

The Floorplanner view opens.

4. Select View _ Zoom _ ToBox and then use the mouse to draw a box

around the counter instance, shown in green on the right side of the chip.

VLSI Lab Manual

17

5. This Fig 1 shows where the entire design was placed. Click on any of

the components listed in the Design Hierarchy window to see where each

component is placed.

6. Zoom in to the right side of the chip even more, and place your mouse

over the K13pad. You can see that your pinout constraint was applied -

the DIRECTION pin is placed at K13.

7. Close the Floorplanner without saving.

Viewing Resource Utilization in Reports:

Many ISE processes produce summary reports which enable you to check

information about your design after each process is run. Detailed reports

are available from the Processes for Source window. You can also view

summary information and access most often-utilized reports in the Design

Summary.

1. Click on the Design Summary tab at the bottom of the window. If you

closed the summary during this tutorial, you can reopen it by double-

clicking the View Design Summary process.

Figure 3: Timing Analyzer - Timing Summary

VLSI Lab Manual

18

Figure 4: FPGA Editor - Detailed View

2. In the Device Utilization Summary section, observe the number of

Slice Flip Flops that were used during implementation. You should see 4

flip flops, since you implemented a 4-bit counter.

3. To see other reports, scroll to the bottom of the Design Summary. You

can click on a report from here to view it in the ISE Text Editor.

Timing Closure:

In this section, you will run timing analysis on your design to verify that

your timing constraints were met. Timing closure is the process of

working on your design to ensure that it meets your necessary timing

requirements. ISE provides several tools to assist with timing closure.

1. In the Processes for Source window, under the Place & Route group of

processes, expand the Generate Post-Place & Route Static Timing

group by clicking the “+”sign.

2. Double-click the Analyze Post-Place & Route Static Timing process.

The Timing Analyzer opens.

3. To analyze the design, select Analyze Against Timing Constraints.

The Analyze with Timing Constraints dialog box opens.

4. Click OK. When analysis is complete, the timing report opens.

5. Select Timing summary from the Timing Report Description tree in

the left window. This displays the summary section of the timing report,

where you can see that no timing errors were reported.

6. Close the Timing Analyzer without saving.

VLSI Lab Manual

19

In this section, you will use the FPGA Editor to view the design. You can

view your design on the FPGA device, as well as edit the placement and

routing with the FPGA Editor.

1. Double-click the View/Edit Routed Design (FPGA Editor) process

found in the Place & Route group of processes. Your implemented design

opens in the FPGA Editor.

2. Look in the List window to examine your design components.

3. Click on the COUNT_OUT K12 IOB in the List window to select the

row. This is one of the outputs in your design.

4. With the COUNT_OUT K12 row selected, select View _ Zoom

Selection. In the editor window, you can see the COUNT_OUT<0> IOB

highlighted in red.

5. Push into (double-click) the red-highlighted COUNT_OUT K12 IOB.

You should see Fig 4.

6. Enlarge the window and zoom in so you can see more detail. This view

shows the inside of an FPGA at the lowest viewable level. The blue line

shows the route that is used through the IOB. The red lines show the

routes that are available.

Viewing the Placed and Routed Design:

VLSI Lab Manual

20

Figure 5: Simulator Processes for Test Bench

Figure 6: Timing Simulation in ISE Simulator

7. Verify that the signal goes to the pad as an output.

8. Close the FPGA Editor.

Timing Simulation (ISE Simulator):

You can verify that your design meets your timing requirements by

running a timing simulation. You can use the same test bench waveform

that was used earlier in the design flow for behavioral simulation.

When running timing simulation, the ISE tools create a structural HDL

file which includes timing information available after Place and Route is

run. The simulator will run on a model that is created based on the design

to be downloaded to the FPGA.

If you are using ISE Base or Foundation, you can simulate your design

with the ISE Simulator. To simulate your design with ModelSim, skip to

the “Timing Simulation (ModelSim)” section.

To run the integrated simulation processes:

1. Select the test bench waveform in the Sources in Project window. You

can see the ISE Simulator processes in the Processes for Source window.

2. Double-click the Simulate Post-Place & Route Model process.

This process generates a timing-annotated netlist from the implemented

design and simulates it. The resulting simulation is displayed in the

Waveform Viewer. These results look different than those you saw in the

behavioral simulation earlier in this tutorial. These results show timing

delays.

VLSI Lab Manual

21

3. To see your simulation results, zoom in on the transitions and view the

area between 300 ns and 900 ns to verify that the counter is counting up


4. Zoom in again to see the timing delay between a rising clock edge and

an output transition.

5. Click the Measure Marker button and then click near the 300 ns

mark. Drag the second marker to the point where the output becomes

stable to see the time delay between the clock edge and the transition.

6. Close the waveform view window.You have completed timing

simulation of your design using the ISE Simulator. Skip past the

ModelSim section below, and proceed to the “Creating Configuration

Data” section.

Timing Simulation (ModelSim):

If you have a ModelSim simulator installed, you can simulate your design

using theintegrated ModelSim flow. You can run processes from within

ISE which launches the installed ModelSim simulator.

1. To run the integrated simulation processes, select the test bench in the

Sources in Project window. You can see the ModelSim Simulator

processes in the Processes for Source window.

VLSI Lab Manual

22

Figure 7: Simulator Processes for Test Bench

Figure 8: Timing Simulation in ModelSim

2. Double-click the Simulate Post-Place & Route VHDL/Verilog

Model process.


counter is counting up


4. Zoom in on the rising clock edges to see that the output transitions

occur slightly later

due to the timing delay.

5. Close the ModelSim window.

VLSI Lab Manual

23

RESULT:

VLSI Lab Manual

24

Expt.No: BASIC LOGIC GATES

Date :

AIM:

To implement basic logic gates using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP.

XILINX, ModelSim software.

FPGA kit.

RS 232 cable.

PROCEDURE:

Write and draw the Digital logic system.

Write the Verilog code for above system.

Enter the Verilog code in Xilinx software.

Check the syntax and simulate the above verilog code (using

ModelSim or Xilinx) and verify the output waveform as obtained.

Implement the above code in Spartan III using FPGA kit.

AND Gate:

VLSI Lab Manual

25

# AND Gate

# ------------------------------------------------

# Input1 Input2 Output # ------------------------------------------------

# 0 0 0 # 0 1 0 # 1 0 0

# 1 1 1 # -------------------------------------------------

PROGRAM:

AND Gate: // Module Name: Andgate

module Andgate(i1, i2, out);

input i1;

input i2;

output out;

and (out,i1,i2); endmodule

// Module Name: Stimulus.v

module Stimulus_v;

// Inputs

reg i1; reg i2;

// Outputs wire out;

// Instantiate the Unit Under Test (UUT)

Output:Output:

Output:

VLSI Lab Manual

27

Andgate uut (

.i1(i1),

.i2(i2), .out(out)

); initial

begin $display("\t\t\t\tAND Gate");

$display("\t\t--------------------------------------"); $display("\t\tInput1\t\t Input2\t\t Output"); $display("\t\t--------------------------------------");

$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);

#4 $display("\t\t--------------------------------------");

end initial

begin i1=1'b0; i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

OR Gate:

Output: # OR Gate

# ------------------------------------------------ # Input1 Input2 Output

# ------------------------------------------------

# 0 0 0 # 0 1 1

# 1 0 1

# 1 1 1

# ------------------------------------------------

# 1 0 1

# 1 1 1

# ------------------------------------------------

VLSI Lab Manual

28

OR Gate: // Module Name: Orgate

module Orgate(i1, i2, out);

input i1;

input i2;

output out;

or(out,i1,i2);

endmodule

// Module Name: Simulus.v

module Simulus_v;

// Inputs

reg i1;

reg i2;

// Outputs

wire out;


Orgate uut (

VLSI Lab Manual

29

.i1(i1),

.i2(i2),

.out(out) );

initial begin $display("\t\t\t\tOR Gate");

$display("\t\t--------------------------------------"); $display("\t\tInput1\t\t Input2\t\t Output");

$display("\t\t--------------------------------------"); $monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out); #4 $display("\t\t--------------------------------------");

end

initial

begin i1=1'b0; i2=1'b0;

#1 i2=1'b1; #1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

NAND Gate:

Output: # NAND Gate # ------------------------------------------------ # Input1 Input2 Output

# ------------------------------------------------

# 0 0 1

# 0 1 1 # 1 0 1

# 1 1 0

VLSI Lab Manual

30

# ------------------------------------------------

NAND Gate: // Module Name: Nandgate

module Nandgate(i1, i2, out);

input i1;

input i2; output out; nand(out,i1,i2);

endmodule

// Module Name: Stimulus.v module Stimulus_v;

// Inputs reg i1;

reg i2;

// Outputs

wire out;

// Instantiate the Unit Under Test (UUT) Nandgate uut (

VLSI Lab Manual

31

.i1(i1),

.i2(i2),

.out(out) );

initial begin

$display("\t\t\t\tNAND Gate"); $display("\t\t--------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Output"); $display("\t\t--------------------------------------"); $monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out);

#4 $display("\t\t--------------------------------------");

end

initial begin

i1=1'b0; i2=1'b0; #1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

NOR Gate:

Output: # NOR Gate

# ------------------------------------------------

# Input1 Input2 Output

# ------------------------------------------------

# 0 0 1 # 0 1 0

# 1 0 0

# 1 1 0 # ------------------------------------------------

VLSI Lab Manual

32

NOR Gate: // Module Name: Norgate

module Norgate(i1, i2, out);

input i1;

input i2;

output out;

nor(out,i1,i2);

endmodule


module Stimulus_v;

// Inputs

reg i1;

reg i2;

// Outputs

wire out;


VLSI Lab Manual

33

Norgate uut (

.i1(i1),

.i2(i2), .out(out)

); initial

begin $display("\t\t\t\tNOR Gate");

$display("\t\t--------------------------------------"); $display("\t\tInput1\t\t Input2\t\t Output"); $display("\t\t--------------------------------------");


#4 $display("\t\t--------------------------------------");

end initial

begin i1=1'b0; i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

XOR Gate:

Output: # XOR Gate # ------------------------------------------------ # Input1 Input2 Output

# ------------------------------------------------

# 0 0 0

# 0 1 1 # 1 0 1

# 1 1 0

# -------------------------------------------------

VLSI Lab Manual

34

XOR Gate: // Module Name: Xorgate

module Xorgate(i1, i2, out);

input i1; input i2;

output out;

xor(out,i1,i2); endmodule


module Stimulus_v;

// Inputs

reg i1; reg i2;

// Outputs

wire out;

VLSI Lab Manual

35


Xorgate uut (

.i1(i1), .i2(i2),

.out(out) );

initial begin

$display("\t\t\t\tXOR Gate"); $display("\t\t--------------------------------------"); $display("\t\tInput1\t\t Input2\t\t Output");

$display("\t\t--------------------------------------");


#4 $display("\t\t--------------------------------------"); end

initial begin

i1=1'b0; i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

XNOR Gate:

Output: # XNOR Gate

# ------------------------------------------------

# Input1 Input2 Output

# ------------------------------------------------ # 0 0 1

# 0 1 0

# 1 0 0 # 1 1 1

# ------------------------------------------------

VLSI Lab Manual

36

XNOR Gate: // Module Name: Xnorgate

module Xnorgate(i1, i2, out);

input i1; input i2; output out;

xnor(out,i1,i2);

endmodule


module Stimulus_v; // Inputs

reg i1;

reg i2;

// Outputs

wire out;

VLSI Lab Manual

37


Xnorgate uut ( .i1(i1),

.i2(i2), .out(out) );

initial

begin $display("\t\t\t\tXNOR Gate"); $display("\t\t--------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Output");

$display("\t\t--------------------------------------");

$monitor("\t\t\t%b\t\t%b\t\t%b ",i1,i2,out); #4 $display("\t\t--------------------------------------");

end initial

begin

i1=1'b0; i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule

Not Gate:

Output: # NOT Gate

# ---------------------------

# Input Output # ---------------------------

# 0 1

# 1 0 # ---------------------------

VLSI Lab Manual

38

NOT Gate: // Module Name: Notgate

module Notgate(in, out);

input in;

output out; not(out,in);

endmodule


module Stimulus_v;

// Inputs reg in;



VLSI Lab Manual

39

Notgate uut (

.in(in),

.out(out) );

initial begin $display("\t\t NOT Gate");

$display("\t\t------------------------"); $display("\t\tInput\t\tOutput");

$display("\t\t------------------------"); $monitor("\t\t %b\t\t %b",in,out); #2 $display("\t\t------------------------");

end

initial begin

in=0; #1 in=1;

#1 $stop;

end

endmodule

Buffer:

Output: # BUFFER

# ---------------------------

# Input Output # ---------------------------

# 0 0

# 1 1

# ---------------------------

VLSI Lab Manual

40

Buffer:

// Module Name: Buffer

module Buffer(in, out);

input in;

output out;

buf(out,in); endmodule


// Inputs reg in;

// Outputs

wire out;

VLSI Lab Manual

41


Buffer uut (

.in(in), .out(out)

); initial

begin $display("\t\t BUFFER");

$display("\t\t------------------------"); $display("\t\tInput\t\tOutput"); $display("\t\t------------------------");

$monitor("\t\t %b\t\t %b",in,out);

#2 $display("\t\t------------------------");

end

initial begin

in=0;

#1 in=1;

#1 $stop;

end

endmodule

VLSI Lab Manual

43

RESULT:

VLSI Lab Manual

44

Expt. No: HALF ADDER AND FULL ADDER

Date :

AIM:

To implement half adder and full adder using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP


FPGA kit

VLSI Lab Manual

45

RS 232 cable.

PROCEDURE:







Half Adder:

VLSI Lab Manual

46

Output: # Half Adder

# ------------------------------------------------------------------ # Input1 Input2 Carry Sum # ------------------------------------------------------------------

# 0 0 0 0 # 0 1 0 1

# 1 0 0 1 # 1 1 1 0 # ------------------------------------------------------------------

PROGRAM:

Half Adder: // Module Name: HalfAddr

module HalfAddr(sum, c_out, i1, i2);

output sum;

output c_out;

input i1;

input i2;

xor(sum,i1,i2); and(c_out,i1,i2); endmodule


module Stimulus_v;

VLSI Lab Manual

47

// Inputs

reg i1;

reg i2; // Outputs

wire sum; wire c_out;

// Instantiate the Unit Under Test (UUT) HalfAddr uut (

.sum(sum), .c_out(c_out), .i1(i1),

.i2(i2)

);

initial begin

$display("\t\t\t\t Half Adder"); $display("\t\t----------------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Carry\t\t Sum");

$display("\t\t----------------------------------------------");

$monitor("\t\t %b\t\t %b\t\t %b\t\t %b",i1,i2,c_out,sum);

#4 $display("\t\t----------------------------------------------");

end

initial

begin

i1=1'b0; i2=1'b0;

#1 i2=1'b1;

#1 i1=1'b1; i2=1'b0;

#1 i1=1'b1; i2=1'b1;

#1 $stop;

end

endmodule Full Adder:

VLSI Lab Manual

48

Output: Full Adder

# ------------------------------------------------------------------------------------------------ # i1 i2 C_in C_out Sum # ------------------------------------------------------------------------------------------------

# 0 0 0 0 0 # 0 0 1 0 1

# 0 1 0 0 1 # 0 1 1 1 0 # 1 0 0 0 1

# 1 0 1 1 0 # 1 1 0 1 0

# 1 1 1 1 1

# -------------------------------------------------------------------------------------------------

Full Adder:

// Module Name: FullAddr module FullAddr(i1, i2, c_in, c_out, sum);

input i1;

input i2;

input c_in; output c_out;

output sum;

wire s1,c1,c2; xor n1(s1,i1,i2);

and n2(c1,i1,i2);

xor n3(sum,s1,c_in);

and n4(c2,s1,c_in);

VLSI Lab Manual

49

or n5(c_out,c1,c2);

endmodule


module Stimulus_v; // Inputs

reg i1; reg i2;

reg c_in; // Outputs

wire c_out;

wire sum;


FullAddr uut ( .i1(i1),

.i2(i2),

.c_in(c_in),

.c_out(c_out),

.sum(sum)

);

initial

begin

$display("\t\t\t\t\t\tFull Adder");

$display("\t\t----------------------------------------------------------------");

$display("\t\ti1\t\ti2\t\tC_in\t\t\tC_out\t\tSum");

$display("\t\t----------------------------------------------------------------");

$monitor(" t\t%b\t\t%b\t\t%b\t\t\t%b\t\t%b",i1,i2,c_in,c_out,sum);

#9 $display("\t\t-------------------------------------------------------------------");

end initial begin

VLSI Lab Manual

50

i1 = 0;i2 = 0;c_in = 0;

#1 i1 = 0;i2 = 0;c_in = 0;

#1 i1 = 0;i2 = 0;c_in = 1; #1 i1 = 0;i2 = 1;c_in = 0;

#1 i1 = 0;i2 = 1;c_in = 1;

#1 i1 = 1;i2 = 0;c_in = 0; #1 i1 = 1;i2 = 0;c_in = 1;

#1 i1 = 1;i2 = 1;c_in = 0;

#1 i1 = 1;i2 = 1;c_in = 1;

#2 $stop;

end

VLSI Lab Manual

51

endmodule

RESULT:

VLSI Lab Manual

52

Expt. No: HALF SUBTRACTOR & FULL SUBTRACTOR, 4

BIT MULTIPLIER, 8 BIT ADDER

Date :

AIM:

To implement half subtractor and full subtractor using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP


VLSI Lab Manual

53

FPGA kit

RS 232 cable.

PROCEDURE:







Half Subtractor:

VLSI Lab Manual

54

Output: # Half Subtractor # ------------------------------------------------------------------------ # Input1 Input2 Borrow Difference

# ------------------------------------------------------------------------- # 0 0 0 0

# 0 1 1 1 # 1 0 0 1

# 1 1 0 0

# ------------------------------------------------------------------------

PROGRAM:

Half Subtractor: // Module Name: HalfSub

module HalfSub(i0, i1, bor, dif); input i0;

input i1; output bor;

VLSI Lab Manual

55

output dif;

wire i0n;

not(i0n,i0); xor(dif,i0,i1);

and(bor,i0n,i1); endmodule


// Inputs reg i0;

reg i1;

// Outputs wire bor;

wire dif;


HalfSub uut (

.i0(i0),

.i1(i1),

.bor(bor),

.dif(dif)

);

initial

begin

$display("\t\t\t\t\tHalf Subtractor");

$display("\t\t----------------------------------------------------------");

$display("\t\tInput1\t\t Input2\t\t Borrow\t\t Difference");

$display("\t\t----------------------------------------------------------"); $monitor("\t\t\t%b\t\t%b\t\t%b\t\t%b",i0,i1,bor,dif); #4 $display("\t\t-----------------------------------------------------------");

end

initial

begin

i0=1'b0; i1=1'b0;

#1 i1=1'b1; #1 i0=1'b1; i1=1'b0;

Full Subtractor:

VLSI Lab Manual

56

Output: # Full Subtractor # ------------------------------------------------------------------------------------------------ # B_in I1 i0 B_out Difference

# ------------------------------------------------------------------------------------------------ # 0 0 0 0 0

# 0 0 1 0 1

# 0 1 0 1 1

# 0 1 1 0 0

# 1 0 0 1 1

# 1 0 1 0 0

# 1 1 0 1 0

# 1 1 1 1 1

# -------------------------------------------------------------------------------------------------

#1 i0=1'b1; i1=1'b1;

#1 $stop;

VLSI Lab Manual

57

end

endmodule

Full Subtractor: // Module Name: FullSub

module FullSub(b_in, i1, i0, b_out, dif); input b_in;

input i1; input i0; output b_out;

output dif; assign {b_out,dif}=i0-i1-b_in;

endmodule


module Stimulus_v;

// Inputs

reg b_in;

reg i1;

reg i0;

// Outputs

wire b_out;

wire dif;


FullSub uut (

.b_in(b_in),

.i1(i1),

.i0(i0),

.b_out(b_out),

.dif(dif) );

initial begin

$display("\t\t\t\t\t\tFull Subtractor");

$display("\t\t-------------------------------------------------------------------------");

$display("\t\tB_in\t\tI1\t\ti0\t\t\tB_out\t\tDifference"); $display("\t\t-------------------------------------------------------------------------");

$monitor("\t\t%b\t\t%b\t\t%b\t\t\t %b\t\t\t %b",b_in,i1,i0,b_out,dif);

#9 $display("\t\t-------------------------------------------------------------------------"); end

VLSI Lab Manual

58

initial begin

VLSI Lab Manual

59

// Initialize Inputs

b_in = 0;i1 = 0;i0 = 0;

#1 b_in = 0;i1 = 0;i0 = 0; #1 b_in = 0;i1 = 0;i0 = 1;

#1 b_in = 0;i1 = 1;i0 = 0; #1 b_in = 0;i1 = 1;i0 = 1; #1 b_in = 1;i1 = 0;i0 = 0;

#1 b_in = 1;i1 = 0;i0 = 1; #1 b_in = 1;i1 = 1;i0 = 0;

#1 b_in = 1;i1 = 1;i0 = 1; #2 $stop; end

endmodule

VLSI Lab Manual

60

module Multiplier_verilog(Nibble1,

Nibble2,Result);

input Nibble1, Nibble2;

output Result;

assign Result= (unsigned(Nibble1) *

unsigned(Nibble2));

end module

[edit] Simulation Waveform

http://en.wikibooks.org/w/index.php?title=VHDL_for_FPGA_Design/4-Bit_Multiplier&action=edit&section=2

VLSI Lab Manual

61

8 BIT ADDER

module 8bitadder_carryinput(A, B, Carry_in, SUM); input [7:0] A;

input [7:0] B; input Carry_in; output [7:0] SUM; assign SUM = A + B + Carry_in; endmodule

RESULT:

VLSI Lab Manual

62

Expt No: IMPLEMENTATION OF 2 x 4 DECODER AND

Date: 4 x 2 ENCODER

AIM:

To implement 2 x 4 Decoder and 4 x 2 Encoder Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

PROCEDURE:







VLSI Lab Manual

63

Encoder:

Output: # 4to2 Encoder # -------------------------------------

# Input Output

# -------------------------------------

# 1000 00

# 0100 01

# 0010 10

# 0001 11

# ------------------------------------

VLSI Lab Manual

64

PROGRAM:

Encoder: // Module Name: Encd2to4

module Encd2to4(i0, i1, i2, i3, out0, out1); input i0;

input i1; input i2; input i3;

output out0; output out1;

reg out0,out1; always@(i0,i1,i2,i3) case({i0,i1,i2,i3})

4'b1000:{out0,out1}=2'b00; 4'b0100:{out0,out1}=2'b01;

4'b0010:{out0,out1}=2'b10; 4'b0001:{out0,out1}=2'b11; default: $display("Invalid");

endcase

endmodule


module Stimulus_v;

// Inputs

reg i0;

reg i1;

reg i2;

reg i3;

// Outputs

wire out0;

wire out1;


Encd2to4 uut ( .i0(i0),

.i1(i1),

.i2(i2), .i3(i3),

.out0(out0),

.out1(out1)

); initial begin

$display("\t\t 4to2 Encoder");

$display("\t\t------------------------------");

VLSI Lab Manual

65

Decoder:

VLSI Lab Manual

66

$display("\t\tInput\t\t\tOutput");

$display("\t\t------------------------------");

$monitor("\t\t%B%B%B%B\t\t\t %B%B",i0,i1,i2,i3,out0,out1); #4 $display("\t\t-------------------------------");

end initial begin

i0=1; i1=0; i2=0; i3=0; #1 i0=0; i1=1; i2=0; i3=0;

#1 i0=0; i1=0; i2=1; i3=0; #1 i0=0; i1=0; i2=0; i3=1; #1 $stop;

end

endmodule

Decoder: // Module Name: Decd2to4

module Decd2to4(i0, i1, out0, out1, out2, out3);

input i0;

input i1;

output out0;

output out1;

output out2;

output out3;

reg out0,out1,out2,out3;

always@(i0,i1)

case({i0,i1})

2'b00: {out0,out1,out2,out3}=4'b1000;

2'b01: {out0,out1,out2,out3}=4'b0100;

2'b10: {out0,out1,out2,out3}=4'b0010;

2'b11: {out0,out1,out2,out3}=4'b0001;

default: $display("Invalid"); endcase

endmodule


module Stimulus_v;

// Inputs reg i0;

reg i1;

// Outputs wire out0;

wire out1;

wire out2;

wire out3;

VLSI Lab Manual

67

Output: # 2to4 Decoder

# ------------------------------------- # Input Output

# ------------------------------------- # 00 1000 # 01 0100

# 10 0010 # 11 0001

# ------------------------------------

VLSI Lab Manual

68


Decd2to4 uut (

.i0(i0), .i1(i1),

.out0(out0), .out1(out1), .out2(out2),

.out3(out3) );

initial begin $display("\t\t 2to4 Decoder"); $display("\t\t------------------------------");

$display("\t\tInput\t\t\tOutput");

$display("\t\t------------------------------");

$monitor("\t\t %b%b\t\t\t %b%b%b%b",i0,i1,out0,out1,out2,out3); #4 $display("\t\t------------------------------");

end initial begin

i0=0;i1=0;

#1 i0=0;i1=1;

#1 i0=1;i1=0;

#1 i0=1;i1=1;

#1 $stop;

end

endmodule

RESULT:

VLSI Lab Manual

70

Expt. No: MULTIPLEXER & DEMULTIPLEXER

Date :

AIM:

To implement Multiplexer & Demultiplexer using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

PROCEDURE:







VLSI Lab Manual

71

Multiplexer:

Output: # 4to1 Multiplexer

# -----------------------------------------------

# Input=1011

# -----------------------------------------------

# Selector Output # -----------------------------------------------

# {0,0} 1

# {1,0} 0

# {0,1} 1 # {1,1} 1

# -----------------------------------------------

VLSI Lab Manual

72

PROGRAM:

Multiplexer: // Module Name: Mux4to1

module Mux4to1(i0, i1, i2, i3, s0, s1, out);

input i0; input i1;

input i2; input i3;

input s0;

input s1;

output out;

wire s1n,s0n;

wire y0,y1,y2,y3;

not (s1n,s1);

not (s0n,s0);

and (y0,i0,s1n,s0n);

and (y1,i1,s1n,s0);

and (y2,i2,s1,s0n);

and (y3,i3,s1,s0);

or (out,y0,y1,y2,y3);

endmodule


module Stimulus_v;

// Inputs

reg i0; reg i1;

reg i2;

reg i3;

reg s0; reg s1;



Mux4to1 uut (

VLSI Lab Manual

73

.i0(i0),

.i1(i1),

.i2(i2), .i3(i3),

.s0(s0), .s1(s1), .out(out)

);

Demultiplexer:

VLSI Lab Manual

74

initial

begin

$display("\t\t\t 4to1 Multiplexer");

$display("\t\t------------------------------------");

#1 $display("\t\t\t Input=%b%b%b%b",i0,i1,i2,i3); $display("\t\t------------------------------------");

$display("\t\tSelector\t\t\t\tOutput");

$display("\t\t------------------------------------");

$monitor("\t\t{%b,%b}\t\t\t\t\t%b",s0,s1,out);

#4 $display("\t\t------------------------------------");

end

initial begin

i0=1; i1=0; i2=1; i3=1;

#1 s0=0; s1=0; #1 s0=1; s1=0;

#1 s0=0; s1=1; #1 s0=1; s1=1;

VLSI Lab Manual

75

#1 $stop;

end

endmodule

Demultiplexer: // Module Name: Dux1to4 module Dux1to4(in, s0, s1, out0, out1, out2, out3);

input in; input s0; input s1;

output out0; output out1;

output out2;

output out3; wire s0n,s1n;

not(s0n,s0); not(s1n,s1);

and (out0,in,s1n,s0n);

and (out1,in,s1n,s0);

and (out2,in,s1,s0n);

and (out3,in,s1,s0);

endmodule

// Module Name: stimulus.v

module stimulus_v;

// Inputs

Output: # 1to4 Demultiplexer

# -----------------------------------------------

# Input=1

# ----------------------------------------------- # Status Output

# -----------------------------------------------

# {0,0} 1000 # {0,1} 0100

# {1,0} 0010

# {1,1} 0001

# ---------------------------------------------

VLSI Lab Manual

76

reg in;

reg s0;

reg s1;

// Outputs

wire out0; wire out1; wire out2;

wire out3;


Dux1to4 uut (

.in(in),

.s0(s0), .s1(s1),

.out0(out0),

.out1(out1), .out2(out2),

.out3(out3)

VLSI Lab Manual

77

);

initial

begin $display("\t\t 1to4 Demultiplexer");

$display("\t\t------------------------------------"); #1 $display("\t\t\t\tInput=%b",in); $display("\t\t------------------------------------");

$display("\t\tStatus\t\t\t\tOutput"); $display("\t\t------------------------------------");

$monitor("\t\t{%b,%b}\t\t\t\t%b%b%b%b",s1,s0,out0,out1,out2,out3); #4 $display("\t\t------------------------------------"); end

initial

begin

in=1; #1 s1=0;s0=0;

#1 s1=0;s0=1; #1 s1=1;s0=0;

#1 s1=1;s0=1;

#1 $stop;

end

endmodule

RESULT:

VLSI Lab Manual

78

Expt.No: FLIP-FLOPS, PRBS GENERATORS, ACCUMULATORS

ACCUMULATORS

Date :

AIM:

To implement Flipflops using Verilog HDL.

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

PROCEDURE:




Check the syntax and simulate the above Verilog code (using



VLSI Lab Manual

79

Flip-Flop: D Flip-Flop:

Output: # D FipFlop

# --------------------------------------------------------------------------

# Clock Reset Input (d) Output q(~q)

# ---------------------------------------------------------------------------

# 0 0 0 0(1)

# 1 0 0 0(1)

# 0 0 1 0(1)

# 1 0 1 0(1)

# 0 0 0 0(1)

# 1 0 0 0(1)

# 0 1 1 0(1)

# 1 1 1 1(0)

# 0 1 0 1(0)

# 1 1 0 0(1)

# 0 1 1 0(1)

# 1 1 1 1(0) # 0 0 0 0(1)

# 1 0 0 0(1)

# 0 0 0 0(1) # --------------------------------------------------------------------------

VLSI Lab Manual

80

PROGRAM:

D Flip-Flop: // Module Name: DFF module DFF(Clock, Reset, d, q); input Clock;

input Reset; input d;

output q; reg q;

always@(posedge Clock or negedge Reset)

if (~Reset) q=1'b0; else q=d;

endmodule


module Stimulus_v;

// Inputs

reg Reset;

reg Clock;

reg d;

// Outputs

wire q;


DFF uut (

.Clock(Clock),

.Reset(Reset),

.d(d), .q(q) );

initial

begin

$display("\t\t\t\t\tD FipFlop");

$display("\t\t------------------------------------------------------------");

$display("\t\tClock\t\tReset\t\tInput (d)\t\tOutput q(~q)");

$display("\t\t------------------------------------------------------------"); $monitor("\t\t %d \t\t %d \t\t %d \t\t %d(%d)",Clock,Reset,d,q,~q);

#15 $display("\t\t------------------------------------------------------------");

end

always #1 Clock=~Clock;

VLSI Lab Manual

81

initial

begin

Clock=0; Reset=0;d=0; #2 Reset=0; d=1;

T Flip-Flop:

Output: # T FipFlop

# ---------------------------------------------------------------------------

# Clock Reset Input (t) Output q(~q)

# ---------------------------------------------------------------------------

# 0 0 0 0(1)

# 1 0 0 0(1)

# 0 0 1 0(1)

# 1 0 1 0(1)

# 0 0 0 0(1)

# 1 0 0 0(1)

# 0 1 1 0(1)

# 1 1 1 1(0)

# 0 1 0 1(0)

# 1 1 0 1(0)

# 0 1 1 1(0)

# 1 1 1 0(1)

# 0 0 0 0(1) # 1 0 0 0(1)

# 0 0 0 0(1)

# --------------------------------------------------------------------------

VLSI Lab Manual

82

#2 d=0; #2 Reset=1; d=1;

#2 d=0; #2 d=1;

#2 Reset=0; d=0; #1; // Gap for display. #2 $stop;

end

endmodule

T Flip-Flop: // Module Name: TFF

module TFF(Clock, Reset, t, q);

input Clock;

input Reset;

input t;

output q;

reg q;

always@(posedge Clock , negedge Reset)

if(~Reset) q=0;

else if (t) q=~q;

else q=q;

endmodule


module Stimulus_v;

// Inputs

reg Clock;

reg Reset; reg t;

// Outputs

wire q;


TFF uut ( .Clock(Clock),

.Reset(Reset),

.t(t),

.q(q)

VLSI Lab Manual

83

);

initial begin

$display("\t\t\t\t\tT FipFlop");

JK Flip-Flop:

VLSI Lab Manual

84

$display("\t\t------------------------------------------------------------"); $display("\t\tClock\t\tReset\t\tInput (t)\t\tOutput q(~q)");

$display("\t\t------------------------------------------------------------"); $monitor("\t\t %d \t\t %d \t\t %d \t\t %d(%d)",Clock,Reset,t,q,~q);

#15 $display("\t\t------------------------------------------------------------"); end always

#1 Clock=~Clock;

initial

begin Clock=0; Reset=0;t=0;

#2 Reset=0; t=1; #2 t=0;

#2 Reset=1; t=1;

#2 t=0;

#2 t=1;

#2 Reset=0; t=0;

#1; // Gap for display.

#2 $stop;

end

endmodule

JK Flip-Flop:

Program: // Module Name: JKFF

module JKFF(Clock, Reset, j, k, q);

input Clock; input Reset;

input j;

input k;

output q; reg q;

always@(posedge Clock, negedge Reset)

if(~Reset)q=0; else

begin

case({j,k})

2'b00: q=q;

2'b01: q=0; 2'b10: q=1;

VLSI Lab Manual

85

2'b11: q=~q;

endcase

end endmodule

Output: # JK FipFlop

# -------------------------------------------------------------------------- # Clock Reset Input (j,k) Output q(~q)

# --------------------------------------------------------------------------

# 0 0 (0,0) 0(1) # 1 0 (0,0) 0(1)

# 0 0 (0,1) 0(1) # 1 0 (0,1) 0(1)

# 0 0 (1,0) 0(1)

# 1 0 (1,0) 0(1)

# 0 0 (1,1) 0(1)

# 1 0 (1,1) 0(1)

# 0 1 (0,0) 0(1)

# 1 1 (0,0) 0(1)

# 0 1 (0,1) 0(1)

# 1 1 (0,1) 0(1)

# 0 1 (1,0) 0(1)

# 1 1 (1,0) 1(0)

# 0 1 (1,1) 1(0)

# 1 1 (1,1) 0(1)

# 0 0 (0,0) 0(1)

# 1 0 (0,0) 0(1)

# 0 0 (0,0) 0(1)

# -------------------------------------------------------------------------

VLSI Lab Manual

86


// Inputs

reg Clock; reg Reset; reg j;

reg k;

// Outputs

wire q; // Instantiate the Unit Under Test (UUT)

JKFF uut ( .Clock(Clock),

.Reset(Reset),

.j(j),

.k(k),

.q(q)

);

initial

begin

$display("\t\t\t\t\tJK FipFlop");

$display("\t\t--------------------------------------------------------------");

$display("\t\tClock\t\tReset\t\tInput (j,k)\t\tOutput q(~q)");

$display("\t\t--------------------------------------------------------------");

$monitor("\t\t %d \t\t %d \t\t (%d,%d) \t\t %d(%d)",Clock,Reset,j,k,q,~q);

#19 $display("\t\t--------------------------------------------------------------");

end always #1 Clock=~Clock;

initial

begin

Clock=0; Reset=0;

j=0; k=0;

#2 j=0; k=1; #2 j=1; k=0; #2 j=1; k=1;

#2 Reset=1;

j=0; k=0;

#2 j=0; k=1; #2 j=1; k=0;

#2 j=1; k=1;

#2 Reset=0; j=0; k=0;

VLSI Lab Manual

87

#1; // Gap for display.

#2 $stop;

end

endmodule

PRBS generators

module lfsr(input clk, reset, en, output reg [7:0] q);

always @(posedge clk or posedge reset) begin

if (reset)

q <= 8'd1; // can be anything except zero

else if (en)

q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; // polynomial for maximal

LFSR

end

endmodule;

1. reg [18:0] lfsr=0;

2.

3. always @ (posedge

clock)

lfsr <= {lfsr, ~lfsr[18]^lfsr[5]^lfsr[1]^lfsr[0]};

VLSI Lab Manual

88

Accumulator

module accum (C, CLR, D, Q);

input C, CLR;

input [3:0] D;

output [3:0] Q;

reg [3:0] tmp;

always @(posedge C or posedge CLR)

begin

if (CLR)

tmp = 4'b0000;

else

tmp = tmp + D;

end

assign Q = tmp;

endmodule

RESULT:

VLSI Lab Manual

89

Expt No: IMPLEMENTATION OF COUNTERS

Date:

AIM:

To implement Counters using Verilog HDL

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

PROCEDURE:







VLSI Lab Manual

90

Counter:

VLSI Lab Manual

91

PROGRAM:

2- Bit Counter: // Module Name: Count2Bit

module Count2Bit(Clock, Clear, out); input Clock; input Clear;

output [1:0] out; reg [1:0]out;

always@(posedge Clock, negedge Clear) if((~Clear) || (out>=4))out=2'b00; else out=out+1;

endmodule


module Stimulus_v;

// Inputs

reg Clock;

reg Clear;

// Outputs

wire [1:0] out;


Count2Bit uut (

.Clock(Clock),

.Clear(Clear),

.out(out)

);

initial begin

$display("\t\t\t 2 Bit Counter");

$display("\t\t----------------------------------------");

$display("\t\tClock\t\tClear\t\tOutput[2]");

$display("\t\t----------------------------------------");

$monitor("\t\t %b\t\t %b \t\t %b ",Clock,Clear,out);

#28 $display("\t\t----------------------------------------"); end always

#1 Clock=~Clock;

initial

begin Clock=0;Clear=0;

VLSI Lab Manual

92

#10 Clear=1;

#16Clear=0;

#2 $stop; end

endmodule

Output: # 2 Bit Counter # --------------------------------------------------- # Clock Clear Output[2]

# --------------------------------------------------- # 0 0 00

# 1 0 00

# 0 0 00 # 1 0 00

# 0 0 00 # 1 0 00

# 0 0 00

# 1 0 00

# 0 0 00

# 1 0 00

# 0 1 00

# 1 1 01

# 0 1 01

# 1 1 10

# 0 1 10

# 1 1 11

# 0 1 11

# 1 1 00

# 0 1 00

# 1 1 01 # 0 1 01

# 1 1 10

# 0 1 10

# 1 1 11 # 0 1 11

# 1 1 00

# 0 0 00 # 1 0 00

# ------------------------------------------------

VLSI Lab Manual

93

VLSI Lab Manual

94

RESULT:

Expt No: IMPLEMENTATION OF REGISTERS

Date:

AIM:

To implement Registers using Verilog HDL

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

PROCEDURE:







VLSI Lab Manual

95

Register:

OutPut: # 2 Bit Register

# -----------------------------------------------------------------------

# Clock Clear Input[2] Output[2]

# -----------------------------------------------------------------------

# 0 0 00 00

# 1 0 00 00

# 0 0 01 00

# 1 0 01 00

# 0 0 10 00

# 1 0 10 00 # 0 0 11 00

# 1 0 11 00

# 0 1 00 00 # 1 1 00 00

# 0 1 01 00

# 1 1 01 01

# 0 1 10 01

# 1 1 10 10

# 0 1 11 10

# 1 1 11 11 # 0 0 11 00

# 1 0 11 00

# 0 0 11 00

# --------------------------------------------------------------------

VLSI Lab Manual

96

PROGRAM:

2 – Bit Register: // Module Name: Reg2Bit module Reg2Bit(Clock, Clear, in, out);

input Clock; input Clear;

input [0:1] in;

output [0:1] out;

reg [0:1] out;

always@(posedge Clock, negedge Clear)

if(~Clear) out=2'b00;

else out=in;

endmodule


module Stimulus_v;

// Inputs

reg Clock;

reg Clear;

reg [0:1] in;

// Outputs

wire [0:1] out;


Reg2Bit uut (

.Clock(Clock),

.Clear(Clear), .in(in),

.out(out)

); initial

begin

$display("\t\t\t\t 2 Bit Register");

$display("\t\t------------------------------------------------------");

VLSI Lab Manual

97

$display("\t\tClock\t\tClear\t\tInput[2]\t\tOutput[2]");

$display("\t\t------------------------------------------------------");

$monitor("\t\t %b\t\t %b \t\t %b \t\t %b ",Clock,Clear,in,out); #19 $display("\t\t------------------------------------------------------");

end always #1 Clock=~Clock;

initial begin

Clock=0;Clear=0; in=2'b00; #2 in=2'b01;

VLSI Lab Manual

98

#2 in=2'b10; #2 in=2'b11;

#2 Clear=1; in=2'b00;

#2 in=2'b01;

#2 in=2'b10;

#2 in=2'b11;

#2 Clear=0;

#1; //Gap for display.

#2 $stop;

end

endmodule

RESULT:

VLSI Lab Manual

99

Expt. No: Design of a 10 bit number controlled oscillator using

standard cell approach

Date:

AIM:

To design a a 10 bit number controlled oscillator using standard cell

approach

APPARATUS REQUIRED:

PC with Windows XP.


FPGA kit.

RS 232 cable.

Design of a 10 bit number controlled oscillator using standard cell approach

LIBRARY ieee; USE ieee.std_logic_1164.all;

USE IEEE.numeric_std.ALL;

VLSI Lab Manual

100

ENTITY nco IS

-- Declarations port ( clk : in std_logic; reset : in std_logic;

din : in signed(11 downto 0); dout : out signed(7 downto 0)

); END nco ;

-- hds interface_end

ARCHITECTURE behavior OF nco IS

type vectype is array (0 to 256) of signed(7 downto 0); -- ROM cosrom

constant cosrom : vectype := ( 0 => "01111111",

1 => "01111111",

2 => "01111111",

3 => "01111111",

4 => "01111111",

5 => "01111111",

6 => "01111111",

7 => "01111111",

8 => "01111111",

9 => "01111111",

10 => "01111111",

11 => "01111111",

12 => "01111111",

13 => "01111111",

14 => "01111111", 15 => "01111111", 16 => "01111111",

17 => "01111111",

18 => "01111111",

19 => "01111111",

20 => "01111111",

21 => "01111111", 22 => "01111111", 23 => "01111111",

24 => "01111111",

25 => "01111110",

26 => "01111110", 27 => "01111110",

28 => "01111110",

29 => "01111110",

VLSI Lab Manual

101

30 => "01111110",

31 => "01111110",

32 => "01111110", 33 => "01111101",

34 => "01111101", 35 => "01111101", 36 => "01111101",

37 => "01111101", 38 => "01111101",

39 => "01111100", 40 => "01111100", 41 => "01111100",

42 => "01111100",

43 => "01111100",

44 => "01111011", 45 => "01111011",

46 => "01111011", 47 => "01111011",

48 => "01111010",

49 => "01111010",

50 => "01111010",

51 => "01111010",

52 => "01111010",

53 => "01111001",

54 => "01111001",

55 => "01111001",

56 => "01111001",

57 => "01111000",

58 => "01111000",

59 => "01111000",

60 => "01110111",

61 => "01110111", 62 => "01110111", 63 => "01110111",

64 => "01110110",

65 => "01110110",

66 => "01110110",

67 => "01110101",

68 => "01110101", 69 => "01110101", 70 => "01110100",

71 => "01110100",

72 => "01110100",

73 => "01110011", 74 => "01110011",

75 => "01110011",

76 => "01110010",

VLSI Lab Manual

102

77 => "01110010",

78 => "01110010",

79 => "01110001", 80 => "01110001",

81 => "01110001", 82 => "01110000", 83 => "01110000",

84 => "01101111", 85 => "01101111",

86 => "01101111", 87 => "01101110", 88 => "01101110",

89 => "01101101",

90 => "01101101",

91 => "01101101", 92 => "01101100",

93 => "01101100", 94 => "01101011",

95 => "01101011",

96 => "01101010",

97 => "01101010",

98 => "01101010",

99 => "01101001",

100 => "01101001",

101 => "01101000",

102 => "01101000",

103 => "01100111",

104 => "01100111",

105 => "01100110",

106 => "01100110",

107 => "01100101",

108 => "01100101", 109 => "01100100", 110 => "01100100",

111 => "01100011",

112 => "01100011",

113 => "01100010",

114 => "01100010",

115 => "01100001", 116 => "01100001", 117 => "01100000",

118 => "01100000",

119 => "01011111",

120 => "01011111", 121 => "01011110",

122 => "01011110",

123 => "01011101",

VLSI Lab Manual

103

124 => "01011101",

125 => "01011100",

126 => "01011100", 127 => "01011011",

128 => "01011011", 129 => "01011010", 130 => "01011001",

131 => "01011001", 132 => "01011000",

133 => "01011000", 134 => "01010111", 135 => "01010111",

136 => "01010110",

137 => "01010101",

138 => "01010101", 139 => "01010100",

140 => "01010100", 141 => "01010011",

142 => "01010010",

143 => "01010010",

144 => "01010001",

145 => "01010001",

146 => "01010000",

147 => "01001111",

148 => "01001111",

149 => "01001110",

150 => "01001110",

151 => "01001101",

152 => "01001100",

153 => "01001100",

154 => "01001011",

155 => "01001010", 156 => "01001010", 157 => "01001001",

158 => "01001000",

159 => "01001000",

160 => "01000111",

161 => "01000111",

162 => "01000110", 163 => "01000101", 164 => "01000101",

165 => "01000100",

166 => "01000011",

167 => "01000011", 168 => "01000010",

169 => "01000001",

170 => "01000001",

VLSI Lab Manual

104

171 => "01000000",

172 => "00111111",

173 => "00111110", 174 => "00111110",

175 => "00111101", 176 => "00111100", 177 => "00111100",

178 => "00111011", 179 => "00111010",

180 => "00111010", 181 => "00111001", 182 => "00111000",

183 => "00111000",

184 => "00110111",

185 => "00110110", 186 => "00110101",

187 => "00110101", 188 => "00110100",

189 => "00110011",

190 => "00110011",

191 => "00110010",

192 => "00110001",

193 => "00110000",

194 => "00110000",

195 => "00101111",

196 => "00101110",

197 => "00101101",

198 => "00101101",

199 => "00101100",

200 => "00101011",

201 => "00101010",

202 => "00101010", 203 => "00101001", 204 => "00101000",

205 => "00100111",

206 => "00100111",

207 => "00100110",

208 => "00100101",

209 => "00100100", 210 => "00100100", 211 => "00100011",

212 => "00100010",

213 => "00100001",

214 => "00100001", 215 => "00100000",

216 => "00011111",

217 => "00011110",

VLSI Lab Manual

105

218 => "00011110",

219 => "00011101",

220 => "00011100", 221 => "00011011",

222 => "00011011", 223 => "00011010", 224 => "00011001",

225 => "00011000", 226 => "00011000",

227 => "00010111", 228 => "00010110", 229 => "00010101",

230 => "00010100",

231 => "00010100",

232 => "00010011", 233 => "00010010",

234 => "00010001", 235 => "00010001",

236 => "00010000",

237 => "00001111",

238 => "00001110",

239 => "00001101",

240 => "00001101",

241 => "00001100",

242 => "00001011",

243 => "00001010",

244 => "00001010",

245 => "00001001",

246 => "00001000",

247 => "00000111",

248 => "00000110",

249 => "00000110", 250 => "00000101", 251 => "00000100",

252 => "00000011",

253 => "00000010",

254 => "00000010",

255 => "00000001",

256 => "00000000"); signal dtemp : unsigned(17 downto 0);

signal din_buf : signed(17 downto 0);

signal dtemp1 : integer;

constant offset : unsigned(17 downto 0) := "000100000000000000";

begin

VLSI Lab Manual

106

process(CLK, RESET)

begin

if (RESET='1') then dout <= (others => '0');

din_buf <= (others => '0'); dtemp <= (others => '0'); dtemp1 <= 0;

elsif rising_edge(CLK) then din_buf <= din(11)&din(11)&din(11)&din(11)&din(11)&din(11)&di n;

dtemp <= dtemp + unsigned(din_buf) + offset; dtemp1 <= to_integer(dtemp(17 downto ); if (dtemp1 >= 0) and (dtemp1 < 257) then

dout <= cosrom(dtemp1);

elsif (dtemp1 >= 257) and (dtemp1 < 513) then

dout <= -cosrom(512-dtemp1); elsif (dtemp1 >= 513) and (dtemp1 < 769) then

dout <= -cosrom(dtemp1-512); else

dout <= cosrom(1024-dtemp1);

end if;

end if;

end process;

RESULT:

VLSI Lab Manual

153

How to work in XILINX

Step 1: Open Xilinx software

Step 2: Select File New Project.

VLSI Lab Manual

154

Step 3: In the New Project window enter project name and project

location.

VLSI Lab Manual

155

Step 4: Select the corresponding entries for the property names.

Step 5: Click New Source.

VLSI Lab Manual

156

Step 6: Enter the file name and then select Verilog module.

VLSI Lab Manual

157

Step 7: Define the input and output port names ,then click Next for all

successive windows.

Step 8: The Verilog file will be created under .ise file.

VLSI Lab Manual

158

Step 9: Double click the Verilog file and enter the logic details and save

the file.

VLSI Lab Manual

159

Step 10: Double click Synthesize – XST for checking the syntax .

Step 11: Right click the halfadd.v file and select new source ,then click

Implementation Constraints File and enter the filename.

VLSI Lab Manual

160

Step 12:.ucf file will be created

.

Step13: Open the .ucf file and enter the pin location and save the file

VLSI Lab Manual

161

Step14: Goto Generate programming file and select Generate

PROM,ACE or JTAG file in the processes window.

VLSI Lab Manual

162

Step 15: In Slave Serial mode ,right click and select Add Xilinx Device.

Step 16: In the Add Device window select the .bit file to add the device.

VLSI Lab Manual

163

Step 17: Connect the RS232 cable between computer and kit. Connect the

SMPS to kit and switch on the kit.

Step 18: Right click the device and select Program to transfer the file to

kit.

Step 19: After successful transmission of file “Programming Succeeded”

will be displayed.

VLSI Lab Manual

164

ec2357-lm

Documents

vlsi lab manual

digital logic

outputs wire

initial begin

end initial

input setup

endmodule

checking test