ec 1258-digital electronics lab

7/29/2019 Ec 1258-Digital Electronics Lab

1/38

EC1258 DIGITAL ELECTRONICS LAB

LIST OF EXPERIMENTS

1. ADDER AND SUBTRACTOR

2. BINARY CODE TO GRAY CODE AND VICEVERSA

3. BCD TO EXCESS3 CODE AND VICE VERSA

4. MAGNITUDE COMPARATOR

5. MULTIPLEXER AND DEMULTIPLEXER

6. 9 BIT PARITY GENERATOR/CHECKER

7. ENCODER AND DECODER

8. SHIFT REGISTER

9. SYNCHRONOUS COUNTER

10. ASYNCHRONOUS COUNTER

11. 4 BIT BINARY ADDER AND SUBTRACTOR

12. BCD ADDER


2/38

ADDERS

AIM:

To Design and construct Half and Full Adder and to verify its truth table.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7432

3. IC 74084. IC 7404

5. IC 7486

6. Connecting wires.

PROCEDURE:

1. The connections are made as per the circuit diagram.

2. Give the logical inputs as per the truth table.

3. The corresponding output is verified with their truth table.


3/38

TRUTH TABLE FOR HALF ADDER:

INPUT OUTPUT

A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1

1

2

3

1

2

3

SUMY

X

IC7408

IC7486

CARRY

HALF ADDER


4/38

1

2

3 4

5

6

1

2

3

4

5

6

1

2

3

Y

X

FULL ADDER

Z

CARRY

SUM

IC7486

IC7432IC7408

IC7408

IC7486

TRUTH TABLE FOR FULL ADDER:

INPUT OUTPUT

A B C S C

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 11 1 1 1 1

RESULT:

Thus the Adder circuits are verified with their truth table.


5/38

SUBTRACTORS

AIM:

To Design and Construct Half and Full Subtractor and verify its truth table.

APPARATUS REQUIRED:

1. IC trainer kit.2. IC 7432

3. IC 74084. IC 7404

5. IC 7486


PROCEDURE:

1. The connections are made as per the circuit diagram.2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.


6/38

1

2

3

1

2

3

1 2

YX

BORROW

DIFFERENCE

HALF SUBTRACTOR

IC7404 IC7408

IC7486

TRUTH TABLE FOR HALF SUBTRACTOR:

INPUT OUTPUT

A B D B

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0


7/38

TRUTH TABLE FOR FULL SUBTRACTOR:

INPUT OUTPUT

A B C D B

0 0 0 0 0

0 0 1 1 10 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

1

2

3 4

5

6

1 2

3 4

1

2

3

4

5

6

1

2

3

XY

Z

FULL SUBTRACTOR

BORROW

DIFFEREN

IC7408

IC7404IC7408

IC7486IC7486

IC7432IC7404

RESULT:

Thus the Subtractor circuits are verified with their truth table.


8/38

CODE CONVERTERS

BINARY CODE TO GRAY CODE

AIM:

To Design and Implement BINARY TO GRAY & GRAY TO BINARY usinglogic gates.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 74863. Connecting wires

PROCEDURE:


2. Give the logical inputs as per the truth table.3. The corresponding output is verified with their truth table.


9/38

BINARY TO GRAY CODE:

INPUT OUTPUT

A B C D W X Y Z

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0

1 1 0 1 1 0 1 1

1

2

3

4

5

6

9

1 0

8

B2 B1 B0

G

G

G

G

B3

IC7486

IC7486

BINARY TO GRAY CODE

CODE CONVERTER

IC7486

GRAY TO BINARY CODE:


10/38

INPUT OUTPUT

W X Y Z A B C D

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1

1

23

4

56

9

1

0 8

1 2

1

3 1 1

1

23

4

56

GRAY TO BINARY CODE

B2

B1

B0

G0G1G2G3

B3

IC7486

IC7486IC7486

IC7486

IC7486

IC7486

RESULT:

Thus the Code Converters were designed and implemented.

BCD TO EXCESS 3 CODE AND VICE VERSA


11/38

AIM:

To Design and Implement BCD TO EXCESS 3 & EXCESS TO BCD using logic

gates.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7486

3. Connecting wires

PROCEDURE:




TRUTH TABLE:


12/38

BCD TO EXCESS 3 CODES:

INPUT OUTPUT

B3 B2 B1 B0 E3 E2 E1 E00 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 11 0 0 1 1 1 0 0

3

4

5

6

9

8

1

23 1 2

1

1 22

1 3

1

23

4

56 1

2

3

4

5

6 1

23

IC7411IC7432

IC7404

IC7404

IC7404

IC7404

IC7432

IC7408

IC7432IC7408

IC7486

B1B2B3 B0

BCD TO EXCESS-3 CODE

EXCESS 3 TO BCD CODE:


13/38

INPUT OUTPUT

E3 E2 E1 E0 B3 B2 B1 B0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 00 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

3

4

5

6

9

8

1

2

3

1

2

3

1

1 22

1 3

3

64

5

1

2

3

4

5

6

1

2

3

1

1 22

1 3

1

2

3

B0

E0E1E2E3

EXCESS-3 TO BCD CODE

B3

B2

B1

IC7404

IC7404

IC7404

IC7408

IC7486

IC7432

IC7432

IC7432

IC7411

IC7411

IC7411

IC7408

RESULT:

Thus the Code Converters were designed and implemented.

MAGNITUDE COMPARATOR


14/38

AIM:

To Design and Implement 2 bit, 4 bit Magnitude Comparator using logic gates and MSI

devices.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7432

3. IC 7408

4. IC 74045. IC 7486

6. IC 74857. Connecting wires.

PROCEDURE:



TRUTH TABLE:

2 BIT MAGNITUDE COMPARATOR


15/38

INPUT OUTPUT

A0 A1 B0 B1 A>B A=B A


16/38

COMPARING INPUTS CASCADING

INPUTS

OUTPUT

A3B3 A2B2 A1B1 A0B0 A>B A=B AB A=B A>B

A3>B3 X X X X X X 1 0 0A3B2 X X X X X 1 0 0

A3=B3 A2B1 X X X X 1 0 0

A3=B3 A2=B2 A1B0 X X X 1 0 0

A3=B3 A2=B2 A1=B1 A0

B

_

IN

4

A

B

5

A2

A3

+5V

4 BIT MAGNITUDE COMPARATOR

A1

A0

B0

B3

B2

B1

IC7485

OUTPUT R

RESULT:

Thus the Magnitude Comparator circuit are designed and implemented.


17/38

MULTIPLEXER AND DEMULTIPLEXER

AIM:

To Design and Implement Multiplexer, DEMultiplexer using logic gates and MSI devices.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7432

3. IC 74084. IC 7404

5. IC 74151


PROCEDURE:




18/38

TRUTH TABLE:

MULTIPLEXER

INPUT OUTPUT

S0 S1 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3


19/38

1

2

3

4

1

1 22

1 3

3

64

5

9

81 0

1 1

1

1 22

1 3

1

2

3

4

5

6

9

1 0

8

S0S1

IC7411

IC7404

IC7404

Y

D3

D2

D1

D0

IC7432

IC7432

IC7432

IC7411

IC7411

IC7411

MULTIPLEXER

TRUTH TABLE:

DEMULTIPLEXER

INPUT OUTPUT

D A B D0 D1 D2 D3

1 0 0 1 0 0 0

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1


20/38

1

2

3

4

9

81 0

1 1

3

64

5

9

81 0

1 1

1

1 22

1 3

IC7411

S1 S0

IC7404

IC7404

D2

D3

D0

D1

IC7411

IC7411

IC7411

DEMULTIPLEXER

Y3

Y2

Y1

Y0

RESULT:

Thus the Multiplexer circuit is designed and implemented.

9 BIT PARITY GENERATOR / CHECKER

AIM:

To Design and Implement Parity Generator/Checker using IC 74180.

APPARATUS REQUIRED:


21/38

1. IC trainer kit.

2. IC 74180

3. Connecting wires

PROCEDURE:




TRUTH TABLE

PARITY CHECKER

INPUTS

OUTPUTS

Number

of Xo

X7

EVE

N

ODD EVE

N

ODD

EVEN 1 0 1 0


22/38

ODD 1 0 0 1

EVEN 0 1 1 0

ODD 0 1 1 0

X 1 1 0 0

X 0 0 1 1

PARITY GENERATOR:

PARITY OF

INPUTS

CASCADING

INPUT

PARITY

OF X0-X7

PARITY

OF X0-

X7

X0 X7 EVEN ODD EVEN ODD

ODD 1 0 ODD EVEN

EVEN 1 0 ODD EVENODD 0 1 EVEN ODD

EVEN 0 1 EVEN ODD


23/38

A8

B9

C1 0

D1 1

E1 2

F1 3

G1

H2

O D D _ I N4 E V E N _ I N3

O D D _ O U T6

E V E N _ O U T5

A8

B9

C1 0

D1 1

E1 2

F1 3

G1

H2

O D D _ I N4 E V E N _ I N3

O D D _ O U T6

E V E N _ O U T5

EVEN INODD IN

ODD OUT

ODD INEVEN IN

X3X2X1X0

X0 - X7

ODD OUT

EVEN OUT

EVEN OUT

X7X6X5X4

X0

X3X2X1

X5X4

X7X6

9 BIT PARITY CHECKER

9 BIT PARITY GENERATOR

9 BIT PARITY CHECKER / GENERATOR

RESULT:

Thus the 9 bit Parity Generator/ Checker circuit are designed and implemented.


24/38

ENCODER AND DECODER

AIM:

To Design and Implement encoder and decoder using logic gates .

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7432

3. IC 7408


PROCEDURE:





25/38

TRUTH TABLE:

ENCODER

INPUT OUTPUT

A0 A1 A2 A3 A4 A5 A6 A7 D0 D1

1 0 0 0 0 0 0 0 0 0

0 1 0 0 0 0 0 0 0 0

0 0 1 0 0 0 0 0 0 1

0 0 0 1 0 0 0 0 0 1

0 0 0 0 1 0 0 0 1 0

0 0 0 0 0 1 0 0 1 0

0 0 0 0 0 0 1 0 1 1

0 0 0 0 0 0 0 1 1 1

1

2

3

4

5

6

9

1

0 8

1 2

1

3

1 1

1

2

3

4

5

6

9

1

0 8

1 2

1

3 1 1

1

2

3

A3A2A1A0 A7A6A5A4

IC7432

IC7432

IC7432

IC7432

D

D

D

ENCODER (OCTAL TO BINARY)

IC7432

IC7432

IC7432

IC7432

IC7432


26/38

TRUTH TABLE:

DECODER

INPUT OUTPUT

I0 I1 I2 A0 A1 A2 A3 A4 A5 A6 A7

0 0 0 1 0 0 0 0 0 0 00 0 1 0 1 0 0 0 0 0 0

0 1 0 0 0 1 0 0 0 0 0

0 1 1 0 0 0 1 0 0 0 0

1 0 0 0 0 0 0 1 0 0 0

1 0 1 0 0 0 0 0 1 0 0

1 1 0 0 0 0 0 0 0 1 0

1 1 1 0 0 0 0 0 0 0 1

1

2

3

4

5

6

I2I1I0

1

1 22

1 3

3

64

5

9

81 0

1 1

1

1 22

1 3

3

64

5

9

81 0

1 1

1

1 22

1 3

3

64

5

A6

A5

A4

A3

A2

A1

A0

IC7404

IC7404

IC7404

A7

IC7411

IC7411

IC7411

IC7411

DECODER (BINARY TO OCTAL)

IC7411

IC7411

IC7411

IC7411

RESULT:

Thus the encoder and decoder circuit is designed and implemented.


27/38

SHIFT REGISTERS

AIM:

To Design a 4bit Shift Register using flip-flops.

(1). Serial In Serial Out

(2). Serial In Parallel Out(3). Parallel In Parallel Out.

APPARATUS REQUIRED:


3. Connecting wires

PROCEDURE:




28/38

SERIAL IN SERIAL OUT:

T i t l e

S i z e D o c u m e n t N u m b e r R e v

D a t e : S h e e t o f

< D o c > < R e v C o d e >

< T i t l e >

A

1 1F r i d a y , S e p t e m b e r 2 1 , 2 0 0 7

C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

D a t a I n S e r i a l O u t

V c c

CLK DATA QD

0 1 0

1 1 0

2 0 0

3 0 04 0 1


29/38

SERIAL IN PARALLEL OUT:

T i t l e



< D o c > < R e v C o d e >

< T i t l e >

A


T i t l e



< D o c > < R e v C o d e >

< T i t l e >

A


C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

D a t a I n

V c c

Q DQ CQ B

Q A

CLK DATA QA QB QC QD

0 1 0 0 0 0

1 1 1 0 0 0

2 0 0 1 0 0

3 0 0 0 1 0

4 0 0 0 0 1

PARALLEL IN PARALLEL OUT:


30/38

D 1 D 2

T i t l e



< D o c > < R e v C o d e >

< T i t l e >

A


T i t l e



< D o c > < R e v C o d e >

< T i t l e >

A


T i t l e



< D o c > < R e v C o d e >

< T i t l e >

A


C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

C L K3

C

L

R

1

D2

P

R

E

4

Q5

Q6

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E

1

0

Q9

Q8

7 4 7 4

V c c

Q B

Q A

Q DQ C

D 4D 4

D 3

CLOCK D1 D2 D3 D4 QA QB QC QD

0 1 1 0 0 0 0 0 0

1 1 1 0 0 1 1 0 0

RESULT:

Thus the Shift Registers circuits are designed and verified with their truth table.

SYNCHRONOUS COUNTER

AIM:


31/38

To Design and Implement 3-bit Synchronous counter.

APPARATUS REQUIRED:


3. IC 7408

4. Connecting wires

PROCEDURE:

1. The connections are made as per the circuit diagram.2. Give the logical inputs as per the truth table.



32/38

P

R

E

2

J4

C L K1

K1 6

C

L

R

3

Q1 5

Q1 4

P

R

E

7

J9

C L K6

K1 2

C

L

R

8

Q1 1

Q1 0

P

R

E

2

J4

C L K1

K1 6

C

L

R

3

Q1 5

Q1 4

1

2

3

CLOCK

PRESET

CLEAR

IC7476IC7476IC7476

IC7408

A0A1A2

DATA IN

SYNCHRONOUS COUNTER

TRUTH TABLE:

CLK QA QB QC

0 0 0 0

1 0 0 1

2 0 1 0

3 0 1 1

4 1 0 0

5 1 0 1

6 1 1 0

7 1 1 1

RESULT:

Thus the Synchronous Counter circuits are designed and verified with their truth

table.


33/38

ASYNCHRONOUS COUNTER

AIM:

To Design and Implement 4-bit ASynchronous counter.

APPARATUS REQUIRED:

1. IC trainer kit.


PROCEDURE:




34/38

C L K3

C

L

R

1

D2

P

R

E4

Q5

Q6

U 1 A

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E1

0

Q9

Q8

U 1 B

7 4 7 4

C L K3

C

L

R

1

D2

P

R

E4

Q5

Q6

U 2 A

7 4 7 4

C L K1 1

C

L

R

1

3

D1 2

P

R

E1

0

Q9

Q8

U 2 B

7 4 7 4

A1

A2

A3

PRESET

CLEAR

CLOCK

ASYNCHRONOUS COUNTER

A0

TRUTH TABLE:

CLK QA QB QC QD

0 0 0 0 0

1 1 1 1 1

2 1 1 1 0

3 1 1 0 1

4 1 1 0 0

5 1 0 1 1

6 1 0 1 0

7 1 0 0 1

8 1 0 0 0

9 0 1 1 1

10 0 1 1 0

11 0 1 0 1

12 0 1 0 0

13 0 0 1 1

14 0 0 1 0

15 0 0 0 1

RESULT:

Thus the Asynchronous Counter circuits are designed and verified with theirtruth table.


35/38

4 BIT BINARY ADDER / SUBTRACTOR

AIM:

To design and implement 4 bit parallel binary adder and Subtractor.

APPARATUS REQUIRED:



PROCEDURE:


2. Apply the binary inputs for A and B.3. Observe the output for the corresponding input .


36/38

A

4

1

A

3

3

A

2

8

A

1

1

0

B

4

1

6

B

3

4

B

2

7

B

1

1

1

C

0

1

3

C

4

1

4

S

U

M

4

1

5

S

U

M

3

2

S

U

M

2

6

S

U

M

1

9

1

2

3

4

5

6

9

1 0

8

1

2

1 3

1 1

A3

GND/VCC

B2

B1

B0

A0A3

A1

A2

B3

S0 CoutS3S2S1

Cin

IC7486

IC7486

IC7486

IC7486

4 BIT BINARY ADDER/SUBTRACTOR

RESULT:

Thus the 4 bit binary adder and Subtractor circuit was designed andimplemented.


37/38

BCD ADDER

AIM:

To design and implement BCD adder.

APPARATUS REQUIRED:

1. IC trainer kit.

2. IC 7483

3. IC 7408

4. IC 7432

5. Connecting wires

PROCEDURE:


2. Apply the binary inputs for X and Y.3. Observe the output for the corresponding input .


38/38

A

4

1

A

3

3

A

2

8

A

1

1

0

B

4

1

6

B

3

4

B

2

7

B

1

1

1

C

0

1

3

C

4

1

4

S

U

M

4

1

5

S

U

M

3

2

S

U

M

2

6

S

U

M

1

9

A

4

1

A

3

3

A

2

8

A

1

1

0

B

4

1

6

B

3

4

B

2

7

B

1

1

1

C

0

1

3

C

4

1

4

S

U

M

4

1

5

S

U

M

3

2

S

U

M

2

6

S

U

M

1

9

0

00

1

2

3

1

23

45

6

Y1

Y0

X0

X1

X2

X3

Y3

Y2

Cout

S2S1S0 S3

IC 7432

IC 7432

IC 7408

BCD ADDER

RESULT:

Thus the BCD adder circuit was designed and implemented

ec 1258-digital electronics lab

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