eb-gs2971...closed sd. eb-gs2971 evaluation board user guide 52169 - 1 november 2011 8 of 22...

EB-GS2971

Evaluation Board User Guide

1 of 22

Proprietary & Confidential

EB-GS2971Evaluation Board User Guide52169 - 1 November 2011

www.gennum.com

www.gennum.com

Contents

Overview ..............................................................................................................................................................3

1. Evaluation Board User Guide ....................................................................................................................4

1.1 Power ....................................................................................................................................................5

1.2 SDI Input (J4) ......................................................................................................................................6

1.3 Switch Settings (SW2) ......................................................................................................................6

1.4 Outputs ................................................................................................................................................7

1.4.1 SDI Loop-Through (J5).........................................................................................................7

1.4.2 Audio Output (J23 and BNCs J19-J22) ...........................................................................7

1.4.3 Parallel Video Output (J16 and J17)................................................................................7

1.5 JTAG/GSPI Header (JP1) .................................................................................................................8

1.6 Lock and Data Error Status ............................................................................................................8

1.7 Modes of Operation .........................................................................................................................8

2. Schematics .......................................................................................................................................................9

2.1 Top Level Schematic ........................................................................................................................9

2.2 Cable Driver Schematic ............................................................................................................... 10

2.3 GS2971 Schematic ......................................................................................................................... 11

2.4 Power and AES Drivers ............................................................................................................... 12

3. Board Layout................................................................................................................................................ 13

4. Bill of Materials............................................................................................................................................ 19

Version ECR Date Changes and / or Modifications

1 157183 November 2011 Updated Figure 3-2, Figure 3-3, Figure 3-4 and Figure 3-5 in the Board Layout section.

0 151494 March 2009 New document.


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OverviewTogether with the EB-GS2971 Evaluation Board, this document serves as a guide for evaluating the GS2971; a Gennum 3Gb/s, HD, SD SDI Receiver, with integrated equalizer. This document contains four main sections:

1. Evaluation Board User Guide.

2. Evaluation Board Schematics.

3. Evaluation Board Layout.

4. Evaluation Board Bill of Materials

The figure below shows a block diagram of the features and the functions of the EB-GS2971.

The board includes a power supply, a 3G-SDI input, a 3G-SDI loop-through output, a GS2971 Receiver, a parallel video output connector, an audio output with four BNCs for AES audio, a four-pin header for serial audio, a JTAG/GSPI header, a 27MHz crystal, a DIP switch and some status indication LEDs.

The GS2971 will automatically detect the input signal as SD-SDI, HD-SDI or 3G-SDI. The input format may also be configured to DVB-ASI or Data-Through mode manually, through a DIP switch. The deserialized video is available on the parallel output connector (J16). The extracted audio is available as serial audio or AES on an audio header (J23), or as buffered AES only audio on the BNC connectors (J19-J22). A serial digital loop-through output is also available.

The EB-GS2971 also provides a JTAG interface and access to the GS2971’s internal registers via GSPI. A GSPI dongle is included in the kit, to communicate with the GS2971 through a USB connection.The GSPI dongle has the provision to control and monitor an additional EB2972 board connected to the EB-GS2971.

Block Diagram of the EB-GS2971

GS2971(Receiver)

AudioO/P

ParallelVideoO/P

3G-SDILoop-Through

3G-SDI I/P

8-ch Audio

20-bit Video

FVH

DIP Switch

LEDs(Lock; Data Error)

Audio Clocks

CD(GS2978)

Power

AES

PCLK

AudioHeader

GSPI/JTAGHeader

GSPI/5V


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1. Evaluation Board User Guide

Figure 1-1 shows the inputs, outputs and power connections for the EB-GS2971.

Figure 1-1: GS2971 Evaluation Board (EB-GS2971)

SDI Input(J4)

SDI Loop-Through(J5)

CD O/P Jumper(JP4)

AES Audio Outputs (J19 - J 22)

Parallel Video Output(J16)

GSPI(J18)

H, V & F Timing Signals(J17)

1.8V/3.3V Jumper(JP7)

Power(J24)

Power(J100)

Power Selection Switch(SW100)

DIP Switch(SW2)

Serial Audio Output(J23)

Power StatusLED (D11)Lock Status

Indicator(U12)

Data ErrorStatus

Indicator(U13)


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1.1 PowerThe EB-GS2971 requires a single +5V DC power supply. The board can be powered through either J24 or J100. Additionally, the board can powered through J18 from an EB-GS2972 or FPGA board.

Figure 1-2: Power Supply

Switch SW100 allows the user to select three different voltages: 5V Ext, 5V EB and 3.3V FPGA. It is important to note that if you are interfacing with an FPGA, you must select 3.3V FPGA.

NOTE 1: If you have accidently selected 3.3V FPGA and connect to a EB-GS2972 Serializer board, protection* will turn on.

Figure 1-3: Power Selection Switch

*The EB-GS2971 has features to protect the GS2971. A fuse (F101) will trip when the Zener Diodes (D100, D101) turn on.

NOTE 2: If the fuse trips, it will recover in approximately 1 hour, with a resistance of 1Ω.

Figure 1-4: Power Protection

LED (D11) indicates the power on/off state of the board.

Through the use of jumper JP7, the GS2971 I/O voltage can be selected as either 1.8V or 3.3V.

If the EB-GS2971 and the EB-GS2972 are connected together, one supply will power both boards. Therefore, the +5V DC power is only required on either the EB-GS2971 or the EB-GS2972.

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C103

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1.2 SDI Input (J4)The EB-GS2971 includes a single SDI input.

1.3 Switch Settings (SW2)A DIP switch (SW2) is populated on the EB-GS2971, with each bit labelled on the silk-screen. This switch is used to set the operating modes of the GS2971. The signal can be set HIGH by placing the switch to the ‘1’ position (Closed).

NOTE: Some signals are active LOW, so you will need to switch the bit ‘OFF’ to activate the signal.

Refer to Table 1-1 below for definitions of each bit.

Table 1-1: SW2 Settings

Bit Name Description

TIM861 Connected to the GS2971 TIM_861 pin. Used to select CEA-861 timing mode.

When TIM_861 is HIGH, the device outputs CEA 861 timing signals (HSYNC/VSYNC/DE) instead of H:V:F digital timing signals.

SMPTE_BYPASSb Connected to the GS2971 SMPTE_BYPASS pin. Used to enable/disable all forms of encoding/decoding, descrambling, audio and ANC data detection and extraction and error detection and correction.

When the AUTO/MAN bit in the Host Interface register is HIGH (Default), this pin is an OUTPUT. SMPTE_BYPASS is HIGH when the device locks to a SMPTE compliant input. SMPTE_BYPASS is LOW under all other conditions.

When the AUTO/MAN bit in the Host Interface register is LOW, this pin is an INPUT. No SMPTE scrambling takes place, and none of the I/O processing features of the device are available when SMPTE_BYPASS is set LOW.

When SMPTE_BYPASS is set HIGH, the device carries out SMPTE descrambling and I/O processing.

When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode.

DVB_ASI Connected to the GS2971 DVB_ASI pin. Used to enable/disable DVB-ASI data decoding in manual mode.

When the AUTO/MAN bit in the Host Interface is LOW, this pin is an input and when set HIGH the device will carry out DVB_ASI data extraction and processing. The SMPTE_BYPASS pin must be set LOW.

When SMPTE_BYPASS and DVB_ASI are both set LOW, the device operates in Data-Through mode.

When the AUTO/MAN bit in the Host Interface is HIGH (Default), DVB-ASI input is not supported.

AUDIO_EN/DISb Connected to the GS2971 AUDIO_EN/DIS pin. Enables or disables audio extraction.

IOPROC_EN/DISb Connected to the GS2971 IOPROC_EN/DIS pin. Used to enable or disable I/O processing features.

When IOPROC_EN/DIS is HIGH, the I/O processing features of the device are enabled. When IOPROC_EN/DIS is LOW, the I/O processing features of the device are disabled, and the latency of the device is LOW. Please refer to the Data Sheet for more information.

20BIT/10BITb Connected to the GS2971 20bit/10bit pin. Used to select the output bus width. (HIGH = 20bit, LOW = 10bit)

SDO_EN/DISb Connected to the GS2971 SDO_EN/DIS pin. Used to enable/disable the serial digital output stage.

When the SDO_EN/DIS is LOW, the serial digital output signals, SDO and SDO, remain static.

When connected to logic HIGH, the serial digital output signals, SDO and SDO, are enabled.

The SDO and SDO outputs will also be disabled when the RESET pin is LOW.

RC_BYPb Connected to the GS2971 RC_BYP pin. When this pin is LOW, the serial digital output is the buffered version of the input serial data.

When this pin is HIGH, the serial digital output is the reclocked version of the input serial data.


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1.4 Outputs

1.4.1 SDI Loop-Through (J5)

A relocked or non-relocked buffered version of the input stream is available on the serial loop-through output (J5). It is designed to be SMPTE compliant for voltage level, rise/fall time and return loss at three rates (SD, HD and 3G) using the compensation network. The GS2978 Cable Driver is necessary to guarantee return loss specification. The GS2978 should be set to SD or HD mode; use jumper JP4 to select the mode. See Table 1-2 below.

If the SDI loop-through is not required, disable the SDO through the SDO_EN/DIS DIP switch setting (SW2). Doing this will also disable the GS2978 Cable Driver.

1.4.2 Audio Output (J23 and BNCs J19-J22)

The extracted 8-channel audio, together with the Audio Master Clock generated by the GS2971, is available on a 10-pin header (J23).

For AES mode, AES-encoded CMOS-level signals are distributed through line drivers, and supplied to four BNC connectors (J19, J20, J21 and J22).

An audio output board can be connected to Serial Audio Output header (J23).

1.4.3 Parallel Video Output (J16 and J17)

Parallel video data with the PCLK is available on a 48-pin connector (J16) and timing signals H, V and F are connected to a 10-pin connector (J17). This is a standard Gennum parallel interface, compatible with all Gennum evaluation boards.

SW_EN Connected to the GS2971 SW_EN pin. Used to enable switch-line locking. Please refer to the Data Sheet for more information.

STANDBY Connected to the GS2971 STANDBY pin. When this pin is set HIGH, the device power is reduced, and placed into Standby mode.

Table 1-1: SW2 Settings (Continued)

Bit Name Description

Table 1-2: GS2978 Cable Driver format

JP4 Position Status

Open HD/3G

Closed SD


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1.5 JTAG/GSPI Header (JP1)The GS2971 contains a set of internal status and configuration registers. These registers are available to the host via the GS2971’s GSPI pins. Access to the applicable pins on the GS2971 is provided using the JTAG/GSPI header.

A GSPI dongle is provided for communication to the GSPI interface. If you have the EB-GS2971 and an EB-GS2972 connected together, only one GSPI dongle is required, and can be connected to either of the boards.

1.6 Lock and Data Error StatusLED U12 indicates the lock status of the GS2971, and LED U13 indicates data error. Both are bi-colour devices. See Table 1-3 below.

1.7 Modes of OperationThe GS2971 supports four distinct modes of operation that can be set through the DIP switch or by programming internal registers through the GSPI. These modes are: SMPTE mode, Data-Through mode, DVB-ASI mode and Standby mode.

The GS2971 can automatically detect the format of the incoming signal when AUTO/MAN = HIGH. If the format of the incoming signal is not recognized, the GS2971 defaults into SMPTE Bypass mode. Alternatively, the device may be forced into any of the four modes through the Host Interface (Address 024h).

In SMPTE mode, the GS2971 performs full SMPTE processing, and features a number of signal integrity checks and measurement capabilities.

In DVB-ASI mode, 8b/10b decoding is applied to the received data stream.

In SMPTE Bypass mode, all forms of SMPTE and DVB-ASI decoding are disabled, and the device can be used as a simple serial-to-parallel converter without incurring the latency penalties associated with SMPTE or DVB-ASI mode.

The device can also operate in a lower power Standby mode. In this mode, no signal is generated at the output.

The DIP switch (SW2) corresponds directly to pins on the GS2971. Refer to the GS2971 Data Sheet for a more detailed explanation of the modes of operation.

Table 1-3: Lock and Data Error Status

LED Green Red

U12 (Lock Status) Locked Unlocked

U13 (Data Error Status) No Error Detected Error Detected


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P

Clo

se t

o G

S297

1

123456789 10 11 12 13 14 15 16RN

274

2C16

3220

HV

F[2:

0]

VID

_DA

T_O

ut1

6

C10

147

0n

C10

0

470n

VID

_DA

T_O

ut1

+3.3

VA

Dat

a Er

ror

AU

DIO

_Ou

t [6

:0]

VID

_DA

T_O

ut1

5

Pin

_ct

rl[1

0:0]

VB

GA

1

LFA

2

LB_C

ON

TA

3

VCO_VDDA4

STA

T0A

5ST

AT1

A6

STA

T2B

5

STA

T3B

6

STA

T4C

5

STA

T5C

6

IO_VDDA7

PCLK

A8

DO

UT0

K8

DO

UT1

J8

DO

UT2

K9

DO

UT3

K10

DO

UT4

J9D

OU

T5J1

0D

OU

T6H

9D

OU

T7H

10D

OU

T8F9

DO

UT9

F10

DO

UT1

0E9

DO

UT1

1E1

0

DO

UT1

2C

8D

OU

T13

C10

DO

UT1

4C

9D

OU

T15

B10

DO

UT1

6B

9D

OU

T17

A10

DO

UT1

8A

9D

OU

T19

B8

A_VDDB1

PLL_VDDB2

A_T

EST

B3

VCO_GND B4

IO_GND B7

SDI

C1

A_GND C2

PLL_VDDC3

PLL_VDDC4

RES

ETC

7

SDI

D1

A_GND D2

A_GND D3

PLL_GND D4

CORE_GND D5

CORE_VDDD6

SW_E

ND

7

JTA

G/H

OST

D8

IO_GND D9

IO_VDDD10

SDI_VDDE1

A_GND E3

PLL_GND E4

CORE_GND E5

CORE_VDDE6

SDO

UT_

TDO

E7

SDIN

_TD

IE8

AG

C+

F1

RSV

F2

A_GND F3

PLL_GND F4

CORE_GND F5

CORE_VDDF6

CS_

TMS

F7SC

LK_T

CK

F8

AG

C-

G1

A_GND G2

RC

_BY

PG

3

CORE_GND G4

CORE_GND G5

CORE_VDDG6

SMPT

E_B

YPA

SSG

7

DV

B_A

SIG

8

IO_GND G9

IO_VDDG10

BUF_VDDH1BUF_GND H2

AU

DIO

_EN

/DIS

H3

WC

LKH

4

TIM

_861

H5

XTA

L_O

UT

H6

20B

IT/1

0BIT

H7

IOPR

OC

_EN

/DIS

H8

SDO

J1

SDO

_EN

/DIS

J2

AO

UT_

1/2

J3

AC

LKJ4

AO

UT_

5/6

J5

XTA

L2J6

IO_GND J7

SDO

K1

STA

ND

BY

K2

AO

UT_

3/4

K3

AM

CLK

K4

AO

UT_

7/8

K5

XTA

L1K

6

IO_VDDK7

SDI_GND E2U5

GS2

971

Clo

se t

o G

S297

1

Lock

VID

_DA

T_O

ut0

WC

LKA

UD

IO_O

ut

0R

3722

RA

CLK

AU

DIO

_Ou

t 1

R38

22R

+1.2

V

5. IO

_VD

D c

an b

e +3

.3V

, wh

ich

is s

up

plie

d b

y th

is b

oar

d t

hro

ug

h a

1-o

hm

jum

per

, or

dif

fere

nt

volt

age

sup

plie

d b

y th

e o

utp

ut

bo

ard

co

nn

ecte

d t

o it

, in

wh

ich

cas

e th

e 1-

oh

m ju

mp

er s

hal

l be

rem

ove

d;

R24

22R

R25

22R

VID

_DA

T_O

ut1

4

10. A

nal

og

po

wer

an

d g

rou

nd

iso

lati

on

(re

fer

to P

CB la

you

t g

uid

e).

9. M

inim

um

of

3x t

race

wid

th s

pac

ing

fo

r D

OU

T10~

19, P

CLK

;

11. C

riti

tal 3

G s

ign

al la

you

t (r

efer

to

PCB

layo

ut

gu

ide)

;

SCLK

GSP

I1SD

ING

SPI2

SDO

UT

GSP

I3

CS0

GSP

I0Lo

ck

+3.3

VA

Dat

a Er

ror

C51

1u

R42

75R

L36n

2 R45 75

RR

4637

R4

C49

1u

A_G

ND

VID

_DA

T_O

ut1

3

VID

_DA

T_O

ut1

1

GS2

971

Pow

er D

ecou

plin

g &

Filt

erin

g

VID

_DA

T_O

ut1

2

VID

_DA

T_O

ut1

01

2

3JP

7

TP7

7. U

se B

NC

gro

un

d a

s th

e g

rou

nd

tes

t p

oin

ts;

VC

C_1

.8V

TP19

VID

_DA

T_O

ut9

+3.3

VA

GSP

I[3:

0]

PCLK

R18

22R

C26

1u

TP20

13. V

ia s

ize

test

po

ints

sh

ou

ld b

e as

clo

se a

s p

oss

ible

to

th

e p

ins;

AO

UT_

3/4

AU

DIO

_Ou

t 4

AO

UT_

1/2

AU

DIO

_Ou

t 5

VID

_DA

T_O

ut8

6. T

he

valu

e o

f th

e se

rial

res

isto

rs o

n v

ideo

ou

tpu

t p

ort

will

be

det

erm

ined

by

bo

ard

sig

nal

inte

gri

ty t

est;

R16

22R

R17

22R

R14

22R

FH

VF2

VH

VF1

HH

VF0

GN

D

C25

1u

TP8

Lock

GN

D

AO

UT_

7/8

AU

DIO

_Ou

t 2

AO

UT_

5/6

AU

DIO

_Ou

t 3

123456789 10 11 12 13 14 15 16RN

174

2C16

3220

VID

_DA

T_O

ut7

C31

1u

C34

10n

C17 10n

C27

10n

C16

10n

C41

47n

-470

n

C15

10n

R12 0R R10 0R

C30

10n

R2

0R

C14

10n

C29

10n

C8

10n

R91 0R

C24

10n

C33

10n

R11 0R

C13

10n C

35

10n

C12

10n

C32

10n

+1.2

VA

C28

10n

C11

10n

A_G

ND

A_G

ND

VC

C_3

.3V

GN

D

GN

D

VC

C_3

.3V

+1.2

V

GN

D

GN

D

+1.2

VA

+3.3

VA

IO_V

DD

+1.2

V

R20

22R

TIM

861

Pin

_ct

rl10

VID

_DA

T_O

ut6

LB_C

ON

T Se

ttin

gs:

VID

_DA

T_O

ut1

9

Dat

a Er

ror

R22

22R

SMPT

E_B

YPA

SSb

Pin

_ct

rl9

AM

CLK

AU

DIO

_Ou

t 6

3. P

ow

er c

on

sum

pti

on

:2.

DN

P (D

o N

ot

Pop

ula

te);

217

+1.2

V+3

.3V

75G

S297

0_1

No

tes:

Dev

ice

0G

S297

851

SDI

Inp

ut

C42

1u

1. T

his

bo

ard

is G

S296

0/1

com

pat

ible

;

217m

ATo

tal

191m

A

C10

1u

DV

B_A

SIPi

n _

ctrl

8

VID

_DA

T_O

ut5

SDO

SDO

SDO

SDO

2.4 Power and AES Drivers

Figure 2-4: Power and AES Drivers Schematics

GND

C70 0.1u

C95 0.1u

C8510n

C65 0.1u

C87

1u

5V

J24

5V Input

C92 0.1u

C39

33u

C40

22u

A3

B4

R 5

GND2

Vcc1

110R

U19

SN65LVDT2

C93 0.1u

R57

240R

A3

B4

R 5

GND2

Vcc1

110R

U20

SN65LVDT2

R9649.9K

A3

B4

R 5

GND2

Vcc1

110R

U18

SN65LVDT2

IN8

SHDN5

AGND4 PGND6

SENSE3OUT2

NC1

NC7

U4LT3021ES8-1.2

R61.15K

PWR

VCCA1

GND2

A3 B 4

DIR 5VCCB 6

SN74LVC1T45DRLR

U15

PWRGD_3V3

C58 0.1u

C86

22u

AES AUDIO OUT

C94 0.1u

C63 0.1u

R33.57K

C322u

VCC_5V

IN5

IN6

IN7

IN8

BIAS10

PG9

OUT1

OUT18OUT19OUT20

NC17

FB16

EN11

SS15

GN

D12

NC

13

NC

14

NC

2

NC

3

NC

4

Pad

U14

TPS74201_RGW

D11LNJ311G8PRA

A3

B4

R 5

GND2

Vcc1

110R

U17

SN65LVDT2

GND

GND

VCC_3.3V

GND

GND

GND

VCC_3.3V

GND

GND GND

GND

VCC_3.3V

GND GND

GND

VCC_3.3V

GND

VCC_5V_In

GNDGND

GND

VCC_3.3V_regVCC_5V

VCC_3.3V +1.2V

GNDGND

VCC_5V

GND

VCC_3.3V_reg

GND

D101

3.6V

VCC_MB

R100240R

3.3V

MBD102

LNJ311G8PRA

GND

C84

0.1u

C88

33u

Heat sinkon copper

IN8

SHDN5

AGND4 PGND6

SENSE3OUT2

NC1

NC7

U22LT3021ES8-1.8

500mAVCC_3.3V VCC_1.8V

C90

1u

GNDGND

D100

3.6V

VCC_3.3V

VCC_3.3V

3

21

J100

PJ-202AH

1

2

3

4

5

6

7

8

SW100

SW SLIDE-DP3TF101

0603L035

C102

470u

VCC_3.3V

VCC_MB

TP2

VCC_3.3V_reg

C36EEV-FK1C221XP

VCC_3.3V

VCC_MB_F

VCC_MB_F

AOUT_1/2VCC_5V_In

PWRGD_3V3

AOUT_3/4

VCC_5V

AOUT_5/6

VCC_MB

VCC_LED

AOUT_7/8

5V5V Ext5V EB

GND

3.3V FPGA

AES Ch 1_2

AES Ch 3_4

AES Ch 5_6

Heat sinkon copper

AES Ch 7_8

POWER SUPPLIES

500mA

C103

22u

+1.2V

AOUT_3/4

AOUT_5/6

AOUT_7/8

AOUT_1/2


12 of 22


3. Board Layout

Figure 3-1: Layer 1 (Top Layer)


13 of 22


Figure 3-2: Layer 2 (Ground)


14 of 22


Figure 3-3: Layer 3 (Power)


15 of 22


Figure 3-4: Layer 4 (Signal 1)


16 of 22


Figure 3-5: Layer 5 (Signal 2)


17 of 22


Figure 3-6: Layer 6 (Bottom Layer)


18 of 22


4. Bill of Materials

Table 4-1: Bill of Materials

Quantity Reference Part

5 C3, C18, C40, C86, C103 22μF Capacitor (805)

5 C8, C20, C23, C24, C30 10nF Capacitor (0603)

9 C9, C10, C21, C22, C25, C26, C31, C87, C90 1μF Capacitor (0603)

18 C11, C12, C13, C14, C15, C16, C17, C27, C28, C29, C32, C33, C34, C35, C47, C48, C57, C85

10nF Capacitor (0402)

1 C36 EEV-FK1C221XP (CT-CAP/PANA_FK_D8)

2 C39, C88 33μF Capacitor (1210)

1 C41 47nF-470nF Capacitor (0402)

3 C42, C49, C51 1μF Capacitor (0402)

2 C43, C44 16pF Capacitor (0603)

2 C50, C52 4.7μF Capacitor (0603)

10 C58, C63, C65, C70, C84, C91, C92, C93, C94, C95

0.1μF Capacitor (0402)

2 D11, D102 LNJ311G8PRA (1206_LED)

2 D100, D101 CT-SMB_DO214AA

1 F101 0603L035 (CT-0603)

1 JP1 TSW-105-07-L-D (BLKCON .100/VH/TM2OE/W.200/10)

1 JP4 JUMPER (HEADER_.100_1X2)

1 JP7 BLKCON .100/VH/TM1SQ/W.100/3

2 J4, J5 UCBBJE20-1 (BNC_EDGEMNT _GHZ-POUR-2LYR-ER3.8)

1 J16 TMMH-124-01-F-D-RA-ES (HEADER2MM_48_2X24)

2 J17, J18 TMMH-105-01-F-D-RA (HEADER2MM_10_2X5)

4 J19, J20, J21, J22 BCJ-FPLV01 (BNC _EDGEMNT_RIGHT_ANGLE)

1 J23 TSW-105-07-L-D (HEADER2MM_10_2X5)

1 J24 5V Input (CON_WEID5MM_2_PWR)


19 of 22


1 L3 6.2nH Inductor (0402)

1 L4 5.6nH Inductor (0402)

2 RN1, RN2 742C163220 (CT-742_16)

1 RN3 742C163103 (CT-742_16)

7 R2, R9, R10, R11, R12, R91, R94 0Ω Resistor (0603)

1 R3 3.57kΩ Resistor (0603)

2 R6, R84 1.15kΩ Resistor (0603)

1 R7 105Ω Resistor (0603)

10 R14, R16, R17, R18, R20, R22, R24, R25, R37, R38

22Ω Resistor (0402)

7 R35, R36, R87, R88, R89, R90, R93 10kΩ Resistor (0402)

1 R40 750Ω Resistor (0402)

8 R41, R42, R43, R44, R45, R47, R85, R86 75Ω Resistor (0402)

1 R46 37.4Ω Resistor (0402)

2 R48, R49 49.9Ω Resistor (0402)

2 R57, R100 240Ω Resistor (0603)

1 R92 10kΩ Resistor (0603)

1 R96 49.9kΩ Resistor (0603)

1 SW2 Switch, DIP-10/SM (Through Hole)

1 SW100 Switch, SLIDE-DP3T

1 S1 B3S-1002P

6 TP2, TP7, TP8, TP18, TP19, TP20 Via (CT-TP)

1 U1 MAX6823V (SOT23-5)

1 U4 MCP1725-1202E/SN (CT-SOIC_8)

1 U5 GS2971 Receiver (CT-BGA_100_11X11_1.00)

1 U7 GS2978 Cable Driver (CT-QFN_4MM_16/WSHLD)

2 U12, U13 HSMF-C165

1 U14 TPS74201_RGW (20-QFN)

1 U15 SN74LVC1T45DBVR (SOT23-6)

1 U16 FXL4TD245 (DQFN-MLP016E)

4 U17, U18, U19, U20 SN65LVDT2 (SOT23-5)

Table 4-1: Bill of Materials (Continued)



20 of 22


1 U22 TPS77518D (CT-SOIC_8)

1 U24 FXL2TD245 (MAC010A)

1 Y1 CS10-27.000M (SM/XTAL_6.0X3.5/2)

Table 4-1: Bill of Materials (Continued)



21 of 22


CANADASuite 320, 3553 31st St. N.W. Calgary, Alberta T2L 2K7 Canada

Phone: +1 (403) 284-2672 Fax: +1 (905) 632-2055 415 Legget Drive, Suite 200 Kanata, Ontario K2K 2B2 Canada

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Phone: +49 89 309040 290 Fax: +49 89 309040 293 E-mail: [email protected]

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Phone: +91 (674) 65304815 Fax: +91 (674) 259-5733

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Phone: +81 (03) 3349-5501 Fax: +81 (03) 3349-5505 E-mail: [email protected]

Web Site: http://www.gennum.co.jp

MEXICOVenustiano Carranza 122 Int. 1 Centro, Aguascalientes Mexico CP 20000

Phone: +1 (416) 848-0328

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NORTH AMERICA EASTERN REGION4281 Harvester Road Burlington, Ontario L7L 5M4 Canada


TAIWAN6F-4, No.51, Sec.2, Keelung Rd. Sinyi District, Taipei City 11502 Taiwan R.O.C.

Phone: (886) 2-8732-8879 Fax: (886) 2-8732-8870 E-mail: [email protected]

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Phone: +44 1279 714170 Fax: +44 1279 714171 2, West Point Court, Great Park Road Bradley Stoke, Bristol BS32 4PY Great Britain

Phone: +44 1454 462200 Fax: +44 1454 462201

SNOWBUSH IP - A DIVISION OF GENNUM439 University Ave. Suite 1700 Toronto, Ontario M5G 1Y8 Canada


Web Site: http://www.snowbush.com

DOCUMENT IDENTIFICATIONUSER GUIDEInformation relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Gennum assumes no liability for any errors in this document, or for the application or design described herein. Gennum reserves the right to make changes to the product or this document at any time without notice.


22 of 2222


Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement.

All other trademarks mentioned are the properties of their respective owners.

GENNUM and the Gennum logo are registered trademarks of Gennum Corporation.

© Copyright 2009 Gennum Corporation. All rights reserved.

www.gennum.com

GENNUM CORPORATE HEADQUARTERS4281 Harvester Road, Burlington, Ontario L7L 5M4 Canada

Phone: +1 (905) 632-2996 Fax: +1 (905) 632-2055

E-mail: [email protected] www.gennum.com

CAUTIONELECTROSTATIC SENSITIVE DEVICES

DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION

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