early output logic with anti-tokens
DESCRIPTION
Early Output Logic with Anti-Tokens. Charlie Brej, Jim Garside APT Group Manchester University. Outline. Asynchronous Logic DIMS (Delay Insensitive Minterm Synthesis) Early Output Logic Guarding Anti-Tokens Collisions Conclusions. Asynchronous Latch. Ri. Ro. Latch. Ai. Ao. Req. - PowerPoint PPT PresentationTRANSCRIPT
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Early Output Logic with Anti-Tokens
Charlie Brej, Jim GarsideAPT Group
Manchester University
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Outline
Asynchronous LogicDIMS (Delay Insensitive Minterm
Synthesis)Early Output Logic
GuardingAnti-Tokens
CollisionsConclusions
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Asynchronous Latch
Ri Ro
AoAi
Latch
Req
Ack
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Asynchronous Pipeline
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Asynchronous Pipeline Stall
Wait!
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Dual-Rail Latch
Dual-Rail 00 = ‘NULL’ 01 = 0 10 = 1 11 = Illegal
Return to ‘NULL’
Ri_0 Ro_0
AoAi
LatchRi_1 Ro_1
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DIMS Logic
0
10
C
C
C
C
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DIMS vs Early Output Logic
C
C
C
C
Size:48 transistors
Delay:4 inversions
Size:12 transistors
Delay:2 inversions
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Early Output Logic
0
1
0
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Guarding
Problem: Inputs
Late Unnecessary
Acknowledge before ready
Solution: Validity signal (Vo)
Ri Ro
AoAi
Latch Vo
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Early Output Guarding
00
1 C
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Anti-Tokens
Don’t:Stall entire stage until late input
arrives
Do:Stall the latch instead
Early ‘Validity’Acknowledge before Data
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Anti-Token Generation
00
CA
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Anti-Token Propagation
AA
A C
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Token Pass
T T T
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Anti-Token Pass
A A A
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Token Anti-Token collision
T T A
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Token Anti-Token collision 2
T ? A
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Dual-Purpose Signals
Arbiter freeReq:
Token RequestAnti-Token
AcknowledgeAck:
Anti-Token RequestToken Acknowledge
Req
Ack
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ConclusionsNew, fine-grain, asynchronous
pipelineFaster than DIMS (2x)Smaller than DIMS (4x)Lower power than DIMSSome speed advantages over
synchronous designsCounterflow - no arbitrationRequires some timing assumptions
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Timing Hazard example
A0
A
0
C