e-cpu-800 | deditec manual · 2.7.2. can interface the e-cpu-800 module provides one (2nd is...

Hardware description

Juli

E-CPU-800

2012

INDEX

Index | 2Seite

1. Introduction 5

1.1. General remarks 5

1.2. Customer satisfaction 5

1.3. Customer response 5

2. Hardware description 7

2.1. Technical data 8

2.2. Board Overview 9

2.3. Mechanics 10

2.4. CPU 10

2.5. SDRAM 10

2.6. Flash Memory 11

112.6.1. NAND Flash 112.6.2. Serial Flash (optional)

2.7. Interfaces 11

112.7.1. Ethernet 122.7.1.1. Ethernet PHY

132.7.2. CAN Interface 142.7.3. USB Host Port 152.7.4. USB Device Port 162.7.5. Universal Synchronous Asynchronous Receiver Transmitter (USART) 182.7.6. Debug Port (DBG) 192.7.7. Serial Synchronous Controller (SSC) 202.7.8. A/D-Converter 10Bit / 4 channel 212.7.9. JTAG (Join Test Action Group) 222.7.10. MCI (MultiMedia Card Interface) 232.7.11. TWI (Two-wire Interface) 242.7.12. Error Corrected Code (ECC) Controller 242.7.13. SPI (Serial Peripheral Interface) 262.7.14. Timer Counter

INDEX

Index | 3Seite

272.7.15. System Controller 272.7.15.1. Reset Controller / VDDBU / 1,0 Volt from CPU

282.7.15.2. Shutdown Controller

282.7.16. CPU data-/addressbus (optional)

2.8. Real Time Clock 29

2.9. Memory Layout 30

2.10. CPU Address Mapping 31

312.10.1. NAND-Flash memory mapping

2.11. Pin Assignment 32

322.11.1. Connector J1 - 100pin Hirose (CPU, ethernet, serial) 362.11.2. Connector J2 - 100pin Hirose (optional) (address- & databus, cs) 372.11.2.1. J2 pin Description

2.12. DC Operating Conditions 38

382.12.1. Maximum Ratings

2.13. Dimensions 39

3. Firmware 41

3.1. UBOOT 41

3.2. Bootstrap procedure 41

4. Appendix 43

4.1. Important Documents 43

4.2. Ordering Information 44

4.3. Revisions 45

4.4. Copyrights and trademarks 46

I

Introduction |Seite 4

Introduction

Introduction |Seite 5

1. Introduction

1.1. General remarks

First of all, we would like to congratulate you to the purchase of a high qualityDEDITEC product.

Our products are being developed by our engineers according to qualityrequirements of high standard. Already during design and development we takecare that our products have -besides quality- a long availability and an optimalflexibility.

Modular design

The modular design of our products reduces the time and the cost of development.Therefor we can offer you high quality products at a competitive price.

Availability

Because of the modular design of our products, we have to redesign only a moduleinstead of the whole product, in case a specific component is no longer available.

1.2. Customer satisfaction

Our philosophy: a content customer will come again. Therefor customersatisfaction is in first place for us.

If by any chance, you are not content with the performance of our product, pleasecontact us by phone or mail immediately.

We take care of the problem.

1.3. Customer response

Our best products are co-developments together with our customers. Therefor weare thankful for comments and suggestions.

II

Hardware description |Seite 6

Hardware description


2. Hardware description

E-CPU-800 is a CPU module based on the AT91SAM9G20 processor fromAtmel. This processor board comes standard with a 128MB NAND Flash and a64MB (or 16MB) SDRAM.

The E-CPU-800 module only requires +3,3 Volt as power supply and works withthe open source operating system LINUX. For evaluation and engineering the E-CPU-800 module can be used with an additional baseboard (E-BASE-800). Anexternal address bus (A0-A25), data bus (D0-D31) and control signals (CS, RD,WR) are optional available on header J2.

Board overview:


2.1. Technical data

Single Power Supply: +3,3V

ATMEL AT91SAM9G20 CPU / 400MHz

32Kbyte Data Cache, 32Kbyte Instruction Cache, Write Buffer

ARM Jazelle® Technologie for Java Acceleration

64MB/16MB SDRAM (32Bit Databus)

128MB NAND Flash (8Bit Databus)

Ethernet Interface (100/10Mbit/sec)

1x CAN Controller (optional 2x)

Real Time Clock

2x USB 2.0 Host Interface (12Mbit/sec)

1x USB 2.0 Device Interface (12Mbit/sec)

Debug Unit

SPI Serial Peripheral Interface (2 channel)

TWI Two Wire Interface, (I²C compatible)

USART (5 channel)

MCI (MultiMedia Card Interface)

A/D Converter (10Bit / 4 channel)

In Circuit Emulator Interface (ICE)

JTAG debug port

Timer / Counter (6 channel)

Serial Synchronous Controller (SSC)

Board Dimensions: 72,00mm x 51,00mm

Operating systems: Linux, Microsoft Windows Embedded CE (optional)


2.2. Board Overview

Block diagram:


2.3. Mechanics

The E-CPU-800 module was designed as a CPU-module, which can beconnected to base boards with one or two 100-pin Hirose FX8 connectors.

The size of the E-CPU-800 module is only 72x51x6 mm. While havingimplemented the sensible CPU, SDRAM and Flash design, it still exports almostall possible CPU-Pins on its connectors to allow a flexible design on base boards.

2.4. CPU

ARM9G20 Core:

The AT91SAM9G20 is based on the integration of an ARM926EJ-S processorwith fast ROM and RAM memories and a wide range of peripherals.

The AT91SAM9G20 embeds an Ethernet MAC, one USB device port, and a USBHost controller. It also integrates several standard peripherals, such as the USART,SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMediaCard Interface. The AT91SAM9G20 is architectured on a 6-layer matrix, allowing amaximum internal bandwidth of six 32-bit buses. It also features an External BusInterface capable of interfacing with a wide Memory range of memory devices. TheAT91SAM9G20 is an enhancement of the AT91SAM9260 with the sameperipheral features.It is pin-to-pin compatible with the exception of power supplypins. Speed is increased to reach 400 MHz on the ARM core and 133 MHz on thesystem bus and EBI.

Embedded memories:

• 64 KB ROM

• Single Cycle Access at full matrix speed

• Two 16 KB Fast SRAM

• Single Cycle Access at full matrix speed

2.5. SDRAM

The E-CPU-800 is equiped with a 64MB (optional 16MB) Mobile SDRAM. It has a32Bit Databus.


2.6. Flash Memory

2.6.1. NAND Flash

The standard flash memory on the E-CPU-800 module is a 1Gbit (128MByte)NAND Flash with a 8Bit wide multiplexed Address-/ Databus. Larger memorysizes up to 4Gb will be supported.

2.6.2. Serial Flash (optional)

A 64/32Mbit Serial Flash Memory can be added optional to the E-CPU-800module. It can be used for booting purposes or storing configuration data. It´sconnected to the SPI Bus.

2.7. Interfaces

2.7.1. Ethernet

The Media Access Controller (MAC) of the Ethernet interface is integrated in theAT91SAM9G20 processor whereas the Physical Layer Interface (PHY) isimplemented by the DM9161. The MAC and configuration data of the Ethernetcontroller are stored in the NAND Flash.


2.7.1.1. Ethernet PHY

The E-CPU-800 module is equiped with a DM9161 10/100 Mbit MDI-X FastEthernet PHY Transceiver from Davicom. It´s wired to the 100pin connector J1 andallows the user to connect a RJ45 jack with transceiver directly, without anyresistors or capacitors.

The DM9161 is a physical layer, single-chip, and low power transceiver for100BASE-TX and 10BASE-T operations.

On the media side, it provides a direct interface either to Unshielded Twisted PairCategory 5 Cable (UTP5) for 100BASE-TX Fast Ethernet, or UTP5/UTP3 Cablefor 10BASE-T Ethernet. Through the Media Independent Interface (MII), theDM9161 connects to the Medium Access Control (MAC) layer, ensuring a highinter operability from different vendors.

The DM9161 uses a low power and high performance advanced CMOS process. Itcontains the entire physical layer functions of 100BASE-TX as defined byIEEE802.3u, including the Physical Coding Sublayer (PCS),Physical MediumAttachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TPPMD),10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit(TPMAU).

Pinout Ethernet

Pin J1 Signal Other function

Pin 54 ETH_LED_ACTIVITY -

Pin 56 ETH_LED_SPEED -

Pin 58 ETH_RXM -

Pin 60 ETH_RXP -

Pin 64 ETH_TXM -

Pin 66 ETH_TXP -

Pin 62 VCC_ETH -

Pin 68 GND_ETH -


2.7.2. CAN Interface

The E-CPU-800 module provides one (2nd is optional) independed Stand AloneCAN controller (MCP2515) that implements the CAN specification, version 2.0B.

It is capable of transmitting and receiving both standard and extended data andremote frames. The MCP2515 has two acceptance masks and six acceptancefilters that are used to filter out unwanted messages, thereby reducing the hostMCUs overhead. The MCP2515 interfaces with microcontrollers (MCUs) via anindustry standard Serial Peripheral Interface (SPI).

Pinout CAN1


Pin 87 TXCAN1 -

Pin 89 RXCAN1 -

Pinout CAN2 (optional)


Pin 91 RXCAN2 -

Pin 93 TXCAN2 -


2.7.3. USB Host Port

The USB Host Port (UHP) interfaces the USB with the host application. It handlesOpen HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speedand Low-speed protocols.

The USB Host Port integrates a root hub and transceivers on downstream ports. Itprovides several high-speed half-duplex serial communication ports at a baud rateof 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.)and the USB hub can be connected to the USB host in the USB ”tiered star”topology.

The USB Host Port controller is fully compliant with the OpenHCI specification. Thestandard OHCI USB stack driver can be easily ported to ATMEL’s architecture inthe same way all existing class drivers run without hardware specialization.

This means that all standard class devices are automatically detected andavailable to the user application. As an example, integrating an HID (HumanInterface Device) class driver provides a plug & play feature for all USB keyboardsand mouses.

There are two pins for each USB port at header J1.

Pinout USB Port 1


Pin 53 HDMA -

Pin 55 HDPA -

Pinout USB Port 2


Pin 49 HDMB -

Pin 51 HDPB -


2.7.4. USB Device Port

The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0full-speed device specification.

Each endpoint can be configured in one of several USB transfer types. It can beassociated with one or two banks of a dual-port RAM used to store the current datapayload. If two banks are used, one DPR bank is read or written by the processor,while the other is read or written by the USB device peripheral. This feature ismandatory for isochronous endpoints. Thus the device maintains the maximumbandwidth (1M bytes/s) by working with endpoints with two banks of DPR.

Pinout USB Device Port


Pin 57 DDP -

Pin 59 DDM -

Pin 61 USB_CNX -


2.7.5. Universal Synchronous Asynchronous Receiver Transmitter(USART)

The Universal Synchronous Asynchronous Receiver Transmitter (USART) providesone full duplex universal synchronous asynchronous serial link. Data frame formatis widely programmable (data length, parity, number of stop bits) to support amaximum of standards. The receiver implements parity error, framing error andoverrun error detection. The receiver time-out enables handling variable-lengthframes and the transmitter timeguard facilitates communications with slow remotedevices. Multidrop communications are also supported through address bithandling in reception and transmission. The USART features three test modes:remote loopback, local loopback and automatic echo.The USART supportsspecific operating modes providing interfaces on RS485 buses, with ISO7816 T =0 or T = 1 smart card slots, infrared transceivers and connection to modem ports.The hardware handshaking feature enables an out-of-band flow control byautomatic management of the pins RTS and CTS. The USART supports theconnection to the Peripheral DMA Controller, which enables data transfers to thetransmitter and from the receiver. The PDC provides chained buffer managementwithout any intervention of the processor.

Pinout USART 0


Pin 25 PB4/TXD0 -

Pin 27 PB5/RXD0 -

Pinout USART 1


Pin 39 PB6/TCLK1/TXD1 Mpx with Timer Counter

Pin 37 PB7/TCLK2/RXD1 Mpx with Timer Counter

Pinout USART 2


Pin 29 PB8/TXD2 -

Pin 31 PB9/RXD2 -


Pinout USART 4


Pin 41 PA31/SCK0/TXD4 Mpx with SSC clock 0

Pin 43 PA30/SCK2/RXD4 Mpx with SSC clock 2

Pinout USART 5


Pin 28 PB12/ISI_D10/TXD5 -

Pin 36 PB13/ISI_D11/RXD5 -


2.7.6. Debug Port (DBG)

The Debug Unit provides a single entry point from the processor for access to allthe debug. The Debug Unit features a two-pin UART that can be used for severaldebug and trace purposes and offers an ideal medium for in-situ programmingsolutions and debug monitor communications.

Moreover, the association with two peripheral data controller channels permitspacket handling for these tasks with processor time reduced to a minimum.

The Debug Unit also makes the Debug Communication Channel (DCC) signalsprovided by the In-circuit Emulator of the ARM processor visible to the software.These signals indicate the status of the DCC read and write registers andgenerate an interrupt to the ARM processor, making possible the handling of theDCC under interrupt control.

Chip Identifier registers permit recognition of the device and its revision. Theseregisters inform as to the sizes and types of the on-chip memories, as well as theset of embedded peripherals.

Finally, the Debug Unit features a Force NTRST capability that enables thesoftware to decide whether to prevent access to the system via the In-circuitEmulator. This permits protection of the code, stored in ROM.

Pinout Debug Port


Pin 23 PB14/RX_DBG -

Pin 21 PB15/TX_DBG -


2.7.7. Serial Synchronous Controller (SSC)

The Atmel Synchronous Serial Controller (SSC) provides a synchronouscommunication link with external devices. It supports many serial synchronouscommunication protocols generally used in audio and telecom applications suchas I2S, Short Frame Sync, Long Frame Sync, etc.

The SSC contains an independent receiver and transmitter and a common clockdivider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for theFrame Sync. The transfers can be programmed to start automatically or ondifferent events detected on the Frame Sync signal.

The SSC’s high-level of programmability and its two dedicated PDC channels ofup to 32 bits permit a continuous high bit rate data transfer without processorintervention.

Featuring connection to two PDC channels, the SSC permits interfacing with lowprocessor overhead to the following:

• CODEC’s in master or slave mode

• DAC through dedicated serial interface, particularly I2S

• Magnetic card reader

Pinout SSC


Pin 33 PB17/TCLK4/TF0/I2CTCK

Mpx with Timer Counter and I2C

Pin 35 PB16/TCLK3/TK0/I2CTWD

Mpx with Timer Counter and I2C

Pin 73 PB19/TIOB5/RD0 Mpx with Timer Counter

Pin 75 PB18/TIOB4/TD0 Mpx with Timer Counter


2.7.8. A/D-Converter 10Bit / 4 channel

The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates a 4-to-1 analog multiplexer, makingpossible the analog-to-digital conversions of 4 analog lines. The conversionsextend from 0V to ADVREF.

The ADC supports an 8-bit or 10-bit resolution mode, and conversion results arereported in a common register for all channels, as well as in a channel-dedicatedregister. Software trigger, external trigger on rising edge of the ADTRG pin orinternal triggers from Timer Counter output(s) are configurable.

The ADC also integrates a Sleep Mode and a conversion sequencer and connectswith a PDC channel. These features reduce both power consumption andprocessor intervention. Finally, the user can configure ADC timings, such asStartup Time and Sample & Hold Time.

Pinout ADC


Pin 10 PC0/ADIN0 -

Pin 12 PC1/ADIN1 -

Pin 14 PC2/ADIN2 -

Pin 16 PC3/ADIN3 -

Pin 18 ADVREF -

Pin 20 ADGND -


2.7.9. JTAG (Join Test Action Group)

The JTAG unit can be used for hardware diagnostics, hardware initialization, flashmemory programming, and debug purposes.

Pinout JTAG


Pin 9 XICE_TDI -

Pin 11 XICE_TDO -

Pin 13 XICE_RTCK -

Pin 15 XICE_NTRST -

Pin 17 XICE_TMS -

Pin 19 XICE_TCK -


2.7.10. MCI (MultiMedia Card Interface)

The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC)Specification V3.11, the SDIO Specification V1.1 and the SD Memory CardSpecification V1.0.

The MCI includes a command register, response registers, data registers, timeoutcounters and error detection logic that automatically handle the transmission ofcommands and, when required, the reception of the associated responses anddata with a limited processor overhead.

The MCI supports stream, block and multi-block data read and write, and iscompatible with the Peripheral DMA Controller (PDC) channels, minimizingprocessor intervention for large buffer transfers.

The MCI operates at a rate of up to Master Clock divided by 2 and supports theinterfacing of 2 slot(s). Each slot may be used to interface with a MultiMediaCardbus (up to 30 Cards) or with a SD Memory Card. Only one slot can be selected ata time (slots are multiplexed). A bit field in the SD Card Register performs thisselection.

The SD Memory Card communication is based on a 9-pin interface (clock,command, four data and three power lines) and the MultiMedia Card on a 7-pininterface (clock, command, one data, three power lines and one reserved for futureuse).

The SD Memory Card interface also supports MultiMedia Card operations. Themain differences between SD and MultiMedia Cards are the initialization processand the bus topology.

Pinout MCI


Pin 74 PA7/MCCDA -

Pin 76 PA6/MC_DA0 -

Pin 78 PA8/MC_CK -

Pin 80 PA10/MC_DA2 -

Pin 82 PA9/MC_DA1 -

Pin 84 PA11/MC_DA3 -


2.7.11. TWI (Two-wire Interface)

The Atmel Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400Kbits per second, based on a byte-oriented transfer format. It can be used with anyAtmel Two-wire Interface bus Serial EEPROM and I²C compatible device such asReal Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and TemperatureSensor, to name but a few. The TWI is programmable as a master or a slave withsequential or single-byte access. Multiple master capability is supported.Arbitration of the bus is performed internally and puts the TWI in slave modeautomatically if the bus arbitration is lost.

A configurable baud rate generator permits the output data rate to be adapted to awide range of core clock frequencies.

I²C Standart Atmel TWI

Standard Mode Speed (100KHz) Supported

Fast Mode Speed (400 KHz) Supported

7 or 10 bits Slave Addressing Supported

START BYTE* Not Supported

Repeated Start (Sr) Condition Supported

ACK and NACK Management Supported

Slope control and input filtering(Fast mode)

Not Supported

Clock stretching Supported

Note: * START + b000000001 + Ack + Sr

Pinout TWI


Pin 45 PB16/TCLK3/TK0/I2CTWD

-

Pin 47 PB17/TCLK4/TF0/I2CTCK

-


2.7.12. Error Corrected Code (ECC) Controller

NAND Flash/SmartMedia devices contain by default invalid blocks which have oneor more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalidblocks may occur which can be detected/corrected by ECC code.

The ECC Controller is a mechanism that encodes data in a manner that makespossible the identification and correction of certain errors in data. The ECCcontroller is capable of single bit error correction and 2-bit random detection.When NAND Flash/SmartMedia have more than 2 bits of errors, the data cannotbe corrected.

2.7.13. SPI (Serial Peripheral Interface)

The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link thatprovides communication with external devices in Master or Slave Mode. It alsoenables communication between processors if an external processor is connectedto the system.

The Serial Peripheral Interface is essentially a shift register that serially transmitsdata bits to other SPIs. During a data transfer, one SPI system acts as the”master”' which controls the data flow, while the other devices act as ”slaves'' whichhave data shifted into and out by the master.

Different CPUs can take turn being masters (Multiple Master Protocol opposite toSingle Master Protocol where one CPU is always the master while all of the othersare always slaves) and one master may simultaneously shift data into multipleslaves. However, only one slave may drive its output to write data back to themaster at any given time.

A slave device is selected when the master asserts its NSS signal. If multiple slavedevices exist, the master generates a separate slave select signal for each slave(NPCS).

The SPI system consists of two data lines and two control lines:

• Master Out Slave In (MOSI): This data line supplies the output data from themaster shifted into the input(s) of the slave(s).

• Master In Slave Out (MISO): This data line supplies the output data from a slaveto the input of the master. There may be no more than one slave transmitting dataduring any particular transfer.

• Serial Clock (SPCK): This control line is driven by the master and regulates theflow of the data bits. The master may transmit data at a variety of baud rates; theSPCK line cycles once for each bit that is transmitted.

• Slave Select (NSS): This control line allows slaves to be turned on and off byhardware.


Pinout SPI 0


Pin 50 PA1/SPI0_MOSI/MC_CDB

Mpx with MCI B

Pin 52 PA0/SPI0_MISO/MC_DB0

Mpx with MCI B

Pin 70 PA2/SPI0_SPCK -

Pin 72 PA3/SPI0_NPCS0/MC_DB3

Mpx with MCI B

Pin 86 PC11/SPI0_NPCS1 -

Pin 34 PB21/SPI0_CSCAN1 SPI_CS used for optional 2. CANcontroller

Pinout SPI 1


Pin 71 PB2/TIOA4/SPI1_SPCK Mpx with Timer Counter

Pin 69 PB0/TIOA3/SPI1_MISO Mpx with Timer Counter

Pin 63 PB1/TIOB3/SPI1_MOSI Mpx with Timer Counter

Pin 65 PB3/TIOA5/SPI1_NPCS0Mpx with Timer Counter


2.7.14. Timer Counter

The Timer Counter (TC) block consists of three identical 16-bit Timer Counterchannels. Each channel can be independently programmed to perform a widerange of functions including frequency measurement, event counting, intervalmeasurement, pulse generation, delay timing and pulse width modulation. Eachchannel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channeldrives an internal interrupt signal which can be programmed to generate processorinterrupts. The Timer Counter block has two global registers which act upon allthree TC channels. The Block Control Register allows the three channels to bestarted simultaneously with the same instruction. The Block Mode Register definesthe external clock inputs for each channel, allowing them to be chained.

Pinout Timer Counter


Pin 39 PB6/TCLK1/TXD1 Mpx with USART 1

Pin 37 PB7/TCLK2/RXD1 Mpx with USART 1

Pin 35 PB16/TCLK3/TK0/I2CTWD*

Mpx with SSC and I2C

Pin 45 PB16/TCLK3/TK0/I2CTWD*


Pin 33 PB17/TCLK4/TF0/I2CTCK*


Pin 47 PB17/TCLK4/TF0/I2CTCK*


Pin 75 PB18/TIOB4/TDO Mpx with SSC

Pin 73 PB19/TIOB5/RD0 Mpx with SSC

Pin 69 PB0/TIOA3/SPI1_MISO Mpx with SPI 1

Pin 71 PB2/TIOA4/SPI1_SPCK Mpx with SPI 1

Pin 65 PB3/TIOA5/SPI1/NPCS0 Mpx with SPI 1

Pin 63 PB1/TIOB3/SPI1_MOSI Mpx with SPI 1

Pin 67 PC7/TIOB1/CFCE2 Mpx with ECC

* These signals are lead out two times.


2.7.15. System Controller

The System Controller is a set of peripherals that allows handling of key elementsof the system,such as power, resets, clocks, time, interrupts, watchdog, etc. TheSystem Controller User Interface also embeds the registers that configure theMatrix and a set of registers for the chip configuration. The chip configurationregisters configure EBI chip select assignment and voltage range for externalmemories.

The System Controller’s peripherals are all mapped within the highest 16 Kbytes ofaddress space, between addresses 0xFFFF E800 and 0xFFFF FFFF.

However, all the registers of System Controller are mapped on the top of theaddress space. All the registers of the System Controller can be addressed from asingle pointer by using the standard ARM instruction set, as the Load/Storeinstruction has an indexing mode of ±4 Kbytes.

2.7.15.1. Reset Controller / VDDBU / 1,0 Volt from CPU

• Based on two Power-on-reset cells

- One on VDDBU and one on VDDCORE

• Status of the last reset

- Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), softwarereset, user reset or watchdog reset

• Controls the internal resets and the NRST pin output

- Allows shaping a reset signal for the external devices

Pinout Reset Controller


Pin 88 CPU_GEN_1V0 -

Pin 83 NRST -

Pin 90 VDDBU -


2.7.15.2. Shutdown Controller

Shutdown and Wake-up logic

- Software programmable assertion of the SHDWN pin

- Deassertion Programmable on a WKUP pin level change or on alarm

Pinout Shutdown Interface


Pin 92 SHDN -

Pin 94 WKUP -

2.7.16. CPU data-/addressbus (optional)

32-bit data bus

26-bit address bus

2 external Chip Select

1 external RD pin

1 external WR pin


2.8. Real Time Clock

The E-CPU-800 module is equiped with an internal RTC from Intersil. TheISL12026 comes with following futures:

- I2C Interface

- Real Time Clock / Calendar

- Two Non Volatile Alarms

- 512x8 Bits of EEPROM

Pinout Real Time Clock


Pin 33 & Pin47

PB17/TCLK4/TF0/I2C/TCK

Mpx with Timer Counter & SSC

Pin 35 & Pin45

PB16/TCLK3/TK0/I2C/TWD

Mpx with Timer Counter & SSC

Pin 79 VBAT -


2.9. Memory Layout


2.10. CPU Address Mapping

Address Mapping

Chip Memory address CPU-CS Signal

??????? 0x10000000 NCS0

SDRAM 0x20000000 SDCS_NCS1

NAND-Flash 0x40000000 NCS3/NANDCS

CF-Card-0 0x50000000 CFCS0 (NCS4)

CF-Card-1 0x60000000 CFCS1 (NCS5)

Dataflash1(optional)

0xC0000000 SPI0_NPCS0

Dataflash2(optional)

0xD0000000 SPI0_NPCS1

2.10.1. NAND-Flash memory mapping

Memory address Memory Size Description

0x4000 0000 128 Kbyte Nandflash Bootloader (boots U-BOOT)

0x4002 0000 256 Kbyte U-BOOT

0x4006 0000 128 Kbyte U-BOOT Environment

0x4008 0000 128 Kbyte U-BOOT Environment (copy)

0x4010 0000 15 Mbyte Linux Kernel

0x4100 0000 48 MByte Linux File-System

0x4400 0000 64 MByte Linux File-System 2


2.11. Pin Assignment

2.11.1. Connector J1 - 100pin Hirose (CPU, ethernet, serial)

Adaptable connector: Hirose FX8C-100P-SV

Uneven pin-numbers:

Pin J1 Signal Direction Description

Pin 1 3V3 Power

Pin 3 3V3 Power

Pin 5 3V3 Power

Pin 7 3V3 Power

Pin 9 XICE_TDI Input CPU-JTAG: Test Data In

Pin 11 XICE_TDO Output CPU-JTAG: Test Data Out

Pin 13 XICE_RTCK Output CPU-JTAG: Return Test Clock

Pin 15 XICE_NTRST Input CPU-JTAG: Allows reset of theJTAG Port

Pin 17 XICE_TMS Input CPU-JTAG: Test Mode Select

Pin 19 XICE_TCK Input CPU-JTAG: Test Clock

Pin 21 PB15 / TX_DBG Output Debug Port TX

Pin 23 PB14 / RX_DBG Input Debug Port RX

Pin 25 PB4 / TXD0 Output USART 0 TXD

Pin 27 PB5 / RXD0 Input USART 0 RXD

Pin 29 PB8 / TXD2 Output USART 2 TXD

Pin 31 PB9 / RXD2 Input USART 2 RXD

Pin 33 PB17 / TCLK4 / TF0 /I2CTCK

I/O Internal Clock Input4 / Transm.FrameSyncro / I2C Test Clock

Pin 35 PB16 / TCLK3 / TK0 /I2CTWD

I/O Internal Clock Input3 / TransmitterClock / I2C

Pin 37 PB7 / TCLK2 / RXD1 I/O Internal Clock Input2 / USART 1RXD

Pin 39 PB6 / TCLK1 / TXD1 I/O Internal Clock Input1 / USART 1 TXD

Pin 41 PA31 / SCK0 / TXD4 I/O USART 0 Clock / USART 4 TXD

Pin 43 PA30 / SCK2 / RXD4 I/O USART 2 Clock / USART 4 RXD

Pin 45 PB16 / TCLK3 / TK0 /I2CTWD

I/O Internal Clock Input3 / TransmitterClock / I2C

Pin 47 PB17 / TCLK4 / TF0 /I2CTCK

I/O Internal Clock Input4 / Transm.FrameSyncro / I2C Test Clock

Pin 49 HDMB I/O USB Host B -

Pin 51 HDPB I/O USB Host B +

Pin 53 HDMA I/O USB Host A -


Pin 55 HDPA I/O USB Host A +

Pin 57 DDP I/O USB Device +

Pin 59 DDM I/O USB Device -

Pin 61 USB_CNX Input Detect host connection

Pin 63 PB1 / TIOB3 /SPI1_MOSI

I/O Timer Counter I/O / SPI1 MOSI

Pin 65 PB3 / TIOA5 /SPI1_NPCS0

I/O Timer Counter I/O / SPI1 Chip Select0

Pin 67 PC7 / TIOB1 / CFCE2 I/O Timer Counter I/O / ECC

Pin 69 PB0 / TIOA3 /SPI1_MISO

I/O Timer Counter I/O / SPI1 MISO

Pin 71 PB2 /TIOA4 /SPI1_SPCK

I/O Timer Counter / SPI1 Clock

Pin 73 PB19 / TIOB5 / RD0 I/O Timer Counter I/O

Pin 75 PB18 / TIOB4 / TD0 I/O Timer Counter I/O

Pin 77 PC6 / RX0BE_1 I/O Timer Counter I/O / CF-Card ChipEnable1

Pin 79 VBAT In VBAT

Pin 81 PC9 / CFCS1 Out CF – CS1

Pin 83 NRST I/O Reset CPU

Pin 85 WP_SER_FLASH Input Write Protect Ser. Flash (active=low)

Pin 87 TXCAN1 I/O CAN1 TX

Pin 89 RXCAN1 I/O CAN1 RX

Pin 91 TXCAN2 I/O CAN2 TX

Pin 93 RXCAN2 I/O CAN2 RX

Pin 95 GND Ground

Pin 97 GND Ground

Pin 99 GND Ground


Even pin-numbers:

Pin J1 Signal Direction Description

Pin 2 3V3 Power

Pin 4 3V3 Power

Pin 6 3V3 Power

Pin 8 3V3 Power

Pin 10 PC0 / ADIN0 Input Analog Input Channel 1




Pin 18 ADVREF Input Reference Voltage

Pin 20 ADGND Input Analog Ground

Pin 22 NC Not connected



Pin 28 PB12 / ISI_D10 / TXD5 Input ISI Data 10 / USART 5 TXD

Pin 30 PB10 / ISI_D8 / TXD3 Input ISI Data 8 / USART 3 TXD

Pin 32 PB23 / CAN_IRQ1 Interrupt CAN 1 (optional 2.CAN)

Pin 34 PB21 / SPI0_CSCAN1 Chip Select CAN 1 (optional 2.CAN)

Pin 36 PB13 / ISI_D11 / RXD5 Input ISI Data 11 / USART 5 RXD

Pin 38 PB25 / ISI_D5 / RI0 Input ISI Data 5 / USART 0 RI

Pin 40 PB27 / ISI_D7 / CTS0 Input ISI Data 7 / USART 0 CTS

Pin 42 PB29 / ISI_VSYNC /CTS1

Input ISI VSYNC / USART 1 CTS

Pin 44 PB30 / ISI_HSYNC /PCK0

Input ISI HSYNC / ISI Pixel Clock 0

Pin 46 PB26 / ISI_D6 / RTS0 Input ISI Data 6 / USART 0 RTS

Pin 48 PB28 / ISI_PCK / RTS1 Input ISI Pixel Clock / USART 1 RTS

Pin 50 PA1 / SPI0_MOSI /MC_CDB

SPI 0 MOSI

Pin 52 PA0 / SPI0_MISO /MCDB0

SPI 0 MISO

Pin 54 ETH_LED_ACTIVITY Output High: Link / Low: Link Failed

Pin 56 ETH_LED_SPEED Output High: 100 Mbit / Low: 10 Mbit

Pin 58 ETH_RXM Input ETH RX-

Pin 60 ETH_RXP Input ETH RX+

Pin 62 VCC_ETH Power Out ETH Power

Pin 64 ETH_TXM Output ETH TX-

Pin 66 ETH_TXP Output ETH TX+

Pin 68 GND_ETH Power Out ETH Ground

Pin 70 PA2 / SPI0_SPCK I/O SPI 0 Clock


Pin 72 PA3 / SPI0_NPCS0 /MC_DB3

Output SPI 0 Chip Select 0

Pin 74 PA7 / MCCDA I/O SD Card Command

Pin 76 PA6 / MCDA0 I/O SD Card Data0

Pin 78 PA8 / MC_CK I/O SD Card Clock

Pin 80 PA10 / MC_DA2 I/O SD Card Data2



Pin 86 PC11 / SPI0_NPCS1 Output SPI 0 Chip Select 1

Pin 88 +1V0 Output 1,0V output from CPU Regulator

Pin 90 VDDBU Input 1,0V VDDBU input (connect to pin88 or to an external battery)

Pin 92 SHDN Output Shutdown

Pin 94 WKUP Input Wake up

Pin 96 GND Ground

Pin 98 GND Ground

Pin 100 GND Ground


2.11.2. Connector J2 - 100pin Hirose (optional) (address- & databus, cs)

Adaptable connector: Hirose FX8C-100P-SV

Pin J2 Signal Pin J2 Signal

Pin 1 GND Pin 2 GND

Pin 3 CPU_D7 Pin 4 PC31 / CPU_D31








Pin 19 GND Pin 20 GND










Pin 39 NWR3 Pin 40 NWR1

Pin 41 PC12 / NCS7 / IRQ0 Pin 42 PC15 / IRQ1 / NWAIT

Pin 43 CPU_A1 / NWR2 Pin 44 CPU_A0

Pin 45 CPU_A3 Pin 46 CPU_A2










Pin 65 PC4 / CPU_A23/ALE Pin 66 CPU_A22/CLE

Pin 67 PC10 / CPU_A25 Pin 68 PC5 / PIOUSBCNX / A24


Pin 71 NRD Pin 72 NWE / NWR0


Pin 73 NCS0 Pin 74 NRST














2.11.2.1. J2 pin Description

Signal Direction Description

CPU_D0 – CPU_D31 I/O CPU Data Bus (D0 – D31)

CPU_A0 – CPU_A25 Out CPU Address Bus (A0 – A25)

NWR1 I/O

NWR3 I/O

NSC7 / IRQ0

IRQ0 / NWAIT

NRD

NWF

NCS0

NRST


2.12. DC Operating Conditions

1. Supply voltage 3,3V

2. Typical operating current with 64MB SDRAM:

Normal operation 180 mA

2.12.1. Maximum Ratings

Total DC Output Current on all I/O lines ................ xx mA


2.13. Dimensions

III

Firmware |Seite 40

Firmware

Firmware |Seite 41

3. Firmware

3.1. UBOOT

3.2. Bootstrap procedure

IV

Appendix |Seite 42

Appendix

Appendix |Seite 43

4. Appendix

4.1. Important Documents

CPU:

Atmel AT91SAM9G20 datasheet:

http://www.atmel.com/products/

Ethernet Phy:

Davicom DM9161 datasheet:

http://www.davicom.com.tw/page1.aspx?no=143760

Hirose Connectors:

E-CPU-1000 / E-CPU-1100 module:

Hirose FX8-100S-SV

Adaptable Connector:

Hirose FX8C-100P-SV:

http://www.hirose-connectors.com/

Real Time Clock:

Intersil ISL12026:

http://www.intersil.com/products/deviceinfo.asp?pn=ISL12026



http://www.davicom.com.tw/page1.aspx?no=143760

http://www.hirose-connectors.com/

http://www.intersil.com/products/deviceinfo.asp?pn=ISL12026

Appendix |Seite 44

4.2. Ordering Information

E-CPU-800 Version with 64MB SDRAM

E-CPU-800/16 Version with 16MB SDRAM

Appendix |Seite 45

4.3. Revisions

Rev 1.00 First issue

Rev 2.00 Design change

Rev 2.01 Added index

Appendix |Seite 46

4.4. Copyrights and trademarks

Linux is registered trade-mark of Linus Torvalds.

Windows CE is registered trade-mark of Microsoft Corporation.

USB is registered trade-mark of USB Implementers Forum Inc.

LabVIEW is registered trade-mark of National Instruments.

Intel is registered trade-mark of Intel Corporation

AMD is registered trade-mark of Advanced Micro Devices, Inc.