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TN-47-20: Point-to-Point Package Sizes and Layout BasicsIntroduction

PDF: 09005aef822d14b5/Source: 09005aef822641f0 Micron Technology, Inc., reserves the right to change products or specif icat ions without not ice.TN4720.fm - Rev. A 6/07 EN 1 2006 Micro n Technology, In c. All r igh ts reserved.

Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by

Micron wi thout not ice. Products are only warranted by M icron to meet Microns production dat a sheet specif ications. Allinf ormat ion discussed herein is provided on an as is basis, wit hout warranties of any kind.

Technical NoteDDR2 (Point-to-Point) Package Sizes and Layout Basics

Introduction

Point -to-po int designers face ma ny challen ges when laying out a new printe d circuit

boa rd (PCB). The d esigner m ay need to arran ge group s of devices within a certain area

of the PCB, to place comp on ent s away from critical keep-ou t zones, includ e add ition al

solder pad s for future com pon ent u pgrades, or even en sure the design is robust en ough

to sup port a po tentially faster m em ory speed. Add ition al featu reslike test points,

sockets, and alignmen t ho lesma y also be need ed. Combining these requ iremen ts with

an already comp lex PCB floor p lan can m ake a p oint-to-p oint layout extremely difficultto comp lete.

DDR2 SDRAM m em ory can m ake floor p lann ing easier with th e u se of JEDEC-stand ard

FBGA pa ckages. The pred efine d ba ll ou t with a simp le addressing schem e that su pp orts

all den sities and co nfiguration s helps m ake it easy to design for futu re mem ory

up grades. Ano ther layout advanta ge of DDR2 m em ory is supp ort for on-d ie term ination

(ODT). ODT imp roves signal qua lity while eliminat ing m ost of th e externa l parallel

term ination resistors. By eliminat ing term ination resistors for mem ory I/O, available

board space is increased an d the nu mb er of through-hole vias is reduced.

This docum ent d oes n ot go into de tail on PCB stack-ups, types of traces (stripline vs.

m icrostrip), or topology characterization for the various n ets. This techn ical no te doe s

provide gen eral guidelines for developin g the PCB floor p lan, point s out som e of the key

featu res of DDR2 techn ology, and ide ntifies what to con sider when starting a new p oint-

to-p oint d esign th at u ses DDR2 SDRAM devices. A Micron DDR2 design guide

cont aining detailed routin g inform ation will soon be available.

Gett ing StartedUnderstand the Packages

One of the first steps to a good design is understanding the package variations th at m ay

exist be tween DDR2 devices. Althou gh all stand ard p ackages fall within t he JEDEC-

defined lim its, various package sizes an d ball arrays are available. For examp le, x16

com po nen ts use either an 84-ball array or a 92-ball array, depen ding on th e overall

package size. Likewise, the x4 or x8 configurations use either a 60-ball array or a 68-ba ll

array. Both the 92-ball an d 68-ball packages include out rigger balls in each of the four

corne rs. These add ition al outrigger balls provide mech an ical sup port for the larger

package sizes. The cent er section, o r electrical ball array, is iden tical for th e p ackage with

outriggers an d the p ackage withou t outriggers. The o utrigger balls are true n o con nect s

an d dont have an y electrical con nection s to the sub strate.


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TN-47-20: Point-to-Point Package Sizes and Layout BasicsGett ing Star tedUnderstand t he Packages

Figure 1: 60-Ball and 68-Ball Package Compat ibil ity used only for x4/x8 devices

Actual p ackage size can vary by den sity, vendor, or con figuration . For exam ple, the

Micron 512Mb, 8-bit-wide DDR2 device is 10mm (wide) x 10mm (tall) where an oth er

vendor m ay prod uce th eir 512Mb, 8-bit-wide DDR2 device in an 9mm x 11.5mmpackage. The two pa ckages ha ve ap proxim ately the sam e area, but on e is wider an d

shorte r, an d the oth er is na rrow and taller. Even thou gh both p ackages ha ve the iden tical

60-ball electrical array, the finished b oard layout ma y not be ab le to accomm oda te both

vendor p ackages if the layout d esigner d id not co m pen sate for the slight variation

between these p ackage sizes. For a look at oth er package-related design consideration s,

see Micron techn ical note TN-47-08, DDR2 Package Sizes an d Layout Requ irem en t.

The sub jects covered includ e th e m axim um , JEDEC-allowable package sizes; a comm on

land ing pattern, wh ich was developed to accept all possible p ackage com binations; and

a fun ctional cross-reference table for all signals/ balls.

60-ball package

68-ball package(60 balls wit h out riggers)

PCBs using DDR2 x4 or x8 devices shouldbe designed to accept bot h 60-ball and68-ball packages

60-ball array is commonfor both package

Outriggers are only usedon the larger packages


3/12


TN-47-20: Point-to-Point Package Sizes and Layout BasicsSpecial Signals and Designing for Flexibility

Figure 2: 84-Ball and 92-Ball Package Compat ibil ity used only for x16 devices

Special Signals and Designing f or Flexibili ty

DDR2 SDRAM has m an y more features than previous DRAM me m ory, and to accom m o-

date these featu res, several balls are m ultifun ctional. Layout is easier if these un ique

mu ltifunction al balls are iden tified before starting the design (see Table 1 on page 4).

The com plem en t strobe (DQS#) is an o ption al signal which is only active when the

DDR2 SDRAM is en ab led for different ial strob es. If differen tial strobes are n ot en ab led,

this ball becom es a not-u sed (NU) con nection . A NU ball is define d as ha ving an in tern al

conn ection to th e die, but d oes not h ave any fun ction.

DDR2 (x8) m em ory supp orts a redu nd an t set of strobes to a llow the x8 con figuration to

replicate t wo x4 DDR2 devices. These two signals redun dan t strob e (RDQS) an d

com plem ent red un dan t strobe (RDQS#) are op tional and are only active if ena bled.

RDQS is en abled in th e extend ed mo de register (EMR), with bit 11 and RDQS# is enab led

by EMR bit 10. If they are not ena bled, these t wo ba lls becom e NU signals.

Unless the design is for the ma xim um -den sity DDR2 par t, it is essent ial to incorp orate a

few a dditiona l signals to guaran tee future flexibility for h igher den sity devices. The

add ressing schem e is straightforward, an d sup po rt for higher de nsity parts is easy if theadd ition al addresses are available at the package. These key add resses includ e:

Bank ad dress 2 (BA2) is need ed for all 8-ban k devices, including the 1Gb- an d 2Gb-

density parts

Row/Column address 13 (A13) is required on x4/x8 devices starting with the 512Mb

den sity an d on the 2Gb x16 device

Row/Column address 14 (A14) is required on the 2Gb x4/ x8 devices

84-ball package

92-ball package(84 balls with outriggers)

84-ball array is commonfor both package

Outriggers are only usedon the larger 92-ball package

PCBs using DDR2 x16devices shouldbe designed to accept both 84-ball and 92-ball packages


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TN-47-20: Point-to-Point Package Sizes and Layout BasicsDesign for Debug and/or Test

Each of these add ress pins is considered a n o conn ect (NC) on th e devices that do not

require them . As an NC pin, there is no intern al con ne ction to th e die. Micron su ggests

routing these pins to th e m emory controller so higher density parts can be sup ported. If

the m emor y controller does n ot supp ort these higher order addresses, they could be tied

to groun d th rough a resistor. This will allow the h igher d ensity parts to fun ction when

soldered on to the PCB.

Note that if the se pins are tied to groun d the h igher d ensity parts will function, bu t the

den sity is limited to the nu m ber o f address pin s actua lly driven by the con troller. Also

no te the h igher d en sity pa rts ma y have slightly differen t refresh timing requ iremen ts.

Design for Debug and/or Test

Unlike previous DRAM tech nologies where m ost devices were offered in a TSOP or SOJ

package an d a ll pins were exposed for externa l test points, DDR2 devices are on ly avail-

able in FBGA packages. The FBGA pa ckage uses very sm all solder b alls on the bott om of

the d evice to m ake both an electrical an d p hysical con nection to the PCB. Once the

FBGA pa ckage is soldered to th e PCB, the in terconn ections a re inaccessible. Due to

these hidd en no des o n DDR2 devices, it is virtua lly im po ssible to a ccess the DRAM

signa ls unless the boa rd is well designed. In add ition , becau se of DDR2s high sp eeds,

including trace stu bs an d large test poin ts could affect the qu ality of individu al signals.

Initial debug an d b oard p rototyping need s are different from long term man ufacturing

requirem ent s. For th e initial board d ebu g and for verifying signal qu ality, a lab tech ni-

cian can scrape th e prot ective coating off of a trace or solder a th in wire into an exposed

via to m ake a reliable scope/ probe con nection. But, in a p roduction en vironm ent, m ost

test en gine ers are going to wan t to verify the integrity of the so lder joints b y using a

bed-of-nails type of tester. All of these req uireme nts can be achieved with ca reful plan -

ning.

Table 1: Key Signal Functionalit y Table

SignalName

PinNomenclature Signal Type Funct ion

A13 NC No connection to internal die.Okay to run trace to PCB pad.

Used on x4/x8 512Mb and 1Gb devices and al l

configu rations of t he 2Gb or 4Gb.

A14 NC No Connection to int ernal die.Okay to run trace to PCB pad.

Used on x4/x8 2Gb devices and al l 4Gb conf igurat ions.

A15 NC No Connection to int ernal die.Okay to run trace to PCB pad.

Used on 4Gb (x4/x8) devices.

BA2 NC No Connection to int ernal die.Okay to run trace to PCB pad.

Used on all configurations of the 1Gb, 2Gb, and 4Gb.

DQS# NU May have internal connect ion to die.

If not enabledDO NOT USE.

Optional for use on t he x4 and x8 conf igurations. Only

use when the differential strobe function is enabled.

UDQS#,

LDQS#

NU M ay have int ernal connect ion to die.


Optional f or use on t he x16 conf igurations. Only use

when the dif ferential strobe function is enabled.

RDQS NU May have internal connect ion to die.


Optional fo r use on the x8. Only use when t he

redundant strobe function is enabled.

RDQS# NU May have internal connect ion to die


Optional fo r use on the x8 configu ration. Only use

when t he redundant strobe and dif ferential strobefunctions are enabled.


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TN-47-20: Point-to-Point Package Sizes and Layout BasicsStub Series Terminated Logic (SSTL_18)

For exam ple, ma ke all nod es accessible, at least for the key signals (clocks, strobes,

comm and s, and control), and do n ot use b lind or b uried vias. When possible, keep

signals on an outer layer an d p lace sma ll test points in-line rather than adding stubs to

traces (see Figure 3). Where app licable, use term ination resistors as test poin ts.

Figure 3: Typical Rout ing of Test Points for DDR2 Devices

If inne r layers are requ ired for rou ting, try to include the te st poin ts at on e of the existing

vias. Staggering n odes b etween the to p- an d bo ttom -sides of the PCB will help ma ke

room for test po ints. For examp le, place the t est poin t for address (A2) near on e device

an d p lace the test p oint for add ress (A0) near a d ifferent device.

Stub Series Terminat ed Logic (SSTL_18)

DDR2 uses SSTL_18 logic for a ll inp ut s. A simp le way to d escribe SSTL is tha t each inp ut

is a differential receiver with o ne leg tied to a reference voltage (VREF). When the voltage

offset betwee n VREF an d th e inpu t voltage exceeds the th reshold of the inp ut receiver, the

differen tial receiver will drive to either a HIGH o r LOW logic level.

Due to the fast switching requ iremen ts of DDR2, the DC th reshold is 125m V. This mean s

that when the inpu t to the receiver app roaches VREF + 125mV or VREF - 125m V, th e d evice

will start t o d etec t a logic level. By specification, VREF equ als 50 percent o f VDDQ and it

m ust track th e slight variation s in VDDQ to within 1 pe rcent of the no m inal value. The AC

port ion of VREF is limited to 2 pe rcent of the DC n om inal value.

As can be seen in Figure 4 on page 6, it is imp erative to keep VREF free of noise an d within

the specified value s. If VREF is noisy or is not cen tered at VDDQ/ 2, the switching points of

the receiver may cha nge an d m ay drastically affect the inpu t receivers setup an d h old

timing in ad dition to o ther DRAM timing.

Test Points

84-ball outline (or 92-ball outline)

Routingdifferential clocks on int ernallayer, but bringing each signal out t o t estpoint by a via

Layer 4

Top layer, layer 3, layer 4 andbottom layer shown

Example of (RAS#) trace from4 DRAMs through a test point

Example has 4 (92-ball) DDR2 DRAM2 per side with t est point s

Front Side
http://-/?-http://-/?-


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TN-47-20: Point-to-Point Package Sizes and Layout BasicsGeneral DDR2 Layout Guidelines

Figure 4: Setup and Hold M argins can Signi f icant ly be Reduced When VREF is Noisy

General DDR2 Layout Guidelines

A successful layout req uires the u se of good design ru les, an un derstan ding of critical

device param eters, and t he verification of signa l inte grity and tim ing throu gh

simulation.

The following top ics should fam iliarize the layout en gine er with the prim ary factors to

consider wh en start ing a new DDR2 project.

Match the I/O Drive

DDR2 SDRAM ha s two o utp ut drive levels: full drive strength an d red uced drive strength.

The full drive h as a target outp ut imp edance of about 18 and th e reduced drive has a

target im ped an ce of app roximately 40. This feat ure is available on all DDR2 den sities

and configuration s (x4, x8, and x16). Most po int-to-p oint layouts will use th e 40 value

since it best ma tches the target trace imp edan ce of app roximately 40 to 55.

Keep the t races short

When developing the PCB floor plan, the p roxim ity of the DDR2 device to the m em ory

cont roller is an im porta nt factor. If the m em ory is close to t he co ntro ller, the layout is

usua lly easier. For exam ple, with short traces th e add ress, cont rol, an d com m an d signals

m ay not requ ire both para llel (RTT) and series (RS) terminat ion, or at worst case, on ly

require a sma ll series resistor (RS) of abo ut 10 or less. This RS is not for imped ance

match ing, but is used to dam pen the signals. If the RTT resistors are no t required, this

frees up more b oard space for signal routing and eliminates th e n eed for a VTT power

0.90

1.00

0.80

0.70

0.60

1.10

1.20

VIN(DC)= 1,025mV

VIN(DC)

= 775mV

VREF(DC)

With the ideal conditions, the receiver wil l detect a high logic level at 1,025mV and a low logic level at 775mV.

VREF

VIN

Input to array

VTHRESHOLD = 125mV

VREF(AC) NOISE VREF(DC)specif ied limts VIN(DC)levels at nominal condtions

If VREFdoes not track VDDQ or if VREFis noisy, the receiver may detect logic levels at different points.

There could also be timing skew.

With VREF at 900mV (expected)> VIN(HIGH) will be (900mV + 125mV) or 1,025mV> VIN(LOW) will be (900mV - 125mV) or 775mV

With VREF at 950mV (noisy)> VIN(HIGH) will be (950mV + 125mV) or 1,075mV> VIN(LOW) will be (950mV - 125mV) or 825mV

1.10

1.00

~50ps of skew

VIN(DC) = 1.075V

VIN(DC) = 1.025V

Input signal slew rate ~1V/ns


7/12



source an d d edicated voltage plan e. With longer traces it is likely that using a p ull-up

resistor, RTT to VTT (VDDQ/ 2), will be requ ired. To avoid th e use of RTT termination on

high-speed DDR2 the ta rget address trace length sh ould b e 2.5in (63.5mm )or less.

Use the Correct TopologyNot all po int-to-p oint designs use only one me m ory device for each con troller; ma ny

layouts will use two or four m em ory devices. If four x16 devices are used in p arallel, this

equates to a 64-bit data bus. In this scenario, the data and strobe signals are point-to-

single-point, bu t the address, control, and comm and signals are point-to-four-point.

When th e con troller is driving mo re than on e device, a m atche d TREE type rou ting

pattern sh ould be used. See Figure 5 for an examp le of TREE rout ing.

The ad vantage of a TREE topology is tha t all trace segmen ts are b alanced for each

path . The tota l trace length to the first DRAM is iden tical to that of the last DRAM, and

flight times for each DRAM are also the sa m e. Not only does this he lp with m atchin g

timin g, it also he lps with tra ns m ission line effects by con trolling reflections. In TREE

topo logies, the first segme nt is typically the longest, an d a s the segm en ts get closer to

the DRAM, they get sh orte r.

Figure 5: M atched TREE Rout ing Pat tern

DRAM

DRAM

DRAM

DRAM

VTT

MemoryController TL1

TL2

TL2

TL3

TL4

TL4

TL5

TL5

TL5

TL5

TL4

TL4

TL3

TL6

1st TTotal length = TL1 + TL2

2ndTTotal length = TL3 + TL4

2ndTTotal length = TL3 + TL4

TL5 shouldbe matched for each DRAM

If RTT is required,TL6 shouldbe about 0.1in t o 0.5 in.


8/12



Watch Out for Crosstalk

All DDR2 signa ling is SSTL_18, which m ean s the receivers are op timized to switch wh en

they detect a very sma ll inpu t variation from the reference voltage (VREF). The VIN(DC)

levels are sp ecified a s VREF 125mV. If a fast switching da ta line is cou pled with a ne arby

add ress or con trol line, the resu lt could be system failure du e to crosstalk. Crosstalk canoccur even with sh ort pa rallel traces.

DDR2 sup po rts redu ced drive I/O, which will have slightly slower edge rates. Slower ed ge

rates will help to con trol crosstalk. It is also im po rtan t to keep ad equ ate spa cing between

signa ls tha t run pa rallel, an d to p rovide a good solid reference p lane so the re is a current

return path.

M ethods of Termination

Three signal types are u sed o n DDR2 mem ory: true d ifferential signa ls (clocks), bidirec-

tional signa ls (data), an d single-end ed signa ls (address/ com m an d/ cont rol). Each type

of signal has u nique term ination requiremen ts.

True Dif ferent ial Signals (Clocks)

The clocks (CK and CK#) are a differential signa l and shou ld be term inated at th e en d of

the line be tween CK an d CK# with a 100120 resistor. If m ore th an on e DRAM is

placed, the n th e clock pair m ay be split into several segmen ts. In th e case of mu ltiple

segmen ts, the term ination resistor shou ld be placed at th e first split, or the resistor value

should be increased and a resistor placed at the en d of each segmen t.


9/12



Figure 6: DRAM Clock Rout ing and Placement of the Terminat ion Resistor(s)

Bidirectional Signals (Data)

The I/ O type sign als includ e data (DQ0DQ15), strobes (DQS, RDQS, LDQS, UDQS,

DQS#, RDQS#, LDQS#, UDQS#), an d d ata m ask (DM, LDM, UDM). The se signa ls all

sup port ODT equivalent values of 50, 75, or 150. With the u se of ODT and a reason -

able trace length, add itional term ination may n ot b e n eeded. For these signals the crit-ical factor is the timing within an d bet ween each byte lan e. Depend ing, of course, on th e

timing bu dget for each d esign. A good startin g point is keeping all traces within a byte

lane bet ween 1520ps. This includ es all data line s and the a ssociated strobe. Tim ing

between different byte lanes can usu ally be a b it more relaxed an d are typically within

6070ps.

Note: Values can vary between designs and will be dependant on actual controller require-

ments an d timing budget.

TL3

TL2

TL2

TL3

TL1CK

CK#

ClockGenerator

DRAMCK

CK#

DRAMCK

CK#

R = 100

ClockGenerator

DRAMCK

CK#

DRAMCK

CK#

CK

CK#

TL3

TL2

TL2

TL3

TL1

R = 200

R = 200

Optoin 1Place the t erminati on resisto r just

before the split and use about100120 value

Optoin 2Increase the resistor size and placethe termination at t he end of thelast trace segment


10/12


TN-47-20: Point-to-Point Package Sizes and Layout BasicsConclusion

Figure 7: Lengt h M atching (Tim ing) Betw een Individual Bits and Byte Lanes 32-Bit Bus Example

Notes: 1. The values for each design will vary due to controller requirement s, device speed grades,

and actual t iming budget.

Single-Ended Signals (Address/Command)

Address, comm an d, and con trol signa ls are single-end ed an d are driving on ly from the

controller. Command (RAS#, CAS#, WE#) and control (CS#, ODT, CKE) signals are

latched int o th e DRAM on each clock edge. Som e con trollers will run in 2T mod e. In 2T

mo de, the a ddress signa ls are driven for two clock cycles but o nly latche d on the secon d

rising clock edge. This allows th e signals to settle out before the y are latched into th e

DRAM. 2T addressing can also help to redu ce the n eed for termin ation since th e

switching time s are cut in h alf. Note that con trol signals shou ld always run in 1T mod e.

As described earlier, the ad dress, com m an d, and con trol signa ls m ay not require any

term ination if the top ology is opt imized and th e trace length s are kept arou nd 2.5in

(63.5m m ) or less. It is best to simu late all nets to determ ine the b est m etho d of termina -

tion and the exact termination values.

Conclusion

Using DDR2 SDRAM devices can he lp alleviate t he com plexity of the PCB floor p lan with

its ultra-sma ll pa ckage size, comm on b allout s, and th e nee d for fewer term ination resis-

tors. DDR2 techn ology sup ports two prim aryelectrical ball arrays on e for x4/ x8 an d

one for x16. The electrical ball array for th e x4/ x8 con figurations is a stan dard 60-ball

array, or 60-ba ll plu s ou triggers (68 ba lls tota l) for the lon ger pa ckage sizes. The x16

configuration uses th e stan dard 84-ball array, or 84-ball array plus ou triggers (92 balls

x16 DRAM (B)

High Byte (DRAM A)

Low Byte (DRAM A)

High Byte (DRAM B)

Low Byte (DRAM B)

x16 DRAM (A)

MemoryController

As expected anddue t o nor mal PCB limit ations,each trace may be a slightly different length between

the memory controller and the DRAM.

General guidelines (starting point):Traces wit hin each byte lane should not have a delta between each ot her of more than 1520ps.From byte lane to byte lane there may be up to 6070ps of difference.

Data

Data

Data

Data

Data

Data

Data

Data


11/12

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M icron, the M logo, and the M icron logo are t rademarks of M icron Technology, Inc. All other t rademarks are the propert y oftheir respective ow ners.

TN-47-20: Point-to-Point Package Sizes and Layout BasicsConclusion


total) for th e extend ed p ackage sizes. Also, with th e dyna mic sup port of ODT on all I/O

lines an d redu ced ou tpu t drive levels, such PCB designs ma y not require add ition al

term ination to e nsu re good signa l quality. The com bina tion of comp act ball arrays,

min iature package sizes, an d less term ination p lacemen ts all free up b oard spa ce for

routing traces.

Most PCB layouts u sing DDR2 SDRAM devices sh ou ld ha ve app roximat ely 4055 trace

imp edan ces. Where signals are routed to m ore than on e DRAM, balanced TREE trace

segmen ts should b e used . If a pa rallel termination resistor is ne eded toVTT, it is best to

place it at the end of the line or o n a short segment of its own.

If the designer u nd erstan ds th e basic prin ciples of DDR2 techn ology, follows the recom -

me nd ations of this technical note, and com pletes a full simulation, th e resulting design

should be a success.

For a dd ition al DDR2 inform ation, a nd for the latest data sheets, refer to Microns Web

site at www.micron.com
mailto:[email protected]://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/http://www.micron.com/mailto:[email protected]


12/12


TN-47-20: Point-to-Point Package Sizes and Layout BasicsRevision History

Revision History

Rev A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/ 06

Ini tia l release

dynamic ram

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