dsplab manual

8/6/2019 Dsplab Manual

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DIGITAL SIGNAL PROCESSING LAB MANUAL

DEPARTMENT OF ELECTRONICS &COMMUNICATION ENGINEERING


IVYEAR I SEMESTER (ECE)

SSN ENGINEERING COLLEGEONGOLE

DIGITAL SIGNAL PROCESSING LAB (IV-I SEM)

DEPT OF ECE, SSN ENGG COLLEGE, ONGOLE.


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INDEX

1. To Study the Architecture of DSP chips-TMS 320C 6713 DSPProcessor

2. To verify the Linear convolution3. To verify the Circular convolution4. To design FIR Filter (LP/HP) Using Windowing technique

a. Rectangular windowb. Triangular windowc. Kaiser window

5. To design IIR Filter(LP/HP)

6. N-point FFT algorithm7. MATLAB program to generate sum of sinusoidal signals8. Sine wave generation using DSP Kit9. Power Spectral Density of a sinusoidal signals10. FFT of 1-D signal plot

EXP - 1 : INTRODUCTION TO DSP PROCESSORS

A signal can be defined as a function that conveys information, generally about the state or behavior of a physical system. There are two basic types of signals viz Analog (continuous time



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signals which are defined along a continuum of times) and Digital (discrete-time). Remarkably, underreasonable constraints, a continuous time signal can be adequately represented by samples, obtainingdiscrete time signals. Thus digital signal processing is an ideal choice for anyone who needs theperformance advantage of digital manipulation along with todays analog reality.Hence a processor which is designed to perform the special operations(digital manipulations) on the

digital signal within very less time can be called as a Digital signal processor. The difference between a DSP processor, conventional microprocessor and amicrocontroller are listed below.

Microprocessor or General Purpose Processor such as Intel xx86 or Motorola 680xx family Contains only CPU No RAM No ROM No I/O ports No Timer

Microcontroller such as 8051 family Contains CPU RAM ROM I/O ports Timer & Interrupt circuitry

Some Micro Controllers also contain A/D, D/A and Flash Memory

DSP Processors such as Texas instruments and Analog Devices Contains CPU RAM

ROM I/O ports Timer

Optimized for fast arithmetic Extended precision Dual operand fetch Zero overhead loop Circular buffering

The basic features of a DSP Processor are

Feature UseFast-Multiply accumulate Most DSP algorithms, including

filtering, transforms, etc. aremultiplication- intensive

Multiple access memory architecture Many data-intensive DSP operationsrequire reading a program instruction and



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multiple data items during each instructioncycle for best performance

Specialized addressing modes Efficient handling of data arrays and first-in, first-out buffers in memory

Specialized program control Efficient control of loops for many

iterative DSP algorithms. Fast interrupthandling for frequent I/O operations.

On-chip peripherals and I/O interfaces On-chip peripherals like A/D convertersallow for small low cost systemdesigns.Similarly I/O interfaces tailoredfor common peripherals allow cleaninterfaces to off-chip I/O devices.

ARCHITECTURE OF 6713 DSP PROCESSOR

This chapter provides an overview of the architectural structure of the TMS320C67xx DSP,which comprises the central processing unit (CPU), memory, and on-chip peripherals. The C67xEDSPs use an advanced modified Harvard architecture that maximizes processing power with eightbuses. Separate program and data spaces allow simultaneous access to program instructions and data,providing a high degree of parallelism. For example, three reads and one write can be performed in asingle cycle. Instructions with parallel store and application-specific instructions fully utilize this



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architecture. In addition, data can be transferred between data and program spaces. Such Parallelismsupports a powerful set of arithmetic, logic, and bit-manipulation operations that can all be performedin a single machine cycle. Also, the C67xx DSP includes the control mechanisms to manageinterrupts, repeated operations, and function calling.

Fig. 1 Block Diagram of TMS320C6713

The C67xx DSP architecture is built around eight major 16-bit buses (four program/data buses andfour address buses):

The program bus (PB) carries the instruction code and immediate operands from programmemory.

Three data buses (CB, DB, and EB) interconnect to various elements, such as the CPU, dataaddress generation logic, program address generation logic, on-chip peripherals, and datamemory.

The CB and DB carry the operands that are read from data memory.



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The EB carries the data to be written to memory. Four address buses (PAB, CAB, DAB, and EAB) carry the addresses needed for instruction

execution.

The C67xx DSP can generate up to two data-memory addresses per cycle using the two auxiliary

register arithmetic units (ARAU0 and ARAU1). The PB can carry data operands stored in programspace (for instance, a coefficient table) to the multiplier and adder for multiply/accumulate operationsor to a destination in data space for data move instructions (MVPD and READA). This capability, inconjunction with the feature of dual-operand read, supports the execution of single-cycle, 3-operandinstructions such as the FIRS instruction. The C67xx DSP also has an on-chip bidirectional bus foraccessing on-chip peripherals. This bus is connected to DB and EB through the bus exchanger in theCPU interface. Accesses that use this bus can require two or more cycles for reads and writes,depending on the peripherals structure.

Central Processing Unit (CPU)

The CPU is common to all C67xE devices. The C67x CPU contains: 40-bit arithmetic logic unit (ALU) Two 40-bit accumulators Barrel shifter 17 17-bit multiplier 40-bit adder Compare, select, and store unit (CSSU) Data address generation unit Program address generation unit

Arithmetic Logic Unit (ALU)

The C67x DSP performs 2s-complement arithmetic with a 40-bit arithmetic logic unit (ALU) andtwo 40-bit accumulators (accumulators A and B). The ALU can also perform Boolean operations. TheALU uses these inputs:

16-bit immediate value 16-bit word from data memory 16-bit value in the temporary register, Two 16-bit words from data memory 32-bit word from data memory 40-bit word from either accumulator

The ALU can also function as two 16-bit ALUs and perform two 16-bit operations simultaneously.



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Fig 2. ALU Unit

Accumulators

Accumulators A and B store the output from the ALU or the multiplier/adder block. They can alsoprovide a second input to the ALU; accumulator A can be an input to the multiplier/adder. Eachaccumulator is divided into three parts:

Guard bits (bits 3932) High-order word (bits 3116)

Low-order word (bits 150)

Instructions are provided for storing the guard bits, for storing the high- and the loworderaccumulator words in data memory, and for transferring 32-bit accumulator words in or out of datamemory. Also, either of the accumulators can be used as temporary storage for the other.

Barrel Shifter



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The C67x DSP barrel shifter has a 40-bit input connected to the accumulators or to datamemory (using CB or DB), and a 40-bit output connected to the ALU or to data memory (using EB).The barrel shifter can produce a left shift of 0 to 31 bits and a right shift of 0 to 16 bits on the inputdata. The shift requirements are defined in the shift count field of the instruction, the shift count field(ASM) of status register ST1, or in temporary register T (when it is designated as a shift count

register).

The barrel shifter and the exponent encoder normalize the values in an accumulator in a singlecycle. The LSBs of the output are filled with 0s, and the MSBs can be either zero filled or signextended, depending on the state of the sign-extension mode bit (SXM) in ST1. Additional shiftcapabilities enable the processor to perform numerical scaling, bit extraction, extended arithmetic, andoverflow prevention operations.

Multiplier/Adder Unit

The multiplier/adder unit performs 17 _ 17-bit 2s-complement multiplication with a 40- bit

addition in a single instruction cycle. The multiplier/adder block consists of several elements: amultiplier, an adder, signed/unsigned input control logic, fractional control logic, a zero detector, arounder (2s complement), overflow/saturation logic, and a 16-bit temporary storage register (T).

The multiplier has two inputs: one input is selected from T, a data-memory operand, oraccumulator A; the other is selected from program memory, data memory, accumulator A, or animmediate value. The fast, on-chip multiplier allows the C54x DSP to perform operations efficientlysuch as convolution, correlation, and filtering. In addition, the multiplier and ALU together executemultiply/accumulate (MAC) computations and ALU operations in parallel in a single instruction cycle.This function is used in determining the Euclidian distance and in implementing symmetrical andLMS filters, which are required for complex DSP algorithms. See section 4.5, Multiplier/Adder Unit,on page 4-19, for more details about the multiplier/adder unit.



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Fig 3. Multiplier/Adder Unit

These are the some of the important parts of the processor and you are instructed to go throughthe detailed architecture once which helps you in developing the optimized code for the requiredapplication.



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EXP-2 Linear Convolution

AIM:

To verify Linear Convolution.

EQUIPMENTS:

Operating System Windows XPConstructor- SimulatorSoftware - CCStudio 3 & MATLAB

THEORY:

Convolution is a formal mathematical operation, just as multiplication, addition, and

integration. Addition takes two numbers and produces a third number, while convolution takes twosignals and produces a third signal. Convolution is used in the mathematics of many fields, such asprobability and statistics. In linear systems, convolution is used to describe the relationship betweenthree signals of interest: the input signal, the impulse response, and the output signal.

In this equation, x1(k), x2(n-k) and y(n) represent the input to and output from the system at

time n. Here we could see that one of the input is shifted in time by a value every time it is multiplied

with the other input signal. Linear Convolution is quite often used as a method of implementingfilters of various types.

PROGRAM:// Linear convolution program in c language using CCStudio

#includeint x[15],h[15],y[15];main(){

int i,j,m,n;printf("\n enter value for m");scanf("%d",&m);printf("\n enter value for n");scanf("%d",&n);printf("Enter values for i/p x(n):\n");for(i=0;i


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printf("Enter Values for i/p h(n) \n");for(i=0;i


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EXP -3 : Circular Convolution

AIM

To verify Circular Convolution.

EQUIPMENTS:


THEORY

Circular convolution is another way of finding the convolution sum of two input signals. Itresembles the linear convolution, except that the sample values of one of the input signals is folded

and right shifted before the convolution sum is found. Also note that circular convolution could also befound by taking the DFT of the two input signals and finding the product of the two frequency domainsignals. The Inverse DFT of the product would give the output of the signal in the time domain whichis the circular convolution output. The two input signals could have been of varying sample lengths.But we take the DFT of higher point, which ever signals levels to. For eg. If one of the signal is oflength 256 and the other spans 51 samples, then we could only take 256 point DFT. So the output ofIDFT would be containing 256 samples instead of 306 samples, which follows N1+N2 1 where N1& N2 are the lengths 256 and 51 respectively of the two inputs. Thus the output which should havebeen 306 samples long is fitted into 256 samples. The 256 points end up being a distorted version ofthe correct signal. This process is called circular convolution.

PROGRAM:

/* program to implement circular convolution */#includeint m,n,x[30],h[30],y[30],i,j, k,x2[30],a[30];void main(){printf(" Enter the length of the first sequence\n");scanf("%d",&m);printf(" Enter the length of the second sequence\n");

scanf("%d",&n);printf(" Enter the first sequence\n");for(i=0;i


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The circular convolution is18 16 10 16

Model Graph :

EXP 4 FIR Filter Design Using Windows

AIM

To verify FIR Filter Design Using Windows Techniques.



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EQUIPMENTS:

Operating System Windows XPSoftware - MATLAB

PROGRAM :

I) Rectangular Window

%Program

close all;clear all;clc;

n=64;fs=1000;x=rectwin(n+1);[b a]=fir1(n,200*2/fs,x);[h w]=freqz(b,a,512);subplot(2,2,1)plot(w*fs/(2*pi),abs(h));title('rectwin lowpass filter');[b a]=fir1(n,[100 250]*2/fs,x);[h w]=freqz(b,a,512);subplot(2,2,2)

plot(w*fs/(2*pi),abs(h));title('rectwin bandpass filter');[b a]=fir1(n,200*2/fs,'high',x);[h w]=freqz(b,a,512);subplot(2,2,3)plot(w*fs/(2*pi),abs(h));title('rectwin highpass filter');[b a]=fir1(n,[100 250]*2/fs,'stop',x);[h w]=freqz(b,a,512);

subplot(2,2,4)plot(w*fs/(2*pi),abs(h));title('rectwin bandstop filter');

Result :



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II) Traingular Window

% Program

close all;clearall;clc;



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n=64;fs=1000;x=triang(n+1);[b a]=fir1(n,200*2/fs,x);

[h w]=freqz(b,a,512);subplot(2,2,1)plot(w*fs/(2*pi),abs(h));title('triang lowpass filter');[b a]=fir1(n,[100 250]*2/fs,x);[h w]=freqz(b,a,512);subplot(2,2,2)plot(w*fs/(2*pi),abs(h));title('triang bandpass filter');

[b a]=fir1(n,200*2/fs,'high',x);[h w]=freqz(b,a,512);subplot(2,2,3)plot(w*fs/(2*pi),abs(h));title('triang highpass filter');[b a]=fir1(n,[100 250]*2/fs,'stop',x);[h w]=freqz(b,a,512);subplot(2,2,4)plot(w*fs/(2*pi),abs(h));title('triang bandstop filter');

Result :



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III) Kaiser Window



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%Program

close all;

clear all;clc;n=64;fs=1000;x=kaiser(n+1);[b a]=fir1(n,200*2/fs,x);[h w]=freqz(b,a,512);subplot(2,2,1)plot(w*fs/(2*pi),abs(h));title('kaiser lowpass filter');

[b a]=fir1(n,[100 250]*2/fs,x);[h w]=freqz(b,a,512);subplot(2,2,2)plot(w*fs/(2*pi),abs(h));title('kaiser bandpass filter');[b a]=fir1(n,200*2/fs,'high',x);[h w]=freqz(b,a,512);subplot(2,2,3)plot(w*fs/(2*pi),abs(h));title('kaiser highpass filter');

[b a]=fir1(n,[100 250]*2/fs,'stop',x);[h w]=freqz(b,a,512);subplot(2,2,4)plot(w*fs/(2*pi),abs(h));title('kaiser bandstop filter');

Result :



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AIM

To verify IIR Filter Design .

EQUIPMENTS:


PROGRAM :

I) Low Pass Filter

% Program

clear all;close all;clc;Fs = 100;t = (1:100)/Fs;s1 = sin(2*pi*t*5); s2=sin(2*pi*t*15); s3=sin(2*pi*t*30);s = s1+s2+s3;figure;plot(t,s);xlabel('Time (seconds)'); ylabel('Time waveform');title('input signal');

[b,a] = ellip(4,0.1,40,20*2/Fs);[H,w] = freqz(b,a,512);figureplot(w*Fs/(2*pi),abs(H));xlabel('Frequency (Hz)'); ylabel('Mag. of frequency response');title('frequency responseof the filter');grid;sf = filter(b,a,s);figure

plot(t,sf);xlabel('Time (seconds)');ylabel('Time waveform');title('filtered signal');axis([0 1 -1 1]);

S = fft(s,512);



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SF = fft(sf,512);w = (0:255)/256*(Fs/2);figureplot(w,abs([S(1:256)']));xlabel('Frequency (Hz)'); ylabel('Mag. of Fourier transform');

title('Fourier Transform of input signal');grid;figureplot(w,abs([SF(1:256)']));xlabel('Frequency (Hz)'); ylabel('Mag. of Fourier transform');title('Fourier Transform of Filtered signal');grid;

Results :



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II) High pass Filter

% Program

clear all;close all;clc;Fs = 100;t = (1:100)/Fs;s1 = sin(2*pi*t*5); s2=sin(2*pi*t*15); s3=sin(2*pi*t*30);s = s1+s2+s3;figure;plot(t,s);xlabel('Time (seconds)'); ylabel('Time waveform');title('input signal');

[b,a] = ellip(4,0.1,40,20*2/Fs,'high');[H,w] = freqz(b,a,512);figureplot(w*Fs/(2*pi),abs(H));xlabel('Frequency (Hz)'); ylabel('Mag. of frequency response');title('frequency responseof the filter');grid;

sf = filter(b,a,s);figureplot(t,sf);xlabel('Time (seconds)');ylabel('Time waveform');title('filtered signal');axis([0 1 -1 1]);

S = fft(s,512);SF = fft(sf,512);

w = (0:255)/256*(Fs/2);figureplot(w,abs([S(1:256)']));xlabel('Frequency (Hz)'); ylabel('Mag. of Fourier transform');title('Fourier Transform of input signal');grid;figureplot(w,abs([SF(1:256)']));



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xlabel('Frequency (Hz)'); ylabel('Mag. of Fourier transform');title('Fourier Transform of Filtered signal');grid;

Results :



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EXP 6 N-Point FFT

AIM:

To verify Fast Fourier Transform.

EQUIPMENTS:

Operating System - Windows XPConstructor - SimulatorSoftware - MATLAB

PROGRAM:

%fast fourier transformclc;

clear all;close all;tic;x=input('enter the sequence');n=input('enter the length of fft');%compute fftdisp('fourier transformed signal');X=fft(x,n)



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subplot(1,2,1);stem(x);title('i/p signal');xlabel('n --->');ylabel('x(n) -->');grid;subplot(1,2,2);stem(X);

title('fft of i/p x(n) is:');xlabel('Real axis --->');ylabel('Imaginary axis -->');grid;

RESULT



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EXP 7 Sum of Sinusoidal Signals



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AIM:

To verify Sum of Sinusoidal Signals using MATLAB

EQUIPMENTS:

Operating System Windows XPConstructor- SimulatorSoftware - MATLAB

THEORY:

To generate fourier series of a signal by observing sum of sinusoidal signals & observing gibbsphenomenon effect.

PROGRAM:

% sum of sinusoidal signalsclc;clear all;close all;tic;%giving linear spacest=0:.01:pi;% t=linspace(0,pi,20);%generation of sine signalsy1=sin(t);

y2=sin(3*t)/3;y3=sin(5*t)/5;y4=sin(7*t)/7;y5=sin(9*t)/9;y = sin(t) + sin(3*t)/3 + sin(5*t)/5 + sin(7*t)/7 + sin(9*t)/9;plot(t,y,t,y1,t,y2,t,y3,t,y4,t,y5);legend('y','y1','y2','y3','y4','y5');title('generation of sum of sinusoidal signals');grid;ylabel('---> Amplitude');xlabel('---> t');toc;

RESULT:



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EXP 8 Sine wave generation using DSP Kit



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AIM

To verify Sine wave generation using DSP Kit.

EQUIPMENTS:


PROGRAM :

# include < stdio.h>

#include

#includeFloat y[1000],pi=3.14;

main()

{

int i,j,t,f,fs;

fs=1000;

f=50;

for(t=0;t


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EXP 9 Power Spectral Density



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AIM

To verify the Power Spectral Density of the 1-D signal..

EQUIPMENTS:


PROGRAM :

clearall;close all;clc

fs=1000;t=0:1/fs:10;fo = 10; f1 = 400; % Start at 10Hz, go up to 400Hzy = chirp(t,fo,10,f1,'logarithmic');SPECGRAMDEMO(y,fs)

RESULT :



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EXP 10 FFT of 1-D Signal



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AIM

To verify FFT of the 1-D signal..

EQUIPMENTS:


PROGRAM :

clc;clear all;close all;fs=1000t=0:2*pi/fs:2*pi;y = sin(25*t) + sin(300*t) + sin(150*t) + sin(250*t) + sin(400*t);plot(t,y);legend('y','y1','y2','y3','y4','y5');title('generation of sum of sinusoidal signals');grid;ylabel('---> Amplitude');xlabel('---> t');Y = fft(y);

Y(1)=[];n=length(Y);power = abs(Y(1:floor(n/2))).^2;nyquist = fs/2;freq = (1:n/2)/(n/2)*nyquist;plot(freq,power)xlabel('FREQUENCY')ylabel('POWER');title('FFT of 1-D Signal')

RESULT :



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