dsPIC33EVXXXGM00X/10XdsPIC33EVXXXGM00X/10X

Flash Programming Specification

1.0 DEVICE OVERVIEWThis document defines the programming specificationfor the dsPIC33EVXXXGM00X/10X 16-bit DigitalSignal Controller (DSC) families. This programmingspecification is required only for those developingprogramming support for the following devices:

Customers only using these devices for applicationdevelopment should use development tools thatalready provide support for device programming.

Topics covered include:

• Section 1.0 “Device Overview”• Section 2.0 “Programming Overview”• Section 3.0 “Device Programming – ICSP”• Section 4.0 “Device Programming – Enhanced

ICSP”• Section 5.0 “Programming the Programming

Executive to Memory”• Section 6.0 “The Programming Executive”• Section 7.0 “Device ID”• Section 8.0 “Checksum Computation”• Section 9.0 “AC/DC Characteristics and

Timing Requirements”

2.0 PROGRAMMING OVERVIEWThere are two methods of programming that arediscussed in this programming specification:

• In-Circuit Serial Programming™ (ICSP™)• Enhanced In-Circuit Serial Programming

The ICSP programming method is the most directmethod to program the device; however, it is also theslower of the two methods. It provides native, low-levelprogramming capability to erase, program and verifythe device.

The Enhanced ICSP protocol uses a faster method thattakes advantage of the Programming Executive (PE),as illustrated in Figure 2-1. The PE provides all thenecessary functionality to erase, program and verifythe chip through a small command set. The com-mand set allows the programmer to program adsPIC33EVXXXGM00X/10X device without dealingwith the low-level programming protocols.

FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™

This programming specification is divided into two majorsections that describe the programming methods inde-pendently. Section 3.0 “Device Programming – ICSP”describes the ICSP method. Section 4.0 “DeviceProgramming – Enhanced ICSP” describes theEnhanced ICSP method.

• dsPIC33EV64GM002 • dsPIC33EV256GM002• dsPIC33EV64GM004 • dsPIC33EV256GM004• dsPIC33EV64GM006 • dsPIC33EV256GM006• dsPIC33EV64GM102 • dsPIC33EV256GM102• dsPIC33EV64GM104 • dsPIC33EV256GM104• dsPIC33EV64GM106 • dsPIC33EV256GM106

• dsPIC33EV128GM002• dsPIC33EV128GM004• dsPIC33EV128GM006• dsPIC33EV128GM102• dsPIC33EV128GM104• dsPIC33EV128GM106

dsPIC33EVXXXGM00X/10X

Programmer ProgrammingExecutive

On-Chip Memory

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2.1 Required ConnectionsThese devices require specific connections for pro-gramming to take place. These connections includepower, VCAP, MCLR and one programming pin pair(PGEDx/PGECx). Table 2-1 describes these connec-tions (refer to the specific device data sheet for pindescriptions and power connection requirements).

2.2 Power RequirementsAll dsPIC33EVXXXGM00X/10X devices, power theircore digital logic at a nominal 1.8V. All devices in thedsPIC33EVXXXGM00X/10X families incorporate anon-chip regulator that allows the device to run its corelogic from VDD.

The regulator provides power to the core from the VDDpins. A low-ESR capacitor (such as ceramic or tantalum)must be connected to the VCAP pin (see Figure 2-2 and

Table 2-1). This maintains the stability of the regulator.The specifications for core voltage and capacitance arelisted in Section 9.0 “AC/DC Characteristics andTiming Requirements”.

FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR

TABLE 2-1: PINS USED DURING PROGRAMMING

VDD

VCAP

VSS

dsPIC33EVXXXGM0XX/10X

CEFC

5.0V

(10 F typ)

AVDD

AVSS

Pin Name Pin Type Pin Description

MCLR I Programming EnableVDD and AVDD(1) P Power Supply(1)

VSS and AVSS(1) P Ground(1)

VCAP P CPU Logic Filter Capacitor ConnectionPGECx I Programming Pin Pair: Serial Clock PGEDx I/O Programming Pin Pair: Serial Data Legend: I = Input O = Output P = PowerNote 1: All power supply and ground pins must be connected, including AVDD and AVSS.

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2.3 Pin DiagramsFigure 2-3 through Figure 2-5 provide the pin diagramsfor the dsPIC33EVXXXGM00X/10X families. The pinsthat are required for programming are listed inTable 2-1 and are indicated in bold text in the figures.Refer to the appropriate device data sheet for completepin descriptions.

2.3.1 PGECx AND PGEDx PIN PAIRSAll devices in the dsPIC33EVXXXGM00X/10X familieshave three separate pairs of programming pins, labeledas PGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3. Any one of these pin pairs may be used fordevice programming by either ICSP or Enhanced ICSP.Unlike voltage supply and ground pins, it is not neces-sary to connect all three pin pairs to program thedevice. However, the programming method must useboth pins of the same pair.

FIGURE 2-3: PIN DIAGRAMS

28-Pin SPDIP/SOIC/SSOP

MCLR AVDDAVSS

RB15

PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0 RB14RB13

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2 RB12

PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3 RB11RB10

RA2

RA3 VSS

RB4 RB9

RA4 RB8

VDD RB7PGED2/SDA1/RP37/RB5 PGEC2/SCL1/RP38/RB6

VSS

RA0

RA1

28-Pin QFN-S

RB

8R

B7

PGEC

2/SC

L1/R

P38/

RB6

PGED

2/SD

A1/R

P37/

RB5VD

D

RA

4R

B4

RB13RB12

RB11

RB10

VCAPVSSRB9

RB1

4

RB1

5

AVSS

AVD

D

MC

LR

PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0

PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

VSSRA2

RA3

PGEC1/OA1IN+/AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2

PGED1/OA1IN-/AN5/C1IN1-/CTMUC/RP35/RB3

RA0

RA1

1 28

2 27

3 26

4 25

5 24

6 23

7 22

8 21

9 20

10 19

11 18

12 17

13 16

14 15

dsPI

C33

EV12

8GM

002

dsPI

C33

EV64

GM

002

dsPI

C33

EV25

6GM

002PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

VCAP

28 27 26 25 24 23 22

18

17

16

15

20

19

21

3

4

5

7

1

2

6

8 9 10 11 12 13 14

dsPIC33EV64GMX04dsPIC33EV128GMX04dsPIC33EV256GM002

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FIGURE 2-4: PIN DIAGRAMS (CONTINUED)

44-Pin TQFP/TLA/QFN

dsPIC33EV64GMX04dsPIC33EV128GMX04dsPIC33EV256GMX04

44 43 42 41 40 39 38 37 36 35 341 33

2 32

3 31

4 305 296 287 278 269 2510 2411 23

12 13 14 15 16 17 18 19 20 21 22

RB

8R

A10

RB13 PGEC1/OA1IN+AN4/C1IN3-/C1IN1+/C2IN3-/RPI34/RB2PGED1/OA1IN-/AN5/C1IN1-/CTMU/RP35/RB3RC0RC1RC2VDDVSSRA2RA3

RA8RB4

RA

7R

B14

RB

15AV

SS

AVD

D

MC

LR RA

0R

A1

PGED

3/O

A2IN

-/AN

2/C

2IN

1-/S

S1/R

PI32

/CTE

D2/

RB0

PGEC

3/O

A1O

UT/

AN3/

C1I

N4-

/C4I

N2-

/RPI

33/C

TED

1/R

B1

RB12RB11RB10VCAP

VSSRC9RC8RC7RC6

RB9

RB

7PG

EC2/

SC

L1/R

P38

/RB

6PG

ED2/

SD

A1/

RP

37/R

B5

V DD

VSS

RC

5R

C4

RC

3R

A9

RA

4

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FIGURE 2-5: PIN DIAGRAMS (CONTINUED)

64-Pin TQFP/QFN

dsPIC33EV64GMX06dsPIC33EV128GMX06dsPIC33EV256GMX06

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1 482 473 464 455 446 437 428 419 4010 3911 3812 3713 3614 3515 3416 33

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

RA7RB14RB15RG6RG7RG8

MCLRRG9VSSVDD

RA12RA11RA0RA1

PGED3/OA2IN-/AN2/C2IN1-/SS1/RPI32/CTED2/RB0PGEC3/OA1OUT/AN3/C1IN4-/C4IN2-/RPI33/CTED1/RB1

RA1

0R

B13

RB1

2R

B11

RB1

0R

F1R

F0VD

DVC

AP

RC

9R

D6

RD

5R

C8

RC

7R

C6

RB9

RB8RC13RB7RC10PGEC2/SCL1/RP38/RB6PGED2/SDA1/RP37/RB5RD8VSSRC15RC12VDDRC5RC4RC3RA9RA4

PGEC

1/O

A1IN

+/AN

4/C

1IN

3-/C

1IN

1+/C

2IN

3-/R

PI34

/RB2

PGED

1/O

A1IN

-/AN

5/C

1IN

1-/(C

TMU

C)/R

P35/

RB3

AVD

DAV

SSR

C0

RC

1R

C2

RC

11V S

SVD

DR

E12

RE

13R

E14

RE

15R

A8

RB

4

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2.4 Program Memory Write/Erase

RequirementsThe program Flash memory has a specific write/eraserequirement that must be adhered to for proper deviceoperation. The rule is that any given word in memorymust not be written without first erasing the page inwhich it is located. Thus, the easiest way to conform tothis rule is to write all the data in a programming blockwithin one write cycle. The programming methodsspecified in this document comply with thisrequirement.

2.5 Memory MapThe program memory map extends from 000000h toFFFFFEh. Code memory is located at the start of thememory map. The last locations of implemented codememory are reserved for the device Configuration bits.

Table 2-2 lists the code memory size, the size of theerase blocks and the number of erase blocks presentin each device variant.

Locations, 800200h through 800BFEh, are reserved forexecutive code memory. This region stores the PE andthe debugging executive, which is used for device pro-gramming. This region of memory cannot be used tostore user code. See Section 6.0 “The ProgrammingExecutive” for more information. The special latchesused for device programming are located at addresses,FA0000h and FA0002h.

Locations, FF0000h and FF0002h, are reserved for theDevice ID Word registers. These bits can be used bythe programmer to identify which device type is beingprogrammed. They are described in Section 7.0“Device ID”. The Device ID registers read outnormally, even after code protection is applied.The locations, 800F80h-800FFEh, are theOne-Time-Programmable (OTP) memory area. Theuser OTP Words can be used for storing product infor-mation, such as serial numbers, system manufacturingdates, manufacturing lot numbers and otherapplication-specific information. They are described inSection 2.6.3 “OTP (One-Time-Programmable)Memory”.Figure 2-6 through Figure 2-8 show a generic memorymap for all devices. See the “Memory Organization”chapter in the specific device data sheet for moreinformation.

Note: A program memory bit can beprogrammed from ‘1’ to ‘0’ only.

TABLE 2-2: CODE MEMORY SIZE

Device Family User Memory Limit (Instruction Words)Write Blocks/No. of Rows

Erase Blocks/No. of Pages

dsPIC33EV64GMX02AB7E (21,952) 343 43dsPIC33EV64GMX04

dsPIC33EV64GMX06

dsPIC33EV128GMX021577E (43,968) 687 86dsPIC33EV128GMX04

dsPIC33EV128GMX06

dsPIC33EV256GMX022AB7E (87,488) 1367 171dsPIC33EV256GMX04

dsPIC33EV256GMX06

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FIGURE 2-6: PROGRAM MEMORY MAP FOR dsPIC33EV64GM00X/10X DEVICES(1)

0x000000

Code Memory

0x00AB800x00AB7E

(21952 instructions)

0x800000

DEVID

0xFEFFFE0xFF0000

0xFFFFFE

Unimplemented(Read ‘0’s)

Reserved

0x7FFFFE

Con

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

Device Configuration

0x00AC000x00ABFE

Reserved0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x8010000x800FFE

OTP Memory

0xF9FFFE0xFA00000xFA00020xFA0004

Write Latches

Reserved

0x800F80Reserved

0x800BFE0x800C00

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FIGURE 2-7: PROGRAM MEMORY MAP FOR dsPIC33EV128GM00X/10X DEVICES(1)

0x000000

Code Memory

0x0157800x01577E

(43968 instructions)

0x800000

0xFA0000Write Latches

0xFA00020xFA0004

DEVID

0xFEFFFE0xFF0000

0xFFFFFE

0xF9FFFE

Unimplemented(Read ‘0’s)

Reserved

0x7FFFFE

ReservedCon

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

0x0158000x0157FE

Reserved

0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x8010000x800FFE

OTP Memory

Device Configuration

0x800F80Reserved

0x800BFE0x800C00

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FIGURE 2-8: PROGRAM MEMORY MAP FOR dsPIC33EV256GM00X/10X DEVICES(1)

0x000000

Code Memory

0x02AB800x02AB7E

(87488 instructions)

0x800000

0xFA0000Write Latches

0xFA00020xFA0004

DEVID

0xFEFFFE0xFF0000

0xFFFFFE

0xF9FFFE

Unimplemented(Read ‘0’s)

Reserved

0x7FFFFE

Reserved

Con

figur

atio

n M

emor

y Sp

ace

Use

r Mem

ory

Spac

e

0x02AC000x02ABFE

Reserved

0xFF0002

Note 1: Memory areas are not shown to scale.

0xFF0004

Executive Code Memory

0x8010000x800FFE

OTP Memory

0x800F80

Device Configuration

Reserved

0x800BFE0x800C00

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2.6 Configuration Bits2.6.1 OVERVIEWThe Configuration bits are stored in the last page locationof implemented program memory. These bits can be setor cleared to select various device configurations. Thereare two types of Configuration bits: system operation bitsand code-protect bits. The system operation bits deter-mine the power-on settings for system level components,such as the oscillator and the Watchdog Timer. Thecode-protect bits prevent program memory from beingread and written.

Table 2-3 and Table 2-4 lists the Configuration registeraddress range for each device.

Table 2-5 shows the Configuration register map. Referto the “Special Features” chapter in the specificdevice data sheet for more information.

2.6.2 CODE-PROTECT CONFIGURATION BITS

The device implements an intermediate security featuredefined by the FSEC register. The Boot Segment (BS) isthe highest privileged segment and the General Seg-ment (GS) is the lowest privileged segment. The totalcode memory can be split into BS or GS. The size of thesegments is determined by the BSLIM bits. Therelative location of the segments within user space doesnot change, such that the BS (if present) occupies thememory area just after the Interrupt Vector Table (IVT)and the GS occupies the space just after BS (or if theAlternate Vector Table (AIVT) is enabled, just after theAIVT VS). The Configuration Segment (or CS) is a smallsegment (less than a page, typically just one row) withinthe code memory address space that contains all userconfiguration data.

TABLE 2-3: CONFIGURATION WORD ADDRESSES (1 OF 2)Device FSEC FBSLIM FSIGN FOSCSEL FOSC FWDT FPOR

dsPIC33EV64GMX020xAB80 0xAB90 0xAB94 0xAB98 0xAB9C 0xABA0 0xABA4dsPIC33EV64GMX04

dsPIC33EV64GMX06

dsPIC33EV128GMX020x15780 0x15790 0x15794 0x15798 0x1579C 0x157A0 0x157A4dsPIC33EV128GMX04

dsPIC33EV128GMX06

dsPIC33EV256GMX020x2AB80 0x2AB90 0x2AB94 0x2AB98 0x2AB9C 0x2ABA0 0x2ABA4dsPIC33EV256GMX04

dsPIC33EV256GMX06

TABLE 2-4: CONFIGURATION WORD ADDRESSES (2 OF 2)Device FICD FDMTINTVL FDMTINTVH FDMTCNTL FDMTCNTH FDMT FDEVOPT FALTREG

dsPIC33EV64GMX020xABA8 0xABAC 0xABB0 0xABB4 0xABB8 0xABBC 0xABC0 0xABC4dsPIC33EV64GMX04

dsPIC33EV64GMX06

dsPIC33EV128GMX020x157A8 0x157AC 0x157B0 0x157B4 0x157B8 0x157BC 0x157C0 0x157C4dsPIC33EV128GMX04

dsPIC33EV128GMX06

dsPIC33EV256GMX020x2ABA8 0x2ABAC 0x2ABB0 0x2ABB4 0x2ABB8 0x2ABBC 0x2ABC0 0x2ABC4dsPIC33EV256GMX04

dsPIC33EV256GMX06

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M00X/10X

TA

Bit 3 Bit 2 Bit 1 Bit 0

FS BSS2 BSS1 BSS0 BWRP

FB

Re — — — —

FO — FNOSC2 FNOSC1 FNOSC0

FO — OSCIOFNC POSCMD1 POSCMD0

FW WDTPS3 WDTPS2 WDTPS1 WDTPS0

FP — — — BOREN

FIC — — ICS1 ICS0

FD

FD

FD

FD

FD — — — DMTEN

FD ALTI2C1 r(1) — PWMLOCK

FA — CTXT1

LeNo

BLE 2-5: CONFIGURATION REGISTER MAPRegister

NameBits

23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4

EC — AIVTDIS — — — CSS2 CSS1 CSS0 CWRP GSS1 GSS0 GWRP —

SLIM — — — — BSLIM

served — r(2) — — — — — — — — — — —

SCSEL — — — — — — — — IESO — — —

SC — — — — — — — — PLLKEN FCKSM1 FCKSM0 IOL1WAY —

DT — — — — — — — WDTWIN1 WDTWIN0 WINDIS FWDTEN1 FWDTEN0 WDTPRE

OR — — — — — — — — — r(1) — — —

D — — — — — — — — — r(1) — — —

MTINTVL — DMTINTV

MTINTVH — DMTINTV

MTCNTL — DMTCNT

MCNTH — DMTCNT

MT — — — — — — — — — — — — —

EVOPT — — — — — — — — — — — — —

LTREG — — — — — — — — — CTXT2

gend: — = unimplemented, read as ‘1’; r = Reserved bit.te 1: This bit is reserved and must be programmed as ‘1’

2: This bit is reserved and must be programmed as ‘0’

dsPIC33EVXXXGM00X/10X

TABLE 2-6: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTIONBit Field Register Description

BWRP FSEC Boot Segment Write-Protect bit1 = User program memory is not write-protected0 = User program memory is write-protected

BSS FSEC Boot Segment Code Flash Protection Level bits11 = No protection (other than BWRP write protection)10 = Standard security0x = High security

GWRP FSEC General Segment Write-Protect bit1 = User program memory is not write-protected0 = User program memory is write-protected

GSS FSEC General Segment Code Flash Protection Level bits11 = No protection (other than GWRP write protection)10 = Standard security0x = High security

CWRP FSEC Configuration Segment Write-Protect bit1 = Configuration Segment is not write-protected0 = Configuration Segment is write-protected

CSS FSEC Configuration Segment Code Flash Protection Level bits111 = No protection (other than CWRP write protection)110 = Standard security10x = Enhanced security0xx = High security

AIVTDIS FSEC Alternate Interrupt Vector Table Disable bit1 = Disables AIVT0 = Enables AIVT

BSLIM FBSLIM Boot Segment Code Flash Page Address Limit bitsContains the page address of the first active General Segment page. The value to be programmed is the inverted page address, such that programming additional ‘0’s can only increase the Boot Segment size (i.e., 0x1FFD = 2 Pages or 1024 instruction words).

FNOSC FOSCSEL Initial Oscillator Source Selection bits111 = Internal Fast RC (FRC) Oscillator with Postscaler110 = Internal Fast RC (FRC) Oscillator with Divide-by-16101 = LPRC Oscillator100 = Secondary (LP) Oscillator011 = Primary (XT, HS, EC) Oscillator with PLL010 = Primary (XT, HS, EC) Oscillator001 = Internal Fast RC (FRC) Oscillator with PLL000 = FRC Oscillator

IESO FOSCSEL Two-Speed Oscillator Start-up Enable bit1 = Starts up device with FRC, then automatically switches to the user-selected

oscillator source when ready0 = Starts up device with the user-selected oscillator source

POSCMD FOSC Primary Oscillator Mode Select bits11 = Primary Oscillator is disabled10 = HS Crystal Oscillator mode01 = XT Crystal Oscillator mode00 = EC (External Clock) mode

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OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes)1 = OSC2 is the clock output0 = OSC2 is the general purpose digital I/O pin

IOL1WAY FOSC Peripheral Pin Select (PPS) Configuration bit1 = Allows only one reconfiguration0 = Allows multiple reconfigurations

FCKSM FOSC Clock Switching Mode bits1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

PLLKEN FOSC PLL Lock Wait Enable bit1 = Clock switches to the PLL source; will wait until the PLL lock signal is valid0 = Clock switch will not wait for the PLL lock

WDTPS FWDT Watchdog Timer Postscaler bits1111 = 1:32,7681110 = 1:16,384•••0001 = 1:20000 = 1:1

WDTPRE FWDT Watchdog Timer Prescaler bit1 = 1:1280 = 1:32

FWDTEN FWDT Watchdog Timer Enable bits11 = WDT is enabled in hardware10 = WDT is controlled via the SWDTEN bit01 = WDT is enabled only while device is active and is disabled in Sleep;

SWDTEN bit is disabled00 = WDT and SWDTEN are disabled

WINDIS FWDT Watchdog Timer Window Enable bit1 = Watchdog Timer is in Non-Window mode0 = Watchdog Timer is in Window mode

WDTWIN FWDT Watchdog Timer Window Select bits11 = WDT window is 25% of the WDT period10 = WDT window is 37.5% of the WDT period01 = WDT window is 50% of the WDT period00 = WDT Window is 75% of the WDT period

BOREN FPOR Brown-out Reset (BOR) Detection Enable bit1 = BOR is enabled0 = BOR is disabled

ICS FICD ICD Communication Channel Select bits11 = Communicates on PGEC1 and PGED110 = Communicates on PGEC2 and PGED201 = Communicates on PGEC3 and PGED300 = Reserved, do not use

DMTINTV FDMTINTVL Lower 16 bits of the 32-bit field that configures the DMT window interval bit.DMTINTV FDMTINTVH Upper 16 bits of the 32-bit field that configures the DMT window interval bit.DMTCNT FDMTCNTL Lower 16 bits of the 32-bit field that configures the DMT instruction count

time-out value bit.DMTCNT FDMCNTH Upper 16 bits of the 32-bit field that configures the DMT instruction count

time-out value bit.

TABLE 2-6: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register Description

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2.6.3 OTP (ONE-TIME-PROGRAMMABLE) MEMORY

dsPIC33EVXXXGM00X/10X devices contain 64 OTPWords, located at addresses, 800F80h through800FFEh. The OTP Words can be utilized by the userfor storing checksum, code revisions, productinformation, such as serial numbers, systemmanufacturing dates, manufacturing lot numbers andother application-specific information. These wordscan only be written once.

DMTEN FDMT Deadman Timer Enable bit1 = Deadman timer is enabled and cannot be disabled by software 0 = Deadman timer is disabled and can be enabled by software

PWMLOCK FDEVOPT PWM Lock Enable bit1 = Certain PWM registers may only be written after a key sequence0 = PWM registers may be written without a key sequence

ALTI2C1 FDEVOPT Alternate I2C™ Pins for I2C1 bit1 = I2C1 is mapped to the SDA1/SCL1 pins0 = I2C1 is mapped to the ASDA1/ASCL1 pins

CTXT1 FALTREG Specifies the Alternate Working Register Set #1 Association with Interrupt Priority Level (IPL) bits111 = Not assigned110 = Alternate Register Set #1 assigned to IPL Level 7101 = Alternate Register Set #1 assigned to IPL Level 6100 = Alternate Register Set #1 assigned to IPL Level 5011 = Alternate Register Set #1 assigned to IPL Level 4010 = Alternate Register Set #1 assigned to IPL Level 3001 = Alternate Register Set #1 assigned to IPL Level 2000 = Alternate Register Set #1 assigned to IPL Level 1

CTXT2 FALTREG Specifies the Alternate Working Register Set #2 Association with Interrupt Priority Level (IPL) bits111 = Not assigned110 = Alternate Register Set #2 assigned to IPL Level 7101 = Alternate Register Set #2 assigned to IPL Level 6100 = Alternate Register Set #2 assigned to IPL Level 5011 = Alternate Register Set #2 assigned to IPL Level 4010 = Alternate Register Set #2 assigned to IPL Level 3001 = Alternate Register Set #2 assigned to IPL Level 2000 = Alternate Register Set #2 assigned to IPL Level 1

TABLE 2-6: dsPIC33EVXXXGM00X/10X CONFIGURATION BITS DESCRIPTION (CONTINUED)Bit Field Register Description

Note: The OTP area is not cleared by only theerase command. This memory can bewritten only once.

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3.0 DEVICE PROGRAMMING – ICSPICSP mode is a special programming protocol thatallows you to read and write to device memory. TheICSP mode is the most direct method used to programthe device, which is accomplished by applying controlcodes and instructions, serially to the device, using thePGECx and PGEDx pins. ICSP mode also has theability to read the executive memory to determine if theProgramming Executive (PE) is present. This mode isalso able to write the PE to executive memory if it ismissing and if the Enhanced ICSP mode is to be used.

In ICSP mode, the system clock is taken from thePGECx pin, regardless of the device’s Oscillator Con-figuration bits. All instructions are shifted serially into aninternal buffer, then loaded into the Instruction Register(IR) and executed. No program fetching occurs frominternal memory. Instructions are fed in 24 bits at atime. PGEDx is used to shift data in, and PGECx isused as both the serial shift clock and the CPUexecution clock.

3.1 Overview of the Programming Process

Figure 3-1 illustrates the high-level overview of theprogramming process. After entering ICSP mode, thefirst action is to Bulk Erase the code memory. Next, thecode memory is programmed, followed by the deviceConfiguration bits. Code memory (including the Config-uration bits) is then verified to ensure that programmingwas successful. Then, the code-protect Configurationbits are programmed if required.

FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW

Note 1: During ICSP operation, the operatingfrequency of PGECx must not exceed5 MHz.

2: ICSP mode is slower than EnhancedICSP mode for programming.

Start

Perform BulkErase of Code Memory

Program Code Memory,

Verify Program Memory,

End

Enter ICSP™

Program Code-Protect

Exit ICSP

Configuration Wordsand OTP Words

Configuration Wordsand User OTP Words

Configuration Bits

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3.2 Entering ICSP ModeAs illustrated in Figure 3-2, entering ICSP Program/Verify mode requires four steps:

1. MCLR is briefly driven high and then low (P21).2. A 32-bit key sequence is clocked into PGEDx.

An interval of at least P18 must elapse beforepresenting the key sequence on PGEDx.

3. MCLR is held low during a specified period, P19,and then driven high.

4. After a P7 + 5 * P1 delay, five clock pulses mustbe generated on the PGECx pin.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0001’(more easily remembered as 4D434851h inhexadecimal). The device will enter ICSP mode only ifthe sequence is valid. The Most Significant bit (MSb) ofthe most significant nibble must be shifted in first.

On successful ICSP mode entry, the program memorycan be accessed and programmed in serial fashion.

FIGURE 3-2: ENTERING ICSP™ MODE

Note: If a capacitor is present on the MCLR pin,the high time for entering ICSP mode canvary.

MCLR

PGEDx

PGECx

VDD

P6

P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434851h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 1

P7VDD VDD

P21P1 * 5

1 2 3 4 5

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3.3 ICSP OperationAfter entering into ICSP mode, the CPU is Idle.Execution of the CPU is governed by an internal statemachine. A 4-bit control code is clocked in usingPGECx and PGEDx, and this control code is used tocommand the CPU (see Table 3-1).

The SIX control code is used to send instructions to theCPU for execution and the REGOUT control code isused to read data out of the device through the VISIregister.

TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE

3.3.1 SIX SERIAL INSTRUCTION EXECUTION

The SIX control code allows execution of the familyassembly instructions. When the SIX code is received,the CPU is suspended for 24 clock cycles, as the instruc-tion is then clocked into the internal buffer. Once theinstruction is shifted in, the state machine allows it to beexecuted over the next four PGC clock cycles. While thereceived instruction is executed, the state machinesimultaneously shifts in the next 4-bit command (seeFigure 3-3).

3.3.1.1 Differences Between SIX Instruction Execution and Normal Instruction Execution

There are some differences between executing instruc-tions using the SIX ICSP command and normal deviceinstruction execution. As a result, the code examples inthis specification might not match those required toperform the same operations during normal deviceoperation.

The differences are:

• Two-word instructions require 2 SIX operations toclock in all of the necessary data.

Examples of two-word instructions are GOTO andCALL.

• Two-cycle instructions require 2 SIX operations tocomplete. The first SIX operation shifts in theinstruction and begins to execute it. A second SIXoperation, which should shift in a NOP to avoidlosing data, allows the required CPU clocks tofinish executing the instruction.

Examples of two-cycle instructions are Table Read(TBLRD) and Table Write (TBLWT) instructions.

• The CPU does not automatically stall to accountfor pipeline changes. A CPU stall occurs when aninstruction modifies a register, which is used bythe instruction immediately following the CPU stallfor Indirect Addressing. During normal operation,the CPU forces a NOP while the new data is read.To account for this, while using ICSP, any indirectreferences to a recently modified register shouldbe proceeded with a NOP. For example, MOV #0x0,W0, followed by, MOV[W0],W1, must have a NOP inserted in between. If a two-cycle instruction modifies a register, which isused indirectly, it requires two following NOPs. OneNOP executes the second half of the instruction andthe other NOP stalls the CPU to correct the pipeline. For example, TBLWTL [W0++],[W1], should befollowed by 2 NOPs.

• The device Program Counter (PC) continues toautomatically increment during the ICSP instruc-tion execution, even though the Flash memory isnot being used. As a result, it is possible for thePC to be incremented so that it points to invalidmemory locations.

Examples of invalid memory spaces are unimple-mented Flash addresses or the vector space(location: 0x0 to 0x1FF).

If the PC ever points to these locations, it causesthe device to reset, possibly interrupting the ICSPoperation. To prevent this, instructions should beperiodically executed to reset the PC to a safespace. The optimal method of achieving this is toperform a “GOTO 0x200” instruction.

4-Bit Control Code Mnemonic Description

0000 SIX Shift in 24-bit instruction and execute.

0001 REGOUT Shift out the VISIregister.

0010-1111 N/A Reserved.

Note: Data bits on PGEDx are latched on therising edge of the PGECx clock pulses.

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3.3.2 REGOUT SERIAL INSTRUCTION

EXECUTIONThe REGOUT control code allows the data to beextracted from the device in ICSP mode. It is used toclock the contents of the VISI register out of the deviceand over the PGEDx pin. After the REGOUT controlcode is received, the CPU is held Idle for 8 cycles. Afterthis, an additional 16 cycles are required to clock thedata out (see Figure 3-4).

The REGOUT code is unique as the PGEDx pin is aninput when the control code is transmitted to thedevice. However, after the control code is processed,the PGEDx pin becomes an output as the VISI registeris shifted out.

FIGURE 3-3: SIX SERIAL EXECUTION

FIGURE 3-4: REGOUT SERIAL EXECUTION

Note 1: After the contents of VISI are shifted out,the devices maintain PGEDx as an outputuntil the first rising edge of the next clock isreceived.

2: Data changes on the falling edge andlatches on the rising edge of PGECx.For all data transmissions, the LeastSignificant bit (LSb) is transmitted first.

P4

2 3 1 2 3 23 24 1 2 3 4

P1

PGECxP4A

PGEDx

24-Bit Instruction FetchExecute PC – 1,

1

0 0

Fetch SIX

4 5 6 7 8 18 19 20 21 2217

LSb X X X X X X X X X X X X X X MSb

PGEDx = Input

P2

P3P1B

P1A

0 0 0 0

Control Code

4

0 0

Execute 24-BitInstruction, FetchNext Control Code

1 2 3 4 1 2 7 8PGECx

P4

PGEDx

PGEDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register

P5

PGEDx = Output

1 2 3 1 2 3 4

P4A

11 13 15 161412

No Execution Takes Place,Fetch Next Control Code

0 0 0 0 0

PGEDx = Input

MSb1 2 3 41

4 5 6

LSb 141312... 11100

Fetch REGOUT Control Code

0

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3.4 Flash Memory Programming in

ICSP Mode3.4.1 PROGRAMMING OPERATIONSFlash memory write/erase operations are controlled bythe NVMCON register. Programming is performed bysetting NVMCON to select the type of erase operation(Table 3-2) or write operation (Table 3-3) and initiatingthe programming by setting the WR control bit(NVMCON).

The PGECx clock is required to complete the program-ming operation. The WR control bit is cleared byhardware when the operation is finished. Refer toSection 9.0 “AC/DC Characteristics and TimingRequirements” for information about the maximumtime required for various programming operations.

TABLE 3-2: NVMCON ERASE OPERATIONS

TABLE 3-3: NVMCON WRITE OPERATIONS

3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE

For protection against accidental operations, the erase/write initiation sequence must be written to the NVMKEYregister to allow any erase or program operation toproceed. The two instructions following the start of theprogramming sequence should be NOPs. To start anerase or write sequence, the following steps must becompleted:

1. Write 55h to the NVMKEY register.2. Write AAh to the NVMKEY register.3. Set the WR bit in the NVMCON register.4. Execute three NOP instructions.The WR bit should be polled to generate enough clockcycles for the programming operation and to determineif the erase or write cycle has been completed.

NVMCONValue Erase Operation

400Eh Bulk Erase of user memory only (does not erase Device ID, Programming Executive memory and OTP Words).

4003h Erases a page of program or Programming Executive memory.

NVMCONValue Write Operation

4001h Double-word programming operation.

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REGISTER 3-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY)

R/SO-0(1) R/W-0(1) R/W-0(1) R/W-0 U-0 U-0 R/W-0 R/W-0WR WREN WRERR NVMSIDL(2) — — RPDF(6) URERR(6)

bit 15 bit 8

U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1)

— — — — NVMOP3(4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4)

bit 7 bit 0

Legend: SO = Settable Only bitR = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 WR: Write Control Bit(1)

1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit iscleared by hardware once operation is complete

0 = Program or erase operation is complete and inactivebit 14 WREN: Write Enable bit(1)

1 = Enables Flash program/erase operations0 = Inhibits Flash program/erase operations

bit 13 WRERR: Write Sequence Error Flag bit(1)

1 = An improper program/erase sequence attempt or termination has occurred (bit is set automaticallyon any set attempt of the WR bit)

0 = The program/erase operation completed normallybit 12 NVMSIDL: NVM Stop in Idle Control bit(2)

1 = Discontinues primary Flash operation when the device enters Idle mode0 = Continues primary Flash operation when the device enters Idle mode

bit 11-10 Unimplemented: Read as ‘0’bit 9 RPDF: Row Programming Data Format Control bit(6)

1 = Row data to be stored in RAM is in compressed format0 = Row data to be stored in RAM is in uncompressed format

bit 8 URERR: Row Programming Data Underrun Error Flag bit(6)

1 = Row programming operation has been terminated due to a data underrun error0 = No data underrun has occurred

bit 7-4 Unimplemented: Read as ‘0’

Note 1: These bits can only be reset on a POR.2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.3: All other combinations of NVMOP are unimplemented.4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.6: Not used in ICSP™ mode.

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bit 3-0 NVMOP: NVM Operation Select bits(1,3,4)

1111 = Reserved 1110 = User memory Bulk Erase operation1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0101 = Reserved 0100 = Reserved 0011 = Memory Page Erase operation0010 = Memory row program operation(6)0001 = Memory double-word operation(5)0000 = Reserved

REGISTER 3-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY) (CONTINUED)

Note 1: These bits can only be reset on a POR.2: If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay

(TVREG) before Flash memory becomes operational.3: All other combinations of NVMOP are unimplemented.4: Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress.5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.6: Not used in ICSP™ mode.

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3.5 Erasing Program MemoryThe procedure for erasing the entire code memoryusing Bulk Erase is shown in Figure 3-5.

Figure 3-6 shows the procedure for erasing a page ofcode memory.

Table 3-4 and Table 3-5 illustrate the ICSP programmingprocess for Bulk Erase and Page Erase, respectively.

FIGURE 3-5: BULK ERASE FLOW

FIGURE 3-6: PAGE ERASE FLOW

Note 1: Program memory must be erased beforewriting any data to program memory.

2: For Page Erase operations, theNVMCON value should be modifiedsuitably according to Table 3-2. TheNVMADR/U registers should be pointingto any of the locations of the page to beerased.

Start

End

Set the WR bit to Initiate Erase

Write 400Eh to NVMCON SFR

Poll WR bit until it is Cleared

Start

End

Set the WR bit to Initiate Erase

Write 4003h to NVMCON SFR

Poll WR bit until it is Cleared

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TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASE OF CODE MEMORYCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMCON register to erase all user program memory.0000000000000000

2400EA88394A000000000000

MOV #0x400E, W10MOV W10, NVMCONNOPNOP

Step 3: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 4: Generate clock pulses for the user memory Bulk Erase operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

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TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR ERASING A PAGE OF CODE MEMORY

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page to be erased.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 3: Set the NVMCON register to erase the first page of executive memory.0000000000000000

24003A88394A000000000000

MOV #0x4003, W10MOV W10, NVMCONNOPNOP

Step 4: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 5: Generate clock pulses for Page Erase operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

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3.6 Writing Code MemoryFigure 3-8 provides a high-level description of themethod for writing to code memory.

Two-word writes program the code memory with twoinstruction words at a time. Two words are loaded intothe write latches located at address, FA0000h, and thedestination address must be loaded to the NVMADRU/NVMADR register pair. Next, the WR bit is set to initiatethe write sequence. Then, the WR bit must be checkedfor the sequence to be complete. This process contin-ues for all the data to be programmed. Table 3-6 showsthe ICSP programming details.

The data loaded into the programming latches must bein the packed format, as shown in Figure 3-8.

FIGURE 3-7: PACKED INSTRUCTION WORD FORMAT

FIGURE 3-8: PROGRAM CODE MEMORY FLOW

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word

Start

Configure Devicefor Writes

All DataWritten?

Yes

Initiate WriteSequence and Poll

WR bit to be Cleared

Load Two Words intoWrite Latches

IncrementWrite Pointer

End

No

Programming Using Two Write Latches

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TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W2 with the next two packed instruction words to program.000000000000

2xxxx02xxxx12xxxx2

MOV #, W0MOV #, W1MOV #, W2

Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches.0000000000000000000000000000000000000000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB0B96000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL.W [W6], [W7] NOP NOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 6: Set the NVMCON register to program two instruction words.00000000000000000000

24001A00000088394A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP

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Step 7: Initiate the write cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 8: Generate clock pulses for program operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all code memory is programmed.

TABLE 3-6: SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY:TWO-WORD LATCH WRITES (CONTINUED)

Command(Binary)

Data(Hex) Description

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3.7 Writing Configuration BitsThe procedure for writing Configuration bits is similar tothe procedure for writing code memory, except thatonly two 24-bit words can be programmed at a time.

To change the values of the Configuration bits oncethey have been programmed, the device must beerased, as described in Section 3.5 “ErasingProgram Memory”, and reprogrammed to the desiredvalue. Code protection can be enabled by programming‘0’ in the code protection Configuration bits.

Table 3-7 shows the ICSP programming details forwriting the Configuration bits.

In order to verify the data by reading the Configurationbits after performing the write, the code protection bitsshould initially be programmed to a ‘1’ to ensure thatthe verification can be performed properly. Afterverification is finished, the code protection bits can beprogrammed to a ‘0’ by using a word write to theappropriate Configuration register.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W1 with the next two Configuration Words to program.0000000000000000

2xxxx02xxxx12xxxx22xxxx3

MOV #, W0MOV #, W1MOV #, W2MOV #, W3

Step 4: Set the Write Pointer (W3) and load the write latches.00000000000000000000000000000000000000000000000000000000

EB0300000000BB0B00000000000000BB9B01000000000000BB0B02000000000000BB9B03000000000000

CLR W6NOPTBLWTL W0, [W6]NOPNOPTBLWTH W1, [W6++]NOPNOPTBLWTL W2, [W6]NOPNOPTBLWTH W3, [W6++]NOPNOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct Configuration Word address.0000000000000000

2xxxx42xxxx5883954883965

MOV #DestinationAddress, W4MOV #DestinationAddress, W5MOV W4, NVMADRMOV W5, NVMADRU

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Step 6: Set the NVMCON register to program two instruction words.00000000000000000000

24001A00000088394A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP

Step 7: Initiate the write cycle.0000000000000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOPNOPNOP

Step 8: Generate clock pulses for program operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all Configuration registers are programmed.

TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS (CONTINUED)

Command(Binary)

Data(Hex) Description

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3.8 Writing OTP WordsThe procedure for writing to the OTP Words is similarto the procedure for writing code, except that the OTPWords can only be written once. It is not possible toprogram a ‘0’ to a ‘1’, but the OTP Words may beprogrammed from a ‘1’ to a ‘0’. Refer to Figure 2-6,through Figure 2-8 for the locations of the User OTPWords.

OTP memory must be written, one double-word at atime. Before writing to any double-word in OTP mem-ory, the corresponding memory locations must be readfirst. The double-word read value must be comparedwith the double-word value to be written and the writemay be performed only if one of the following conditionsis true:

1. The read value is (0xFFFFFF:0xFFFFFF).2. The read value is identical to the value to be

written (all 6 bytes must be identical).3. If the value to be written is

(0xFFFFFF:0xFFFFFF), the read value must bewritten back to memory. In this case, the originalvalue to be written is ignored.

3.9 Reading OTP WordsThe procedure for reading OTP Words is similar to theprocedure for reading code memory. Since there aremultiple OTP Words, they are read one at a time.

3.10 Reading Code MemoryReading from code memory is performed by executinga series of TBLRD instructions and clocking out the datausing the REGOUT command.Table 3-8 shows the ICSP sequence for reading codememory.

To minimize reading time, the same packed data formatthat the write procedure uses is utilized. SeeSection 3.6 “Writing Code Memory” for more detailson the packed data format.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

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Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory to W0:W5.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA1BB6000000000000000000000000000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA0BB6000000000000000000000000000000

CLR W7 NOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7] NOPNOPNOPNOPNOP

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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Step 4: Output W0:W5 using the VISI register and the REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

887C40000000

000000887C41000000

000000887C42000000

000000887C43000000

000000887C44000000

000000887C45000000

000000

MOV W0, VISI NOPClock out contents of VISI register.NOPMOV W1, VISI NOPClock out contents of VISI register.NOPMOV W2, VISI NOPClock out contents of VISI register.NOPMOV W3, VISI NOPClock out contents of VISI register.NOPMOV W4, VISI NOPClock out contents of VISI register.NOPMOV W5, VISI NOPClock out contents of VISI register.NOP

Step 5: Reset the device internal PC.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200 NOPNOPNOP

Step 6: Repeat Steps 3-5 until all desired code memory is read.

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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3.11 Reading Configuration RegistersThe procedure for reading Configuration bits is similarto the procedure for reading code memory. Since thereare multiple Configuration Words, they are read one ata time.

Table 3-9 shows the ICSP programming details forreading the Configuration bits.

TABLE 3-9: SERIAL INSTRUCTION EXECUTION FOR READING CONFIGURATION WORDSCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize TBLPAG, the Write Pointer (W7) and the Read Pointer (W6) for the TBLRD instruction.0000000000000000

200xx020F8878802A02xxxx6

MOV #, W0MOV #, W7MOV W0, TBLPAGMOV #, W6

Step 3: Store the Configuration register and send the contents of the VISI register.000000000000000000000000000000010000000000000000000000000001

000000BA8B96000000000000000000000000000000

BA0B96000000000000000000000000000000

NOPTBLRDH [W6], [W7] NOPNOPNOPNOPNOPClock out contents of VISI register.TBLRDL [W6], [W7]NOPNOPNOPNOPNOPClock out contents of VISI register.

Step 4: Repeat Steps 1-3 until all Configuration registers are read.

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3.12 Verify Code Memory and

Configuration BitsThe verify step involves reading back the code memoryspace and comparing it against the copy held in theprogrammer’s buffer. The Configuration Words areverified with the rest of the code.

The verify process is illustrated in Figure 3-9. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer’s buffer. Referto Section 3.10 “Reading Code Memory” forimplementation details of reading code memory.

FIGURE 3-9: VERIFY CODE MEMORY FLOW

3.13 Exiting ICSP ModeExiting Program/Verify mode is done by removing VDDfrom MCLR, as illustrated in Figure 3-10. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VDD.

FIGURE 3-10: EXITING ICSP™ MODE

Note: Because the Configuration Words includethe device code protection bit, code mem-ory should be verified immediately afterwriting if code protection is to be enabled.This is because the device will not bereadable or verifiable if a device Resetoccurs after the code-protect bit has beencleared.

Read Low Word

Read High Byte

Data?

AllCode Memory

Verified?

No

Yes

No

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

DoesInstruction Word =

Expected

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VDD

VDD

P17

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4.0 DEVICE PROGRAMMING – ENHANCED ICSP

This section discusses programming the device throughEnhanced ICSP and the Programming Executive (PE).The PE resides in executive memory (separate fromcode memory) and is executed when Enhanced ICSPProgramming mode is entered. The PE provides themechanism for the programmer (host device) toprogram and verify the dsPIC33EVXXXGM00X/10Xdevices using a simple command set and communica-tion protocol. There are several basic functions providedby the PE:

• Read Memory• Erase Memory• Program Memory• Blank Check

The PE performs the low-level tasks required forerasing, programming and verifying a device. Thisallows the programmer to program the device byissuing the appropriate commands and data. A detaileddescription for each command is provided inSection 6.2 “Programming Executive Commands”.

4.1 Overview of the Programming Process

Figure 4-1 shows the high-level overview of theprogramming process. First, it must be determined ifthe PE is present in executive memory, and then,Enhanced ICSP mode is entered. The programmemory is then erased, and the program memory andConfiguration Words are programmed and verified.Last, the code-protect Configuration bits areprogrammed (if required) and Enhanced ICSP mode isexited.

FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW

Note: The PE uses the device’s data RAM forvariable storage and program execution.After running the PE, no assumptionsshould be made about the contents ofdata RAM.

Start

End

Program Memory,

Verify Program Memory,

Erase

Program Code-Protect

Exit Enhanced ICSP

Confirm Presence of

Enter Enhanced

Configuration Words

Configuration Bits

Programming Executive

ICSP™ Mode

Program Memory

Configuration Wordsand User OTP Words

and User OTP Words

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4.2 Confirming the Presence of the

Programming ExecutiveBefore programming, the programmer must confirmthat the PE is stored in executive memory. Theprocedure for this task is illustrated in Figure 4-2.

First, the ICSP mode is entered. Then, the uniqueApplication ID Word, stored in the executive memory, isread. If the PE is resident, the correct Application IDWord, 0xDF, is read and programming can resume asnormal. However, if the Application ID Word is not pres-ent, the PE must be programmed to executive codememory using the method described in the Section 5.0“Programming the Programming Executive toMemory”.Section 3.0 “Device Programming – ICSP”describes the ICSP programming method. Section 4.3“Reading the Application ID Word” describes theprocedure for reading the Application ID Word in ICSPmode.

FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE

Is

Start

Enter ICSP™ Mode

Application IDPresent?

Yes

No

Application IDCheck the

be ProgrammedProg. Executive must

by Reading Address,800BFEh

End

Exit ICSP Mode

Enter Enhanced

Sanity Check

ICSP Mode

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4.3 Reading the Application ID WordThe Application ID Word is stored at address,800BFEh, in executive code memory. To read thismemory location, you must use the SIX control code tomove this program memory location to the VISI regis-ter. Then, the REGOUT control code must be used toclock the contents of the VISI register out of the device.The corresponding control and instruction codes thatmust be serially transmitted to the device to performthis operation are shown in Table 4-1.

After the programmer has clocked out the ApplicationID Word, it must be inspected. If the Application ID hasthe value, 0xDF, the PE is resident in memory and thedevice can be programmed using the mechanismdescribed in Section 4.0 “Device Programming –Enhanced ICSP”. However, if the Application ID hasany other value, the PE is not resident in memory; itmust be loaded to memory before the device can beprogrammed. The procedure for loading the PE tomemory is described in Section 5.0 “Programmingthe Programming Executive to Memory”.

TABLE 4-1: SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORDCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction.00000000000000000000000000000000000000000000

2008008802A020BFE020F881000000BA0890000000000000000000000000000000

MOV #0x80, W0 MOV W0, TBLPAGMOV #0xBFE, W0 MOV #VISI, W1 NOP TBLRDL [W0], [W1] NOPNOPNOPNOPNOP

Step 3: Output the VISI register using the REGOUT command.0001 Clock out contents of the VISI register.

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4.4 Entering Enhanced ICSP ModeAs illustrated in Figure 4-3, entering Enhanced ICSPProgram/Verify mode requires three steps:

1. The MCLR pin is briefly driven high and thenlow.

2. A 32-bit key sequence is clocked into PGEDx.An interval of at least P18 must elapse beforepresenting the key sequence on PGEDx.

3. MCLR is held low for a specified period of timeand then driven high.

The key sequence is a specific 32-bit pattern,‘0100 1101 0100 0011 0100 1000 0101 0000’(more easily remembered as 4D434850h in hexa-decimal format). The device will enter Program/Verifymode only if the key sequence is valid. The MostSignificant bit (MSb) of the most significant nibble mustbe shifted in first.

Once the key sequence is complete, VDD must beapplied to MCLR and held at that level for as long asProgram/Verify mode is to be maintained. An intervaltime of at least P19, P7 and P1 * 5 must elapse beforepresenting data on PGEDx. Signals appearing onPGEDx before P7 has elapsed will not be interpretedas valid.

4.5 Blank CheckThe term, “Blank Check”, implies verifying that thedevice has been successfully erased and has noprogrammed memory locations. A blank or erasedmemory location is always read as ‘1’. The Device ID registers (FF0000h:FF0002h) can beignored by the Blank Check, since this region storesdevice information that cannot be erased. Additionally,all unimplemented memory space and Calibrationregisters should be ignored by the Blank Check.

The QBLANK command is used for the Blank Check. Itdetermines if the code memory is erased by testingthese memory regions. A ‘BLANK’ or ‘NOT BLANK’response is returned. If it is determined that the deviceis not blank, it must be erased before attempting toprogram the chip.

FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE

MCLR

PGEDx

PGECx

VDD

P6P14

b31 b30 b29 b28 b27 b2 b1 b0b3...

Program/Verify Entry Code = 4D434850h

P1AP1B

P18

P19

0 1 0 0 1 0 0 0 0

P7VDD VIH

P21 P1 * 5

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4.6 Code Memory Programming4.6.1 PROGRAMMING METHODOLOGYThere are two commands that can be used forprogramming code memory when utilizing the PE. ThePROG2W command programs and verifies two 24-bitinstruction words into the program memory, starting atthe address specified. The second and faster command,PROGP, allows up to sixty-four 24-bit instruction words tobe programmed and verified into program memory,starting at the address specified. See Section 6.0 “TheProgramming Executive” for a full description of eachof these commands.

Figure 4-4 and Figure 4-5 show the programmingmethodology for the PROG2W and PROGP commands. Inboth instances, 87552K instruction words of thedsPIC33EVXXXGM00X/10X devices are programmed.

FIGURE 4-4: FLOWCHART FOR DOUBLE-WORD PROGRAMMING

FIGURE 4-5: FLOWCHART FOR MULTIPLE WORD PROGRAMMING

BaseAddress = 0hRemainingCmds = 43776

Start

FailureReport ErrorEnd

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROG2W

RemainingCmdsIs

‘0’?

BaseAddress + 04hBaseAddress =

PROG2W ResponseIs

BaseAddress = 0hRemainingCmds = 1368

Start

FailureReport ErrorEnd

Yes

No

RemainingCmds =RemainingCmds – 1

Yes

PASS?

No

BaseAddressCommand to Program

Send PROGP

RemainingCmdsIs

‘0’?

BaseAddress + 80hBaseAddress =

PROGP ResponseIs

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4.7 Configuration Bit ProgrammingConfiguration bits are programmed one at a time usingthe PROG2W command. This command specifies theconfiguration data and address. When Configurationbits are programmed, any unimplemented bits must beprogrammed with a ‘1’. Multiple PROG2W commands are required to programall Configuration bits. A flowchart for Configuration bitprogramming is shown in Figure 4-6.

FIGURE 4-6: CONFIGURATION BIT PROGRAMMING FLOW

4.8 Programming VerificationAfter code memory is programmed, the contents ofmemory can be verified to ensure that programmingwas successful. Verification requires code memory tobe read back and compared against the copy held inthe programmer’s buffer.

The READP command can be used to read back all theprogrammed code memory and Configuration Words.

Alternatively, you can have the programmer performthe verification after the entire device is programmedusing a checksum computation.

See Section 8.0 “Checksum Computation” for moreinformation on calculating the checksum.

4.9 Exiting Enhanced ICSP ModeExiting Program/Verify mode is done by removing VDDfrom MCLR, as illustrated in Figure 4-7. The onlyrequirement for exit is that an interval, P16, shouldelapse between the last clock, and program signals onPGECx and PGEDx, before removing VDD.

FIGURE 4-7: EXITING ENHANCED ICSP™ MODE

Send PROG2WCommand

IsPROG2W Response

PASS?

No

Yes

No

FailureReport Error

Start

End

Yes

LastConfiguration

Word?

ConfigAddress =ConfigAddress +

04h

MCLR

P16

PGEDx

PGEDx = Input

PGECx

VDD

VDD

VDD

P17

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5.0 PROGRAMMING THE PROGRAMMING EXECUTIVETO MEMORY

5.1 OverviewIf it is determined that the PE is not present in executivememory (as described in Section 4.2 “Confirming thePresence of the Programming Executive”), the PEmust be programmed to executive memory.

Figure 5-1 shows the high-level process of program-ming the PE into executive memory. First, ICSP modemust be entered and executive memory must beerased. Then, the PE is programmed and verified.Finally, ICSP mode is exited.

FIGURE 5-1: HIGH-LEVEL PROGRAMMING EXECUTIVE PROGRAM FLOW

5.2 Erasing Executive MemoryThe procedure for erasing each page of executivememory is similar to that of erasing program memoryand is shown in Figure 5-2. It consists of settingNVMCON to 4003h and then executing the programmingcycle.

Table 5-1 illustrates the ICSP programming process forerasing executive code memory.

FIGURE 5-2: PAGE ERASE FLOW

Note: The Programming Executive (PE) can beobtained from each device page on theMicrochip web site: www.microchip.com.

Start

End

Program the

Enter ICSP™ Mode

Page Erase All Pages in

Programming Executive

Executive Memory

Exit ICSP™ Mode

Read/Verify theProgramming Executive

Note: The PE memory must always be erasedbefore it is programmed, as described inFigure 5-1.

Start

End

Set the WR bit to Initiate Erase

Write 4003h to NVMCON SFR

Poll WR bit until it is Cleared

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TABLE 5-1: SERIAL INSTRUCTION EXECUTION FOR ERASING ALL PAGES OF EXECUTIVE

MEMORYCommand(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page of executive memory to be erased.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 3: Set the NVMCON register to erase the first page of executive memory.0000000000000000

24003A88394A000000000000

MOV #0x4003, W10MOV W10, NVMCONNOPNOP

Step 4: Initiate the erase cycle.00000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOP

Step 5: Generate clock pulses for the Page Erase operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 6: Repeat Steps 2-5 for all pages of executive memory.

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5.3 Program the Programming

ExecutiveStoring the PE to executive memory is similar to normalprogramming of code memory. The executive memorymust first be erased and then programmed usingtwo-word writes (two instruction words). The controlflow for this method is summarized in Figure 5-3.

Table 5-2 illustrates the ICSP programming processesfor PE memory. To minimize programming time, thesame packed data format that the PE uses is utilized.See Section 6.2 “Programming ExecutiveCommands” for more details on the packed dataformat.

FIGURE 5-3: PROGRAMMING EXECUTIVE PROGRAM FLOW

Start

Configure Devicefor Writes

All Data Written?

Yes

Initiate WriteSequence and Poll

WR bit to be Cleared

Load Two Words intoWrite Latches

IncrementWrite Pointer

End

No

Programming Using 2 Write Latches

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TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES)

Command(Binary)

Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register for writing to the latches.00000000

200FAC8802AC

MOV #0xFA, W12MOV W12, TBLPAG

Step 3: Load W0:W2 with the next two packed instruction words to program.000000000000

2xxxx02xxxx12xxxx2

MOV #, W0MOV #, W1MOV #, W2

Step 4: Set the Read Pointer (W6) and the Write Pointer (W7), and load the write latches.0000000000000000000000000000000000000000000000000000000000000000

EB0300000000EB0380000000BB0BB6000000000000BBDBB6000000000000BBEBB6000000000000BB0B96000000000000

CLR W6NOPCLR W7NOPTBLWTL [W6++], [W7] NOPNOPTBLWTH.B [W6++], [W7++] NOPNOPTBLWTH.B [W6++], [++W7] NOPNOPTBLWTL.W [W6], [W7] NOP NOP

Step 5: Set the NVMADRU/NVMADR register pair to point to the correct row.0000000000000000

2xxxx32xxxx4883953883964

MOV #DestinationAddress, W3MOV #DestinationAddress, W4MOV W3, NVMADRMOV W4, NVMADRU

Step 6: Set the NVMCON register to program two instruction words.00000000000000000000

24001A00000088394A000000000000

MOV #0x4001, W10NOPMOV W10, NVMCONNOPNOP

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Step 7: Initiate the write cycle.0000000000000000000000000000000000000000

200551883971200AA1883971A8E729000000000000000000000000000000

MOV #0x55, W1MOV W1, NVMKEYMOV #0xAA, W1MOV W1, NVMKEYBSET NVMCON, #WRNOPNOPNOPNOPNOP

Step 8: Generate clock pulses for program operation to complete until the WR bit is clear.0000000000000000000000010000000000000000000000000000

—

000000803940000000887C40000000

000000000000000000040200000000000000000000

—

NOPMOV NVMCON, W0NOPMOV W0, VISINOPClock out contents of VISI register.NOPNOPNOPGOTO 0x200NOPNOPNOPRepeat until the WR bit is clear.

Step 9: Repeat Steps 3-8 until all code memory is programmed.

TABLE 5-2: PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES) (CONTINUED)

Command(Binary)

Data(Hex) Description

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5.4 Reading Executive MemoryReading from executive memory is performed by exe-cuting a series of TBLRD instructions and clocking outthe data using the REGOUT command.Table 5-3 shows the ICSP programming details forreading executive memory.

To minimize reading time, the same packed data formatthat the PE uses is utilized. See Section 6.2“Programming Executive Commands” for moredetails on the packed data format.

TABLE 5-3: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORYCommand

(Binary)Data(Hex) Description

Step 1: Exit the Reset vector.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200NOPNOPNOP

Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction.000000000000

200xx08802A02xxxx6

MOV #, W0MOV W0, TBLPAGMOV #, W6

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Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory to W0:W5.00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000

EB0380000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA1BB6000000000000000000000000000000BA1B96000000000000000000000000000000BADBB6000000000000000000000000000000BADBD6000000000000000000000000000000BA0BB6000000000000000000000000000000

CLR W7 NOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [W6++], [W7++] NOPNOPNOPNOPNOPTBLRDH.B [++W6], [W7++] NOPNOPNOPNOPNOPTBLRDL [W6++], [W7] NOPNOPNOPNOPNOP

TABLE 5-3: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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Step 4: Output W0:W5 using the VISI register and REGOUT command.000000000001000000000000000100000000000000010000000000000001000000000000000100000000000000010000

887C40000000

000000887C41000000

000000887C42000000

000000887C43000000

000000887C44000000

000000887C45000000

000000

MOV W0, VISI NOPClock out contents of VISI register.NOPMOV W1, VISI NOPClock out contents of VISI register.NOPMOV W2, VISI NOPClock out contents of VISI register.NOPMOV W3, VISI NOPClock out contents of VISI register.NOPMOV W4, VISI NOPClock out contents of VISI register.NOPMOV W5, VISI NOPClock out contents of VISI register.NOP

Step 5: Reset the device internal PC.0000000000000000000000000000

000000000000000000040200000000000000000000

NOPNOPNOPGOTO 0x200 NOPNOPNOP

Step 6: Repeat Steps 3-5 until all desired code memory is read.

TABLE 5-3: SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED)Command

(Binary)Data(Hex) Description

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5.5 Verify Programming ExecutiveThe verify step involves reading back the executivememory space and comparing it against the copy heldin the programmer’s buffer.

The verify process is illustrated in Figure 5-4. The lowerword of the instruction is read, and then the lower byteof the upper word is read and compared against theinstruction stored in the programmer’s buffer. Referto Section 5.4 “Reading Executive Memory” forimplementation details of reading executive memory.

FIGURE 5-4: VERIFY PROGRAMMING EXECUTIVE MEMORY FLOW

Read Low Word

Read High Byte

Does

= ExpectedData?

AllExecutive Memory

Verified?

No

Yes

No

Set TBLPAG = 0x80

Start

Yes

End

with Post-Increment

with Post-Increment

FailureReport Error

Instruction Word

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6.0 THE PROGRAMMING EXECUTIVE

6.1 Programming Executive Communication

The programmer and PE have a master-slaverelationship, where the programmer is the masterprogramming device and the PE is the slave.

All communication is initiated by the programmer in theform of a command. Only one command at a time canbe sent to the PE. In turn, the PE only sends oneresponse to the programmer after receiving andprocessing a command. The PE command set isdescribed in Section 6.2 “Programming ExecutiveCommands”. The response set is described inSection 6.3 “Programming Executive Responses”.

6.1.1 COMMUNICATION INTERFACE AND PROTOCOL

The ICSP/Enhanced ICSP interface is a 2-wire SPI,implemented using the PGC and PGD pins. The PGCpin is used as a clock input pin and the clock sourcemust be provided by the programmer. The PGD pin isused for sending command data to, and receivingresponse data from, the PE.

FIGURE 6-1: PROGRAMMING EXECUTIVE SERIAL TIMING

Since a 2-wire SPI is used, and data transmissions arebidirectional, a simple protocol is used to control thedirection of PGD. When the programmer completes acommand transmission, it releases the PGD line andallows the PE to drive this line high. The PE keeps thePGEDx line high to indicate that it is processing thecommand.

After the PE has processed the command, it bringsPGD low (P9b) to indicate to the programmer that theresponse is available to be clocked out. Theprogrammer can begin to clock out the response aftera maximum wait (P9b) and the programmer mustprovide the necessary amount of clock pulses toreceive the entire response from the PE.

After the entire response is clocked out, theprogrammer should terminate the clock on PGC until itis time to send another command to the PE. Thisprotocol is illustrated in Figure 6-2.

6.1.2 SPI RATEIn Enhanced ICSP mode, the dsPIC33EVXXXGM00X/10X devices operate from the Fast Internal RCOscillator (FRC), which has a nominal frequency of7.3728 MHz. This oscillator frequency yields an effec-tive system clock frequency of 3.6864 MHz. To ensurethat the programmer does not clock too fast, it isrecommended that a 1.8432 MHz clock be provided bythe programmer.

FIGURE 6-2: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

Note: The Programming Executive (PE) can beobtained from each device page on theMicrochip web site: www.microchip.com.

Note: For Enhanced ICSP, all serial data istransmitted on the falling edge of PGCand latched on the rising edge of PGC. Alldata transmissions are sent to the MSbfirst, using 16-bit mode (see Figure 6-1).

PGECx

PGEDx

1 2 3 11 13 15 161412

LSb14 13 12 11

4 5 6

MSb 123... 45

P2

P3

P1

P1BP1A

1 2 15 16 1 2 15 16

PGECx

PGEDx

PGECx = Input PGECx = Input (Idle)

Host TransmitsLast Command Word

PGEDx = Input PGEDx = Output

P8

1 2 15 16

MSB X X X LSB1 0P9b

PGECx = InputPGEDx = Output

P9a

Programming ExecutiveProcesses Command Host Clocks Out Response

Note 1: A delay of 25 ms is required between commands.

MSB X X X LSB MSB X X X LSB

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6.1.3 TIME-OUTSThe PE uses no Watchdog Timer or time-out fortransmitting responses to the programmer. If theprogrammer does not follow the flow controlmechanism using PGECx, as described inSection 6.1.1 “Communication Interface andProtocol”, it is possible that the PE will behaveunexpectedly while trying to send a response to theprogrammer. Since the PE has no time-out, it isimperative that the programmer correctly follow thedescribed communication protocol.

As a safety measure, the programmer should use thecommand time-outs identified in Table 6-1. If the com-mand time-out expires, the programmer should resetthe PE and start programming the device again.

TABLE 6-1: PROGRAMMING EXECUTIVE COMMAND SET

Opcode Mnemonic Length(16-bit words) Time-out Description

0x0 SCHECK 1 1 ms Sanity check.0x1 Reserved N/A N/A This command is reserved; it will return a NACK.0x2 READP 4 1 ms/row Read ‘N’ 24-bit instruction words of primary Flash memory,

starting from the specified address.0x3 PROG2W 6 5 ms Program a double instruction word of code memory at the

specified address and verify.0x4 Reserved N/A N/A This command is reserved; it will return a NACK.0x5 PROGP 99 5 ms Program 64 words of program memory at the specified

starting address, then verify.0x6 Reserved N/A N/A This command is reserved; it will return a NACK.0x7 ERASEB 1 125 ms Bulk Erase user memory.0x8 Reserved N/A N/A This command is reserved; it will return a NACK.0x9 ERASEP 3 25 ms Command to erase a page.0xA Reserved N/A N/A This command is reserved; it will return a NACK.0xB QVER 1 1 ms Query the PE software version.0xC CRCP 5 1s Perform a CRC-16 on the specified range of memory.0xD Reserved N/A N/A This command is reserved; it will return a NACK.0xE QBLANK 5 700 ms Query to check whether the code memory is blank.

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6.2 Programming Executive

CommandsThe PE command set is shown in Table 6-1. This tablecontains the opcode, mnemonic, length, time-out anddescription for each command. Functional details on eachcommand are provided in the command descriptions (seeSection 6.2.4 “Command Descriptions”).

6.2.1 COMMAND FORMATAll PE commands have a general format, consisting ofa 16-bit header and any required data for the command(see Figure 6-3). The 16-bit header consists of a 4-bitopcode field, which is used to identify the command,followed by a 12-bit command length field.

FIGURE 6-3: COMMAND FORMAT

The command opcode must match one of those in thecommand set. Any command that is received, whichdoes not match the list in Table 6-1, will return a“NACK” response (see Section 6.3.1.1 “OpcodeField”). The command length is represented in 16-bit wordssince the SPI operates in 16-bit mode. The PE uses thecommand length field to determine the number ofwords to read from the SPI port. If the value of this fieldis incorrect, the command will not be properly receivedby the PE.

6.2.2 PACKED DATA FORMATWhen 24-bit instruction words are transferred acrossthe 16-bit SPI interface, they are packed to conservespace using the format illustrated in Figure 6-4. Thisformat minimizes traffic over the SPI and provides thePE with data that is properly aligned for performingTable Write operations.

FIGURE 6-4: PACKED INSTRUCTION WORD FORMAT

6.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING

The PE will “NACK” all unsupported commands. Addi-tionally, due to the memory constraints of the PE, nochecking is performed on the data contained in theprogrammer command. It is the responsibility of theprogrammer to command the PE with valid commandarguments or the programming operation may fail.Additional information on error handling is provided inSection 6.3.1.3 “QE_Code Field”.

15 12 11 0

Opcode Length

Command Data First Word (if required)

•

•

Command Data Last Word (if required)

Note: When the number of instruction wordstransferred is odd, MSB2 is zero andLSW2 cannot be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction wordMSBx: Most Significant Byte of instruction word

DS70005137C-page 52 2013-2014 Microchip Technology Inc.

dsPIC33EVXXXGM00X/10X

6.2.4 COMMAND DESCRIPTIONSAll commands supported by the PE are described inSection 6.2.4.1 “SCHECK Command” throughSection 6.2.4.9 “QBLANK Command”.6.2.4.1 SCHECK Command

Table 6-2 shows the description for the SCHECKcommand.

TABLE 6-2: COMMAND DESCRIPTION

The SCHECK command instructs the PE to do nothingbut generate a response. This command is used as a“Sanity Check” to verify that the PE is operational.

Expected Response (2 words):0x1000

0x0002

6.2.4.2 READP Command

Table 6-3 shows the description for READP command.

TABLE 6-3: COMMAND DESCRIPTION

The READP command instructs the PE to read N 24-bitwords of code memory, Flash Configuration Words orDevice ID registers, starting from the 24-bit addressspecified by Addr_MSB and Addr_LS. This commandcan only be used to read 24-bit data. All data returnedin the response to this command uses the packeddata format described in Section 6.2.2 “Packed DataFormat”.Expected Response (2 + 3 * N/2 words for N even):

0x12002 + 3 * N/2Least Significant Program Memory Word 1... Least Significant Data Word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):

0x12004 + 3 * (N – 1)/2Least Significant Program Memory Word 1... MSB of Program Memory Word N (zero-padded)

15 12 11 0Opcode Length

Field Description

Opcode 0x0Length 0x1

Note: This instruction is not required forprogramming, but is provided fordevelopment purposes only.

15 12 11 8 7 0Opcode Length

NReserved Addr_MSB

Addr_LS

Field Description

Opcode 0x2Length 0x4N Number of 24-bit instructions to read

(maximum of 32768)Reserved 0x0Addr_MSB MSB of 24-bit source addressAddr_LS Least Significant 16 bits of 24-bit

source address

Note 1: Reading unimplemented memory wi