dsp design eu fp7 project multibase some research …jsj. svensson3, lv d pl. van der perre2, l....

DSP Design

Some Research Projectsat EITat EIT

related to DSP Design g

Vikt Ö llViktor Öwall

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

DSP Design

EU FP7 project MultibaseMultibase: January 2008 – April 2011

Scalable Multi-tasking Baseband for Mobile Communications1. Multi-streaming radio (concurrent execution of multiple standards)2 S l bl bl / fi bl lti t h l2. Scalable programmable/reconfigurable multi-processor technology3. Algorithm/architecture co-design for maximum energy efficiency


LU Focus: Synch and Channel Estimation, algorithms and architectures.

DSP Design

Digital Front-End Receiver: DFE RxDigital Front-End Receiver: DFE Rx

Contributors:I. Diaz1, L. Hollevoet2 ,

T. Olsson3, J. Rodrigues1, J S 3 L V D P 2J. Svensson3, L. Van Der Perre2,

L. Wilhelmsson3, C. Zhang1, and V Öwall1and V. Öwall

1Lund University2IMEC2IMEC

3Ericsson


DSP Design

Motivation• Design a multi-standard digital front-end receiver

including:g– Automatic Gain and Resource Activity Controller– CompensationCompensation– Filtering and resampling– SynchronizationSynchronization

• Support for concurrent data streams• Support for concurrent data streams


• Supported standards: LTE, DVB-H and IEEE 802.11n

DSP Design

The standardsThe standards• All three standards are OFDM based, however with different FFT-size:

LTE 128 2048– LTE: 128-2048– DVB-H: 2048, 4092 (and 8192)– IEEE 802.11n: 64-128

• …and different sample rates:LTE 30 72 M LTELTE– LTE: 30.72 Msps

– DVB-H: 9.143 Msps– IEEE 802.11n: 20 or 40 Msps

LTELTE

DVBDVBPilot based

DVBDVB

802.11n802.11nPreamble based


Preamble based

DSP Design

The multi stream DFE-Rx

Two concurrent data streams in hardware.

More data streamspossible since theydo not transmit all th tithe time.


DSP Design

Hierarchical wakeup: principleActivation probability Power consumptionComponent

Low HighBaseband

Sync

High Low

Sync

AGRAC High Low


DSP Design

Example: reception of WLAN

DATAChannel

Preamble Noise

Powerconsumption

DATAChannel

p

timeAGRAC (signal detection)

Coarse time syncFalse trigger, no power wastedbecause baseband engine notactivated

Baseband processing


DSP Design

Th lti t DFE RThe multi stream DFE-Rx

Two concurrent data streams in hardware.

More data streamspossible since theydo not transmit all th tithe time.


DSP Design

What is Synchronization?What is Synchronization?Finding the start of a symbol.g y

WLAN

Preamble Signal Data

OFDM SymbolAll SymbolCopyAll

standards

CP Data CP


DSP Design

Synchronization ArchitectureSize of FFT Size of CP or preamble


DSP Design

Synchronization Hardware

Mapped onto a reconfiguarble processing array:Mapped onto a reconfiguarble processing array:• flexibility since multi-standard• hardware reuse since sync only part of the time


DSP DesignMulti standard OFDM timeMulti-standard OFDM time

synchronizationy• 2x2 array• Scenario-aware adaptive resource allocationp• Expandable to more streams

arg


DSP Design

Run-time resource management

• Scenario 1: Single data stream

Corr Input FIFOCorr FIFO

PeakCorr

FIFO &Buffer

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se2010-12-03 Viktor Öwall: FTW 2010

DSP DesignRun-time resource management (II)Run-time resource management


• Scenario 2: Concurrent multi-standard data streams

STD 1(Corr) 21streams

– Computation resources: time-multiplexed.

(Corr) 21

– Data memories: sacrificed data precision.

STD 2(Peak)21


DSP DesignRun-time resource management (III)


• Scenario 2: Concurrent multi-standard data streams STD 1 21

STD 2(Corr)streams

– Computation resources: time-multiplexed.

(Corr)

21(Corr)

– Data memories: sacrificed data precision.

STD 2(Pea21STD 1(Peak)(Pea


DSP Design

Th ChiThe ChipI fi 65 CMOS• Infineon 65nm CMOS process

2 2• Total area 5mm2 and core 3.5mm2

• Pad limited: 144 Pads


DSP DesignSystem infrastructure andSystem infrastructure and

features• An array of resource cells. • Heterogeneous cell array:

RR

R• Heterogeneous cell array:– Processing cell– Memory cell

R R

R

Memory cell– Accelerator

(e.g. no configuration)( g g )• Hierarchical cell array. • Dynamic reconfiguration Addr. gen

Coeff. gen

y g

• Currently looking at channel estimation MIMO for

g


y gLTE-A and Mapping strategies

DSP DesignAlt ti Si Bit S h i tiAlternative: Sign-Bit Synchronization

together with Leif Wilhelmsson @Ericsson• Huge complexity reduction at a cost Huge complexity reduction at a cost

of performance degradation• Area improvement for memories 97%

h d t 8 bitwhen compared to 8-bits• Area improvement for logic 70%

when compared to 8-bits p• Total Area improvement 93% when

compared to 8-bits


DSP DesignSign-Bit Synchronization: Performance

PerformancePerformanceDegradation.

Deemed OK for coarse synchronization


Deemed OK for coarse synchronization.

DSP Design

Multi-mode MIMO in LTE-A

Space Division Multiple Access: Increase cell spectrum efficiency


DSP DesignDifferent antenna configurationsDifferent antenna configurations

and modulation schemes


DSP Design

Objective: unified multi-mode signal detector

• Unified MIMO detector supporting multiple modespp g p• Integrate multiple detectors into a single module area efficiency


DSP Design

N d d RNeeded Resources

Operations MIMO TechnologiesSM SDMA SDSM SDMA SD

Matrix decomposition

Matrix-permutation

Node Selection InterferenceInterferenceCancellation

Euclidean Distance Sorter

• SM – using Imbalaced fixed-complexity sphere decoder• SDMA – using Matrix permutated fixed-complexity sphere decoder


• SDMA – using Matrix permutated fixed-complexity sphere decoder• SD – using Real-valued succesive interference calculation

DSP Design

E ample SDMAExample: SDMA • Unified at the architecture design levelg

• Multi-stage architecture corresponding to antennas• Activate different stages according to antenna configuration

4×44×4 Mode

2×22×2 Mode


DSP Design

Results Proposed work 65nm CMOS, other 0.13m CMOS p ,

technology Supports the largest number ofMIMO modes Supports the largest number ofMIMO modes Consumes the least hardware and energy

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se2011-11-30 SoS@STMicroelectronics

DSP Design

Life after OFDM:

Faster than Nyquist (FTN)Faster-than-Nyquist (FTN)

Signaling Tranceivers


DSP Design

FTN Signaling• Original concept by J E Mazo in 1975 (Bell Syst Tech J)• Original concept by J.E. Mazo in 1975 (Bell Syst. Tech. J).

• Main idea• Main idea– transmit info beyond Nyquist’s criterion for ISI free transmission.– Stack closer in time and/or freq – induce intentional interference.q

f


f

DSP Design


• Main idea• Main idea– transmit info beyond Nyquist’s criterion for ISI free transmission.– Stack closer in time and/or freq – induce intentional interference.q

f


f

DSP Design


• Main idea• Main idea– transmit info beyond Nyquist’s criterion for ISI free transmission.– Stack closer in time and/or freq – induce intentional interference.q– Investigate OFDM-systems due to their popularity– Reuse as much as possible from a ”standard” system

• Motivation: Bandwidth efficient systems– Alternative to higher order modulation– Study hardware feasability


DSP DesignFTN vs Orthogonal system

f

O th l

FTN vs. Orthogonal systemOrthogonal symbol

t

T∆F∆ =1


DSP DesignFTN vs Orthogonal systemFTN vs. Orthogonal system

f

Orthogonal symbolFTN symbol

T F 1t

T∆F∆ =1

T∆F∆ <1

Viktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se2010-12-03


fFTN vs. Orthogonal system


T F 1t

T∆F∆ =1

T∆F∆ <1





T F 1t

T∆F∆ =1

T∆F∆ <1





T F 1t

T∆F∆ =1

T∆F∆ <1


DSP DesignReceiver

Multicarrier demodulationFTN symbol reconstruction Iterative decoding

Receiverg


DSP Design

ReceiverFTN symbol reconstruction Iterative decodingMulticarrier demodulation g

Same

from

Same

matched filter

from Interleaver

tode-interleaverInterleaver

We try to keep as much as possible from a ”traditional” systemSame as in Transmitter


We try to keep as much as possible from a traditional system.

DSP Design

R lt R i fResults: Receiver performanceReceiver Performance at

various time spacings.

• Increased Bandwith efficiency,T =0.5 2x improvement

• BER-performance is degraded

ER

B

E

SNR in dBViktor Öwall, Dept. of Electrical and Information Technology, Lund University, Sweden-www.eit.lth.se

SNR in dB

DSP Design

Results: pre-optimization.Chip area: 0 5 mm2 in ST65 nm standard cell CMOS• Chip area: 0.5 mm2 in ST65 nm standard cell CMOS

• Power: 44mW (80% in the memories)• Throughput: 3.2Mbps at 300MHz.g p p• Tape-out: November 2010

• FTN-signaling is deemed feasable from a hardware perspective.

• Complexity overheadComplexity overhead.• Memory : same order as a max-log-MAP

implementation, (7,5) conv code.• Logic: ~5 times

Accepted for publication in:


Accepted for publication in:IEEE Transactions of Circuits and System – I (TCAS-I)

DSP Design

Analog DecodingAnalog Decoding


DSP Design

Channel decoding• Channel decoding is usually performed in the digital domain:

• Compare to Matthias Kamuf’s work.

• Many different types of codes,e.g.convolutional, block, turbo, LDPC,…

• and decoding algorithmsViterbi, BCJR, …

Di it lDi it lSigma DeltaA t Digital DecodingRF Front -End Digital

Baseband

Sigma Delta A-to-D

Converter

AntennaInterface


System Level Control

DSP Design

Alternative: Analog decodingAlternative: Analog decodingFirst introduced by Joachim Hagenauer, TU Münich, in 1998

Why analog decoders:• very low power consumption• less silicon area

What does technologyscaling do?• less silicon area

• high throughput due to parallel computationsAnalog

D diAlternative Decoding

scaling do?

D t A

Decoding

Detection Analog

gApproaches

Di it lDi it lSigma DeltaA t

D-to-ADetection & Synch.

Analog Decoding

Digital DecodingRF Front -End Digital

Baseband

Sigma Delta A-to-D

Converter

AntennaInterface



DSP Design

M ti tiMotivation• Design the analog decoding cores for various codes.

• Most prior work has been designated as proof of concept and notsystem level aspects. We will investigate system level aspects ofy p g y panalog decoding, e.g.

• Can we make it fit in a “traditional” digital system?• What is needed to do everything in analog domain?What is needed to do everything in analog domain?

Analog Decoding

Alternative Decoding A h

D-to-A

g

Detection & Synch.

Analog Decoding

Approaches

Digital DecodingRF Front-End Digital

BasebandSigma Delta

A-to-DConverter

AntennaInterface



DSP Design

Analog decoder: analog in/digital out


DSP DesignAnalog Core Module for BCJRAnalog Core Module for BCJR

Analog CoreThe structure of the core

will decide the code, e g Hamming ore.g. Hamming or

tailbitingconvolutional (7,5)

Analog Core Module used for BCJR calculations.


DSP DesignShort on BCJRShort on BCJR

L. R. Bahl, J. Cocke, F. Jelinek, and J. Raviv, “Optimal decoding of linearcodes for minimizing symbol error rate ” IEEE Trans Inform Theorycodes for minimizing symbol error rate, IEEE Trans. Inform. Theory,vol. 20, no. 3, pp. 284–287, Mar. 1974.Example: in a circular trellis make one forward, , and one backward, , recursionrecursion.


DSP Design

A l C M d l f BCJRAnalog Core Module for BCJR

Forward metric calculationsForward metric calculations in BCJR algorithm.Backward in the same way. Equivalent analog circuit.


y Equivalent analog circuit.

DSP Design


Forward metric calculationsForward metric calculations in BCJR algorithm.Backward in the same way. Equivalent analog circuit,


yValues represented as currents.

DSP Design





DSP Design





DSP Design





DSP DesignAlternative structure: digitalAlternative structure: digital

in/digital outg


DSP Design

Decoder Output for a Single BitDecoder Output for a Single Bit

1decision

0level

Cadence netlist simulations:• Less than 4 µs is needed to decode the transmitted codeword

D i i h i it t t d t t


• Decision: when circuit converges to an steady state

DSP DesignResults: Analog Hamming DecoderResults: Analog Hamming Decoder

Input interface still to be optimized.


DSP Design

Decoder Structures• (8,4) Hamming block code

• (7,5) convolutional tailbiting code


DSP Design

Grand Slam at SSF!Grand Slam at SSF!LTH have been very succesful this year and attracted three large SSF Grants:attracted three large SSF Grants:

• DARE – Digitally Assisted Radio EvolutionDARE Digitally Assisted Radio EvolutionPI Pietro Andreani

• Distrant - Distributed Antenna SystemsPI Fredrik Tufvesson

• HiPEC - High Performance Embedded ComputingPI Kris KuchcinskiPI Kris Kuchcinski

” – Vi bedömer strategiskt relevans och vetenskaplig kvalitet på ansökningarna och där låg Lund bäst till i denna utlysning ” Joakim Amorin SSF


och där låg Lund bäst till i denna utlysning. , Joakim Amorin, SSF

DSP Design

This last part will NOT be in theThis last part will NOT be in the exam!

Just a flavor on what we’reJust a flavor on what we re working on…g


dsp design eu fp7 project multibase some research …jsj. svensson3, lv d pl. van der perre2, l....

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