dsp design –lecture1 introductionand dsp basics steffen … · 2020. 1. 21. · –lars...
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Design – Lecture 1
Introduction and DSP Basics
Steffen Malkowsky, PhD
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
LecturersFredrik Edman Mail: [email protected] E:2538
Steffen MalkowskyMail: [email protected] E:2334
Sidra Muneer (exercises & labs)Mail: [email protected] E:2339
…and several invited speakers!
Course AdministratorErik Göthe [email protected] E:3152b (3rd floor in the north-west part of the building)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Course information• www.eit.lth.se/course/etin45
• Lectures– Please see detailed schedulehttps://cloud.timeedit.net/lu/web/lth1/ri1X50gQ0560YfQQ25Z5974Y0Zy7007315Y61Q569.html
• Seminars – Please the detailed scheduled– No seminar 1st week
• Labs- Lab 1 Wednesday 5th Feb between 8 - 12 - Lab 2 Wednesday 12th Feb between 8 - 12 - Lab 3 Wednesday 19th Feb between 8 - 12 - Lab 4 Wednesday 4th March between 8 - 12
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Course information• Register for course
– Done by signing up for labs– Do this before Friday, 24th Jan. 12.00– Registration is needed for
• Getting access to labs• Getting access to software used in lab• If you miss this deadline, you may not be
able to participate in first lab!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Compulsary Parts
• Pass 4 Laborations (MATLAB & Hardware design in CatapultC)• Pass Homework exercises & Homework seminar
a results in grade 3
• Written exam for grade 4 & 5
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Litterature
• Course Litterature– Keshab K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation
• Extended Reading – Alan V. Oppenheim, Ronald W. Schafer with John R. Buck, Discrete-Time Signal
Processing, Prentice Hall, 1999, ISBN 0-13-754920-2.– John G. Proakis and Dimitris Manolakis, Digital Signal Processing: Principles,
Algorithms and Applications, Prentice Hall, 1995, ISBN 0133737624.– Sanjit K. Mitra, Digital Signal Processing. A Computer Based Approach, McGRAW-HILL,
2001 ISBN: 0-07-118175-X– Lars Wanhammar, DSP Integrated Circuits, Academic Press, 1999, ISBN 0-12-734530-2– etc.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Scope of the Course
How to get from a signal processing algorithm to an EFFICIENTimplementation using a number of ”tools” such as;
– Different numbering systems– Pipelining– Parallelism– Unfolding/Folding– Strength reduction, i.e. complexity of operations.– etc, etc,...
in a structured way according to the specification!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
GoalsAims: Knowledge
After completing the course the student should: – have gained an understanding for the relationship between parameters such as
calculation capacity, power consumption and silicon area – be familiar with transformations that help the designer to develop different
solutions for a given signal processing algorithm. – understand how different number representations affect the solution.
Aims: SkillsAfter completing the course the student should:
– be able to suggest an architecture from a given set of criteria. – be able to analyze an architecture and suggest alternative solutions.
Aims: AttitudeAfter completing the course the student should:
– have gained an overview of the field of implementation aspects of signal processing algorithms.
– feel well equipped to design an application specific processor given a specification using the methodologies covered in the course.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Introduction to DSP
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Definition DSP (Digital Signal Processing)
• Digital signal processing (DSP) is the mathematical manipulation of an information signal to modify or improve it in some way. It is characterized by the representation of discrete time, discrete frequency, or other discrete domain signals by a sequence of numbers or symbols and the processing of these signals.
• Digital signal processing (DSP) is the process of analyzing and modifying a signal to optimize or improve its efficiency or performance. It involves applying various mathematical and computational algorithms to analog and digital signals to produce a signal that's of higher quality than the original signal.
Wikipedia
Technopedia
Be aware that sometimes DSP = Digital Signal Processor!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Example of DSP Applications• Speech & Audio
– coding, MP3– recognition– echo cancellation
• Image– coding, MPEG4– Filtering
• Wireless Communication– channel coding/decoding– equalization– channel estimation– smart antennas
• beam forming• MIMO, Multiple Input Multiple Output
• Seismology– classification– recognition
• Radar and sonar– classification– detection
• Financial signal processing– filtering– classification– Calculations– Bvlock chain technology
• Biomedicin– smart sensors– telemedicin– pacemakers– Image processing
• ESS, MAX IV, etc.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Definition DSP (Digital Signal Processor)
• Digital signal processor (DSP) A digital signal processor (DSP) is a specialized microprocessor, with its architecture optimized for the operational needs of digital signal processing.
The goal of DSPs is usually to measure, filter and/or compress continuous real-world analog signals. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but dedicated DSPs usually have better power efficiency thus they are more suitable in portable devices such as mobile phones because of power consumption constraints.
Wikipedia
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Programmable or Custom DSPs
What to use depends on requirements– Sample rate– Throughput– Energy consumption– Area– Wordlength – precision– Flexibility– Time to market– Volume/size
Different types of Digital Signal Processors
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Extremely Low Power
Where do we find them?
Very Low Power
Low Power
Large volume of data
High performance computing
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
What’s happening inside the DSP?
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
In the DSP an (DSP) algorithm is executed!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The heart of DSP algorithms are usually DSP ”Primitives”
• Convolutions• Filters
– FIR– IIR– Wave digital
• Correlation• FFT - fast Fourier transform• DCT - discrete cosine transform• LMS – Least Mean Square• etc...
Examples:
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design An application is often comprised of many different blocks (incl. DSPs)
Example: Massive MIMO
Frequency Time
Frequency Time
Space
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
There are several ways of implementing a DSP-algorithm in hardware.
• Microprocessor/µcontroller – is a small computer on a single integrated circuit which may contain a processor core, memory, and programmable input/output peripherals.
• Digital Signal Processor (DSP) – a specialized microprocessor, with its architecture optimized for the operational needs of digital signal processing.
• Field-Programmable Gate Array (FPGA) - an integrated circuit designed to be configured after manufacturing.
• Application-Specific Intergated Circuit (ASIC) - is an integrated circuit customized for a particular use.
Hardware Implementation Techniques
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Architectural Options –Standard Processor vs. Special Purpose
Algorithm
Standard Processor
• Programable/Flexible• Short design time/TTM • Low price?
SpecialPurpose
• High calculation capacity• Low power consumption• Low price at volumeMain focus of this Course
FPGA “ASIC”
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Different applications, different demands...(a simplified view)
FlexibiltyComplexity
Low powerLow costFlexibilty
Lower powerLower cost
ProcessorsFPGAs
ProcessorsASICs
ASICsProcessors
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
This course mainly looks at specialized architectures
Could be used for eitherFPGA or ”ASIC”
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Energy Efficiency
One of the key design issues!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Utilizing the computation time
MIPS
TimeMax computationtime
Compute as fast as we can?
Compute as slow as we’re allowed?
• Can we control the clock frequency?
• What power down options do we have?– clock gating– various sleep modes
• Can we scale the power supply?– Dynamic– How many levels
• What cell library can we choose?– Low power– High speed
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Energy efficiency (MOPS/mW)depends on type of application
0,01
0,1
1
10
100
1000
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Ener
gy an
d Ar
ea E
ffici
enci
es
Chip Number (see next slide)
MicroprocessorsDedicatedDesignsGeneral
Purpose DSP’s
Courtesy: Professor Bob Brodersen, UC Berkeley
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
ISSCC Chips (0.18μm –0.25μm)
Energy efficiency (MOPS/mW)depends on type of application
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Trends in processors
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Complexity
A constant challenge!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
ComplexityComplexity of Algorithms are increasing
with new systemsNumber of transistors possible to implementon a die was always increasing (Moore’s law)
Often mature algorithms (systems) go to non-custom solutions.
But there is always new algorithmsand there is power and price...
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Evolution• New systems
– i.e. high performance– use non-standard architectures and components– e.g. 5G
• Mature systems– i.e. low performance compared to state of the art– implemented on standard platforms– mature technologies– e.g. GSM, 3G
New 1 Mature 1 New 2 Mature 2New 3
Evolution
Mature 3
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Important questions when designing hardware architectures
Which structure gets the job done?
Which structure use the least amount of energy?
Which structure use the least amount of area?
Etc, etc, etc...
How do we design architectures to achieve it?
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Basics Filters
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Digital signal processing algorithms works on samples of a continous signals.
Sampling rate = nr. of samples processed/second
Analoga
DigitalDigitalSignal
Processing
Continoussignal
Sampledsignal
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Two Basic DSP Structures
x(n)
D D Dx(n)
h0 h3h2h1
y(n)
D
D
y(n)
FIR – Finite Impulse Response
4-tap FIR filter
No feedback
IIR – Infinite Impulse Response
Biquad section
Feedback
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter
( ) ( ) ( )å-
=
-=1
0
N
kknxkhny
h(.) is the impulse response which defines the filter response, e.g. low- or highpass.
D D Dx(n)
h0 h3h2h1
y(0)
x(n-1) x(n-2) x(n-3)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter - Definitions
( ) ( ) ( )å-
=
-=1
0
N
kknxkhny
D D Dx(n)
h0 h3h2h1
y(0)
x(n-1) x(n-2) x(n-3)
• The filter length is = N• The filter order is = N-1• The number of filter taps = the filter length
A higher order filter, more taps, will result in a steeper filter function but has higher complexity!
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Quick look at filter order, length and taps
D D Dx(n)
2 864
y(n)
x(n-2) x(n-3) x(n-4)
Suppose that we have the following filter:y[n]=2x[n]+4x[n−2]+6x[n−3]+8x[n−4]
Dx(n-1)
What is the filter length, filter order and number of taps?
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Quick look … answery[n]=2x[n]+4x[n−2]+6x[n−3]+8x[n−4]
D D Dx(n)
2 864
y(n)
x(n-2) x(n-3) x(n-4)D
x(n-1)
Filter length: the filter length is 5, i.e. the filter extends over 5 input samples [x(n),x(n−1),x(n−2),x(n−3),x(n−4)].
Filter order: The order of an FIR filter is filter length minus 1, i.e. the filter order in the example is 4. (The filter order is the max. delay needed, so if your filter is y(n)+y(n−10)=x(n) you have a filter order of 10)
# filter taps: The number of taps is the same as the filter length. In this case you have one tap equal to zero (the coefficient for x(n−1)), so there is 4 non-zero taps. Still, the filter length is 5.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Example: FIR filter in MatlabD D Dx(n)
h0 h3h2h1
y(n)
FIR-filters can be designed with the built-in filter functionfir1(N,Wn) – N’th order filter with the cut-off frequency Wn must be between 0 < Wn < 1.0, with 1.0 corresponding to half the sample rate.
1 2 3 4 5 6 7 8 90
0.05
0.1
0.15
0.2
0.25
0 5 10 15 20 25 30 35-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
32-taps 8-order
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
FIR-filter frequency response
0 200 400 600 800 1000 12000
0.2
0.4
0.6
0.8
1
1.2
1.4
Use fft to transform h(.) to frequency domain and plot.
Symmetry when real input to fft.
32-taps8-taps
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Linear phase FIR filters
0 5 10 15 20 25 30 35-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
Linear phase filters has a constant group delay in the passband, i.e. all frequency components are delayed equally a no phase distortion!
Linear phase filters, e.g. from fir1(), has symmetric coefficients.This can be used to simplify the filter structure.
Dx(n)
h0 h2h1
D
h4
y(n)
D
h3
Dx(n)
y(n)
D
D D
D
0 5 10 15 20 25 30 35-0.02
0
0.02
0.04
0.06
0.08
0.1
0.12
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design The FIR filter, hardware mapped,
first clock cycle( ) ( ) ( )å
-
=
-=1
0
N
kknxkhny
x(0)
h0 h3h2h1
y(0)
x(-1) x(-2) x(-3)REG
REG
REG
clock
)3()2()1()0()0( 3210 -+-+-+= xhxhxhxhy
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The FIR filter, second clock cycle
( ) ( ) ( )å-
=
-=1
0
N
kknxkhny
x(1)
h0 h3h2h1
y(1)
x(0) x(-1) x(-2)REG
REG
REG
clock
)2()1()0()1()1( 3210 -+-++= xhxhxhxhy
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
( ) ( ) ( )å-
=
-=1
0:
N
kknxkhnyFIR
D D Dx(n)
h0 h3h2h1
y(n)
cMUX
REG
1 sample/ccN fixed multipliersN-1 adders
N cc/sample1 generalized multiplier1 adders1 coefficient memory+ control
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(n)
SampleMem
y(n)
0
REG D D Dx(n)
h0 h3h2h1
y(n)
How many clock cycles?
Why the ”0”?
Why the extra reg?
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(0)
SampleMem
y(-1)
0
REG D D Dx(n)
h0 h3h2h1
y(n)
h(0)
cc0: x(0)h(0)+0
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(-1)
SampleMem
y(-1)REG D D Dx(n)
h0 h3h2h1
y(n)
h(1)
cc0: x(0)h(0)+0cc1: x(-1)h(1)+x(0)h(0)
x(0)h(0)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(-2)
SampleMem
y(-1)REG D D Dx(n)
h0 h3h2h1
y(n)
h(2)
cc0: x(0)h(0)+0cc1: x(-1)h(1)+x(0)h(0)x(-1)h(1)+
x(0)h(0)cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(-3)
SampleMem
y(-1)REG D D Dx(n)
h0 h3h2h1
y(n)
h(3)
cc0: x(0)h(0)+0cc1: x(-1)h(1)+x(0)h(0)
x(-2)h(2)+ x(-1)h(1)+ x(0)h(0)
cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0)cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(1)
SampleMem
y(0)REG D D Dx(n)
h0 h3h2h1
y(n)
h(0)
cc0: x(0)h(0)+0cc1: x(-1)h(1)+x(0)h(0)
cc2: x(-2)h(2)+ x(-1)h(1)+x(0)h(0)cc3: x(-3)h(3)+ x(-2)h(2)+ x(-1)h(1)+x(0)h(0)
0
cc4: x(1)h(0)+0; new iteration
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
Time multiplexed to save hardware
coeffMUX
REG
x(n)
SampleMem
y(n)
0
REG
FSMFinite State Machine
CONTROL
load
address
reset
sample
D D Dx(n)
h0 h3h2h1
y(n)
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form I
( ) ( ) ( )0 1
m n
i ji j
y n b x n i a y n j= =
= - + -å åThe impulse response also includes feedback terms.
• Steeper impulse response but possibility for instability
y(n)x(n)
Z-1
+
Z-1
Z-1
+
+
b0
b1
bm-1
bm
Z-1
+
Z-1
Z-1
+
+
a1
an-1
an
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form II( ) ( ) ( )
0 1
m n
i ji j
y n b x n i a y n j= =
= - + -å åEach part is a linear time-invariant system
and the order can be reversed.x(n)
Z-1
+
Z-1
Z-1
+
+
b0
b1
bm-1
bm
y(n)
Z-1
+
Z-1
Z-1
+
+
a1
an-1
an
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, direct form II( ) ( ) ( )
0 1
m n
i ji j
y n b x n i a y n j= =
= - + -å åThe two parts can be collapsed into one with a
minimum number of delay elements.
x(n)
Z-1
+
Z-1
Z-1
+
+
a1
an-1
an
+
+
+
b1
bm-1
bm
y(n)b0
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
The IIR filter, cascade form
( ) ( )1 2
0 1 21 2
1 1 2
; 1 / 21
sNk k k
k k k
b b z b zH z Ns Na z a z
- -
- -=
+ += = +ê úë û- -Õ
x(n)
D
D
y(n)
• Often cascaded with shorter sections which are combined,easier to design when fixed-point arithmetic.
• The above is often referred to as biquad sections.
D
D
D
D
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DSP Basics DFT - FFT
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DFT - FFT
• The Discrete Fourier Transform (DFT) is a mathematical operation. The Fast Fourier Transform (FFT) is an efficient algorithm for the evaluation of that operation (actually, a family of such algorithms).
• The fast Fourier transform (FFT) samples a signal over a period of time (or space) and divides it into its frequency components.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
DFT - FFT
• The DFT/FFT is one of the most common digital signal processing algorithms.
• Used to determine frequency content of a discrete signal sequence.
• Transform between time and frequency domains.
• The FFT is a low complexity way of computing the DFT.
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
N-point DFT
1,...,1,0,)()(1
0-==å
-
=
NkWnxkXN
n
knN
NknjknN eW /2p-=
N filters of length N a O(N2)
NN
N
Only every Nth sample
x(n) X(0)X(1)
X(N-1)
• The DFT determines spectral content at N equally spaced frequency points, i.e. coorelates with different frequencies,
• N samples are needed.
( ) sampleanalysis
mff m
N=
Complex
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
X(3)
X(15)
X(7)
X(11)
X(1)
X(13)
X(5)
X(9)
x(12)
x(15)
x(14)
x(13)
x(8)
x(11)
x(10)
x(9)
W 8
X(2)
X(14)
X(6)
X(10)W 2
W 6
X(0)
X(12)
X(4)
X(8)
x(4)
x(7)
x(6)
x(5)
x(0)
x(3)
x(2)
x(1)
W 7
W 5
W 6
W 4
W 3
W 1
W 2
W 0
W 6
W 2
W 4
W 0
W 0
W 0
W 4
W 0
W 4
W 0
W 4
W 0
W 4
stages)(log2 N
)(log2
)(
2
2
NN
NODFT
FFT
FFT is low complexity DFT
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Steffen Malkowsky, Dept. of Electrical and Information Technology, Lund University, Sweden - www.eit.lth.se
DSP Design
End of Lecture 1
See you on Thursday