dsp c 5000 chapter 8 direct memory access (dma) copyright © 2003 texas instruments. all rights...

DSP C 5000DSP C 5000

Chapter 8Chapter 8Direct Memory Access (DMA)Direct Memory Access (DMA)

Copyright © 2003 Texas Instruments. All rights reserved.Copyright © 2003 Texas Instruments. All rights reserved.

Copyright © 2003 Texas Instruments. All rights reserved.

ESIEEESIEE, Slide 2 Copyright © 2003 Texas Instruments. All rights reserved.

Direct Memory AccessDirect Memory Access

In a real-time system, DMA is used to transfer data In a real-time system, DMA is used to transfer data from peripheral/memory and memory/peripheral from peripheral/memory and memory/peripheral without burdening the CPU :without burdening the CPU :

DMADMA

Input DataInput Data

serial or parallelserial or parallel

MemoryMemory

internal/externalinternal/external

Let’s see how theLet’s see how theDMA performsDMA performs

its tasks...its tasks... C55xC55x

C54xC54x



Performs data transfers without CPU intervention

Terminology- Element: basic unit of transfer (1, 2 words)- Frame: multiple elements (1-64K)- Block: multiple frames (1-256)

SRC address DST addressSOURCESOURCE DESTDEST

Transfer dependent upon:- Source/destination address- Rotating priority between channels- Event sync (different events can be selected)- Element/Frame count- Index (can select: no modification, inc/dec by 1 and element/frame index)

Max Speed: One 16-bit word per 4 CPU cycles (all channels combined)

Element 1Element 2Element 3Element 4

Frame 1Frame 2Frame 3Frame 4

C54x Direct Memory Access (DMA)C54x Direct Memory Access (DMA)



DMA Channels 0-5Source Destination

Elem Index Frame Index

Control Status

DE[5:0] Enable/disable channelsINTSEL Interrupt Multiplex Control

DPRC Channel Priority (Hi or Low)

Free Emulation Control

EHPI

EHPIAuxiliaryChannel

DMA “Resources”

PeripheralsPeripherals

Ext’l MemExt’l MemSARAMSARAMDARAMDARAM

DMPREC Register

14 7 5DE[5:0]INTSELDPRC[5:0]Free

0613 8AUTOIX

15

Only the ‘C5409, ‘10, ‘16, ‘21 and ‘41 support external DMA accesses

DMABus

Elem Count Frame Count

DMA Registers and ResourcesDMA Registers and Resources

AUTOIX Extended reload mode



DMSFCn (Sync Event and Frame Count)DMSFCn (Sync Event and Frame Count)

1515 88rsvdrsvd Frame CountFrame Count

007710101111DBLWDBLWDSYN[3:0]DSYN[3:0]

1212

Frame Count: N-1 (N is desired # of frames) DBLW: Double-word mode (0: 16-bit, 1: 32-bit) DSYN: DMA sync event

DMMCRn (Transfer Mode Control)

15AUTOINIT

5DMD

041011DINDDLAXSDMSSINDSLAXS

8 7 6 2 1

DMD: Destination Address Space (Program, Data, I/O) DIND: Destination Index (none, +, -, element/frame index) DLAXS: Internal/External Access (0/1) DMS: Source Address Space (Program, Data, I/O) SIND: Source Index (none, +, -, element/frame index) SLAXS:Internal/External Access (0/1)

DMA RegistersDMA Registers

DINM IMOD CTMOD14 13 12



DMA Registers - DMA Registers - Synchronisation ExampleSynchronisation Example Index and Frame offset are 16 bits signedIndex and Frame offset are 16 bits signed Example: Example: data data sortingsorting



DMA Registers – DMA Registers – ABU ModeABU Mode Implements circular buffering.Implements circular buffering.

Indefinite number of transfers.Indefinite number of transfers. Base address must be a power of two, 2Base address must be a power of two, 2r r >>NN, ,

with with NN being the being the bufferbuffer size size.. One side must be without address modification One side must be without address modification

and the other can only use an and the other can only use an indexingindexing mode mode..

McBSP

DRR DMSRC1=DRRDMDST1

1E572089F57B...DEAD

3000h

30FFhDMCTR1 DMSFC1



DMA Registers – Interrupt ModeDMA Registers – Interrupt Mode

DINM, IMOD DINM, IMOD and and CTMOD CTMOD specify specify interrupt mode:interrupt mode: DINMDINM: no interrupt on transfer completion if : no interrupt on transfer completion if

0.0. CTMODCTMOD: : multiframemultiframe mode if 0, mode if 0, ABUABU mode if 1. mode if 1. IMOD: IMOD: depend on depend on CTMODCTMOD

Multiframe mode: interrupt occurs at end of block Multiframe mode: interrupt occurs at end of block transfer if 0, else at the end of each frame and at the transfer if 0, else at the end of each frame and at the end of block transfer.end of block transfer.

ABU mode: interrupt occurs when buffer is full if 0, ABU mode: interrupt occurs when buffer is full if 0, else at half buffer full and at buffer full condition.else at half buffer full and at buffer full condition.



DMSRCnDMSRCnDMDSTnDMDSTnDMCTRnDMCTRnDMSFCnDMSFCnDMMCRnDMMCRn

Source AddressDestination AddressElement CountSync Event, Frame CountTransfer Mode Control

Writing to DMA registers is a multi-step process using sub-bank addressing

DMSADMSDNDMSDI

Sub-bank AddressData RegisterData Register with auto-increment

Using sub-bank addressing with auto-incrementDMSRC0 .set 00h

STM DMSRC0,DMSA ;init DMSA to pt to DMSRC0 STM #1000h,DMSDI ;write 1000h to DMSRC0 STM #2000h,DMSDI ;write 2000h to DMDST0…etc.

MMR RegsSub-bank Regs

Writing to the DMA RegistersWriting to the DMA Registers

AnotherAnother example



Ch-3

Ch-2

Ch-0

High

Ch-5

Ch-4

Ch-1

Low Low serviced when high:- waiting for event sync- transfers are complete

DPRC[5:0]: determines DMA bus priority between channels- (hi-1, low-0) Affects access to the 16-bit DMA bus only- Can select high or low rotating priority (per element transfer):

Priority Access toData Buses:

EHPIDMA (Hi)DMA (Lo)

CPU

highest

lowest

DMA ThroughputDMA Throughput



Refer to the documentation for a complete list of the DMA registers

A/DMcBSP

DRR

DMA Ch0

DMSRC0=DRRDMDST0=80h

1E572089F57B...DEAD

80h

8Fh

Sync eventRRDY = 1

DMCTR0=15 DMSFC0=00h

DMGSA=DRR DMGDA=80h DMGCR=15 DMGFR0=00h

Global Reload Regs

Int to CPU

Selected sync event (e.g. RRDY=1) triggers element transfer(e.g. from DRR to 80h)

Interrupt can occur at end of block or end of frame/block DMA channel registers reloaded from reload registers at

end of block transfer IF auto-init enabled. Example shown transfers 16 values from DRR to the same

memory locations every frame

Example: Auto-Init and Sync EventsExample: Auto-Init and Sync Events



Example: Interfacing PCM3002 with DMAExample: Interfacing PCM3002 with DMA

A/DMcBSP2

DRR

McBSP2

DXRD/A

DMA4 DMA5

PINGIN

PONGIN

PINGOUT

PONGOUT

PROCES-SING



OverviewOverview

Create a new project Create a new project Retrieve Retrieve audioIOaudioIO..cdbcdb

(McBSP2 configuration already done) and (McBSP2 configuration already done) and save it in the project directory as save it in the project directory as audioIODma.cdbaudioIODma.cdb

Specify buffer declaration (circular Specify buffer declaration (circular addressing constraint).addressing constraint).

Configure DMA channels with GUI Configure DMA channels with GUI interface.interface.

Interrupt configuration for input DMA Interrupt configuration for input DMA channel channel



Create Source FileCreate Source File Take the file Take the file audioIODmaaudioIODma.c.c and add it to and add it to

the project.the project.



Buffer DeclarationBuffer Declaration Because of constraints on buffer address in Because of constraints on buffer address in

ABU mode, the buffer must declared and ABU mode, the buffer must declared and handled in a special way during linking.handled in a special way during linking.

Add this file Add this file audioIODmaaudioIODma..cmdcmd



DMA ConfigurationsDMA Configurations Open file audioIODma.cdb and go to CSLOpen file audioIODma.cdb and go to CSL

Add a DMA configuration named Add a DMA configuration named « DmaAudioRx ».« DmaAudioRx ».



DMA ConfigurationDMA Configuration Select ABU for circular bufferSelect ABU for circular buffer Interrupt on half and full buffer to Interrupt on half and full buffer to

implement Ping-Pong bufferingimplement Ping-Pong buffering Synchronisation on receive event from AD Synchronisation on receive event from AD

converter through McBSP2.converter through McBSP2.



DM

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DMA ConfigurationDMA Configuration Add a new DMA configuration Add a new DMA configuration

« DmaAudioTx ».« DmaAudioTx ».



DM

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DM

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DMA SettingsDMA Settings Select DMA4 for receive channelSelect DMA4 for receive channel



DMA SettingsDMA Settings Select DMA5 for transmit channelSelect DMA5 for transmit channel



DMA HandlingDMA Handling Declare handle to DMA channels in source file Declare handle to DMA channels in source file

and start transfer using CSL functions call.and start transfer using CSL functions call.



DMA Interrupt HandlingDMA Interrupt Handling Connect IRQ event from DMA4 to a function Connect IRQ event from DMA4 to a function

called RxBuffercalled RxBuffer

Unmask this interrupt and globally enable Unmask this interrupt and globally enable interrupts (interrupts (INTMINTM) )



DMA Interrupt HandlerDMA Interrupt Handler Add the DMA interrupt service routine « RxBuffer »Add the DMA interrupt service routine « RxBuffer »

Build and run the applicationBuild and run the application



Auto-Initialization: - At end of block, DMA copies reload registers to channel registers - Reload registers can be altered at any time - Every channel can select to use auto-init and reload registers - Allows user to provide “continuous” or “repetitious” operation

Other DMA IssuesOther DMA Issues



Performs data transfers without CPU interventionPerforms data transfers without CPU intervention

TerminologyTerminology- Element: basic unit of transfer (1, 2, or 4 bytes)- Element: basic unit of transfer (1, 2, or 4 bytes)- Frame: a group of 1 to 64K elements- Frame: a group of 1 to 64K elements- Block: a group of 1 to 64K frames- Block: a group of 1 to 64K frames

SRC addrSRC addr DST addrDST addrSOURCESOURCE DESTDEST

Transfer dependent upon:Transfer dependent upon:- Source/destination address- Source/destination address- Priority (rotating priority between channels, also Ch vs. CPU)- Priority (rotating priority between channels, also Ch vs. CPU)- - Event sync (20 different events can be selected for ‘C5510)- Element/Frame count- Index (can select: constant, increment, element/frame index)

Max Throughput:Max Throughput: Two 16-bit transfers (R/W) per cycle (2 different Ch’s) Two 16-bit transfers (R/W) per cycle (2 different Ch’s)

Element 1Element 1Element 2Element 2Element 3Element 3Element 4Element 4

Frame 1Frame 1Frame 2Frame 2Frame 3Frame 3Frame 4Frame 4

‘‘C55x Direct Memory Access (DMA)C55x Direct Memory Access (DMA)



DMA Channels 0-5DMA Channels 0-5SourceSource DestinationDestination

Elem CountElem Count Frame CountFrame Count

Elem IndexElem Index Frame IndexFrame Index

ControlControl StatusStatus

3232

3232

3232

1616 PeripheralsPeripherals

DMA “Ports”DMA “Ports”

EMIFEMIF

SARAMSARAM

DARAMDARAM

EHPIEHPI1616EHPIEHPI

AuxiliaryAuxiliaryChannelChannel

DMA Channels 0-5 have access to all ports DMA Channels 0-5 have access to all ports exceptexcept EHPI port EHPI port EHPI Auxiliary Channel has access to all ports EHPI Auxiliary Channel has access to all ports exceptexcept Peripherals port Peripherals port

Each CHx has: 2 32-bit buses (R/W) + 16-bit FIFO + 8 DMA regs Each CHx has: 2 32-bit buses (R/W) + 16-bit FIFO + 8 DMA regs shownshown

ReadReadBusBus

WriteWriteBusBus

16-bit FIFO16-bit FIFO

3232

3232

DMA Registers, ResourcesDMA Registers, Resources

EHPI share the auxiliary port with USB moduleEHPI share the auxiliary port with USB module



DMA vs EHPIDMA vs EHPI Global Control Register (Global Control Register (DMA_GCRDMA_GCR))

If If EXCLEXCL 0 all ports are connected. 0 all ports are connected. If If EXCLEXCL 1 ports in 1 ports in red red are disconnected and EHPI are disconnected and EHPI

have exclusive access to DARAM and SARAMhave exclusive access to DARAM and SARAM



DMA throughput is affected by the combination of:DMA throughput is affected by the combination of:

Ch-3Ch-3

Ch-2Ch-2

Ch-0Ch-0

HighHigh

Ch-5Ch-5

Ch-4Ch-4

Ch-1Ch-1

LowLow Low serviced when highLow serviced when high::- waiting for event sync- waiting for event sync- transfers are complete- transfers are complete

CPU has CPU has FIXEDFIXED priority over the DMA priority over the DMA- Affects access to: RHEA, EMIF, SARAM, DARAM- Affects access to: RHEA, EMIF, SARAM, DARAM

PRIO bitsPRIO bits: (DMA_CCRn:6) sets priority(hi/low) for DMA channel n: (DMA_CCRn:6) sets priority(hi/low) for DMA channel n

EHPI PRIO bitEHPI PRIO bit: (: (DMA_GCR:0) sets priority for EHPI Aux. channel:0) sets priority for EHPI Aux. channel- Affects access to the two 16-bit DMA buses- Affects access to the two 16-bit DMA buses- Can select high or low priority round robin (per element transfer)- Can select high or low priority round robin (per element transfer)

11

22

EHPI EXCL bitEHPI EXCL bit: (: (DMA_GCR:1)- Affects access to internal/external memory- Affects access to internal/external memory- EXCL=1: EHPI accesses internal RAM only, DMA external RAM only- EXCL=1: EHPI accesses internal RAM only, DMA external RAM only

33

DMA ThroughputDMA Throughput



DMA Service ChainDMA Service Chain ScenarioScenario

Service Service chain examplechain example



DMA InterruptDMA Interrupt Interrupts can be generated from multiple events for each Interrupts can be generated from multiple events for each

channel channel (DMA_CICR(DMA_CICR), all interrupts are Ored :), all interrupts are Ored :

Timeout : each resource access can be supervised thanks to a Timeout : each resource access can be supervised thanks to a counter.counter.

Drop : Synchronisation not serviced.Drop : Synchronisation not serviced. Half frame : At half of each frame.Half frame : At half of each frame. Frame : At the end of each frame.Frame : At the end of each frame. Last Frame : At the beginning of the last frame transfer.Last Frame : At the beginning of the last frame transfer. Block : At the end of the block transfer.Block : At the end of the block transfer.

Read Read DMADMA__CSRCSR to determine source of interrupt to determine source of interrupt



Problem: - Transfer a block of pixels from SARAM to a D/AProblem: - Transfer a block of pixels from SARAM to a D/A - Output via McBSP/DMA and sync transfer to D/A (ready) - Output via McBSP/DMA and sync transfer to D/A (ready)

Src: mem_8Src: mem_8

16-bit pixels16-bit pixels(SARAM)(SARAM) DMADMA

EXT_INT4EXT_INT4

There’s more to set up for the DMA channel ...There’s more to set up for the DMA channel ...

88 99 10101414 151516162020 212122222323

17171111

Dest: DXRDest: DXRDXRDXR

McBSPMcBSP

ReadyReadyD/AD/A

DD

DMA Channel n Source Destination Parameters Register (DMA_CSDPn)DMA Channel n Source Destination Parameters Register (DMA_CSDPn)

1515 55 11771313DSTDST BENBEN SRCSRC BENBEN SRCSRC PACKPACK SRCSRC DATADATA TYPETYPE

00668899DSTDSTDSTDST PACKPACK

12121414 22

FieldField Description Description Options Options Answer? Answer?

DST/SRC BENDST/SRC BEN Burst enableBurst enable no burst, 4 element burstno burst, 4 element burst

DATA TYPEDATA TYPE Element sizeElement size 1, 2, or 4 bytes1, 2, or 4 bytesSRC/DSTSRC/DST Port selectPort select SA/DARAM, EMIF, PeriphSA/DARAM, EMIF, Periph

DST/SRC PACKDST/SRC PACK Data packingData packing packed or non-packedpacked or non-packed

22

SARAM/PeriphSARAM/Periphnon-packednon-packed

no burstno burst

Setting Up a DMA Transfer (SARAMSetting Up a DMA Transfer (SARAMD/A)D/A)



FieldField Description Description Options Options Answer? Answer?

SRC/DSTSRC/DST AMODEAMODE Addr indexAddr index none, +, elem indx, frm indxnone, +, elem indx, frm indxWhat other registers need to be set up?What other registers need to be set up?




EXT_INT4EXT_INT4

88 99 10101414 151516162020 212122222323

17171111


McBSPMcBSP

ReadyReadyD/AD/A

DD

ENEN Ch enableCh enable 0: disable, 1: enable0: disable, 1: enable

SYNC Sync EventSync Event 20 options (plus no sync)20 options (plus no sync)FSFS Frame SyncFrame Sync 0: elem sync, 1: frame sync0: elem sync, 1: frame syncPRIOPRIO PriorityPriority 0: low, 1: hi0: low, 1: hi

EXT_INT4EXT_INT4000 (or 1)0 (or 1)

DMA Channel n Control Register (DMA_CCRn)DMA Channel n Control Register (DMA_CCRn)

1515 771313DSTDST AMODEAMODE ENEN PRIOPRIO

55 44FSFS SYNCSYNC

00668899AUTOAUTO INITINITSRCSRC AMODEAMODE

1414

1111 1010

11AUTOAUTO INITINIT Auto initAuto init 0: none, 1: auto init0: none, 1: auto init 00

frm indx/ nonefrm indx/ none

Setting Up a DMA Transfer (SARAMSetting Up a DMA Transfer (SARAMD/A)D/A)



DMA_CSSA_UnDMA_CSSA_Un

SRC starting BYTE AddressSRC starting BYTE Address

DMA_CSSA_LnDMA_CSSA_Ln

DEST starting BYTE AddressDEST starting BYTE Address

DMA_CDSA_UnDMA_CDSA_Un DMA_CDSA_LnDMA_CDSA_Ln

DMA_CENnDMA_CENn

# of Elements# of Elements

DMA_CFNnDMA_CFNn

# of Frames# of Frames

DMA_CEInDMA_CEIn

Element Index Element Index (in bytes)(in bytes)

DMA_CFInDMA_CFIn

Frame Index Frame Index (in bytes)(in bytes)

44 33 22 66




EXT_INT4EXT_INT4

88 99 10101414 151516162020 212122222323

17171111


McBSPMcBSP

ReadyReadyD/AD/A

DD

mem_8[23:16]mem_8[23:16] mem_8[15:0]mem_8[15:0] DXR[23:16]DXR[23:16] DXR[15:0]DXR[15:0]

Note: data labels, e.g. Note: data labels, e.g. mem_8mem_8 must be <<1 to form must be <<1 to form bytebyte address address

DMA Transfer - ExampleDMA Transfer - Example



Auto-Initialization:Auto-Initialization: - Each channel contains “config” and “working” register sets. When - Each channel contains “config” and “working” register sets. When

auto-init is enabled, the “working registers” are reloaded from the auto-init is enabled, the “working registers” are reloaded from the “config” registers (which you can access via I/O memory) “config” registers (which you can access via I/O memory)

- - Continuous operationContinuous operation: can change init/reload registers during current: can change init/reload registers during current block transfer. Next transfer uses new values. Does not stop DMA. block transfer. Next transfer uses new values. Does not stop DMA.

- - Repetitive OperationRepetitive Operation: same init/reload registers used every time: same init/reload registers used every time

Refer to the documentation for a complete list of the DMA registersRefer to the documentation for a complete list of the DMA registers

Other DMA IssuesOther DMA Issues

dsp c 5000 chapter 8 direct memory access (dma) copyright © 2003 texas instruments. all rights...

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