dsar: dsa aware routing with simultaneous dsa guiding ...byu/papers/c56-ispd2017-dsar-slides.pdf ·...

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DSAR: DSA aware Routing with

Simultaneous DSA Guiding

Pattern and Double Patterning

Assignment

Jiaojiao Ou1, Bei Yu2, Xiaoqing Xu1, Joydeep Mitra3, Yibo

Lin1, David Z. Pan1

1ECE Department, University of Texas at Austin2CSE Department, CUHK

3Mentor Graphics Inc.

Outline

Introduction

Problem formulation

Detailed routing algorithms

Experimental results

Conclusion

2

Introduction: Technology Scaling

3

AI / Cu / W wires

Planar CMOS

LE

HNW

VNW

eNVM

LELELE

SADP

SAQP

EUV LELE

10 nm 7 nm 5 nm 3 nm

EUV

EUV EBL

EUV DSA

Cu Doping

3D IC

Opto Connect

Graphene

CNT

FinFET

LELE

W LI

Patterning

Transistors

Co

mp

lexity

Interconnect

2005 2010 2015 2020 2025

[Courtesy ARM]

Technology Scaling: More Masks

4

Via

Mask 1

Mask 2

DSA GP on mask1

Metal 3Metal 2

Mask 3

Mask 4

DSA GP on mask2

Via density increases

Triple/Quadruple patternings are required

• Placement error problem

• Cost increases

More via: 1D design

(a) Original layout (b) Via layer with quadruple patterning

Motivation of DSA on Via Layer

5

Reduce mask number by grouping vias in the same guiding pattern

Reduce 2 mask with DSA

Consider DSA during Routing 1

6

Initial detailed routing without DSA consideration

3 masks are required


7



Reroute n1 and n3


8



Reroute n1 and n3

Reduce 1 more mask

Previous Works

DSA-aware detailed routing for via layer optimization [Du+, SPIE’14]

Resolve conflicts and infeasible via patterns during rip-up and reroute with negotiated congestion based scheme

Incapable to handle DSA with multiple patternings

More wire length may be introduced

Redundant Via insertion consideration [Lin+, ASPDAC’17]

Simultaneously consideration of redundant via insertion and guiding template feasibility

Increase redundant via insertion rate

Multiple patterning for via is not considered, not compatible for 1D design

9

Problem Formulation: DSAR

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DSA and double patterning aware detailed routing

Input:

▷ Netlist with source/target pins

▷ Feasible DSA patterns

▷ Design rules

Output:

▷ Minimize wirelength, unroutable nets

▷ DSA-DP compatible via layer

Forbidden Via distributionDSA design rules

Design Rules

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ViaCut mask

Metal 3Metal 2

More complex guiding templates

Pre-route Net Planning - 1

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Construct conflict graph

Vertices: bbox corners

Edge weight: DSA friendly? 1: 5


13





14





15





16





17





18





19





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Conflict graph constraints

At most 1 corner of each net


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Corners cross the pins of other nets


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Conflict graph bipartization

Pre-determine (estimate) the routing paths for nets


23




Conflict graph bipartization

Pre-determine (estimate) the routing paths for nets

Minimize deleted vertices from conflict graph

• DSA unfriendly vertices


24

Net ordering for undetermined nets

Smaller bbox (HPWL)

Overlaps

Route b first

Route a first

More WL

Detailed Routing - 1

Routing graph model

25

Routing box

Via insertedOne color assignment forbidden

All vias are forbidden


Routing box state update

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Red viaGreen via

All via forbidden grid

Red via is forbidden

Green via is forbidden

Empty via

M2 M3

Nearby routing box update Example


Routing scheme

Negotiated congestion based

A* search

27


Routing scheme

Negotiated congestion based

A* search

28

Post Routing Optimization

Assign DSA guiding patterns

Minimize DSA groups and conflicts

Edge bipartization

29

Post Routing Optimization

Assign DSA guiding patterns

Minimize DSA groups and conflicts

Edge bipartization

30

Experimental Setup

Implemented in C++

3.4GHz Linux server, 32GB RAM

ILP solver: GUROBI 6.5

OpenSparc T1 design:

M2, M3 for routing

[Du+,SPIE’14], 1D router

31

Routing Result Comparison

0

10000

20000

30000

40000

50000

60000

70000

ecc efc ctl alu div top

Conventional 1D router Du+,SPIE'14 DSAR

32

(a) Number of Vias

0

100000

200000

300000

400000

500000

600000



(b) Wirelength

0

50

100

150

200

250

300



(c) DSA conflicts

0

1000

2000

3000

4000

5000



(d) CPU(s)

1% better 1D router20% better SPIE’14


0

10000

20000

30000

40000

50000

60000

70000



33

(a) Number of Vias

0

100000

200000

300000

400000

500000

600000



(b) Wirelength

0

50

100

150

200

250

300



(c) DSA conflicts

0

1000

2000

3000

4000

5000



(d) CPU(s)


1% overhead 1D router15% better SPIE’14


0

10000

20000

30000

40000

50000

60000

70000



34

(a) Number of Vias

0

100000

200000

300000

400000

500000

600000



(b) Wirelength

0

50

100

150

200

250

300



(c) DSA conflicts

0

1000

2000

3000

4000

5000



(d) CPU(s)



269 conflicts 1D router8 conflicts SPIE’14


0

10000

20000

30000

40000

50000

60000

70000



35

(a) Number of Vias

0

100000

200000

300000

400000

500000

600000



(b) Wirelength

0

50

100

150

200

250

300



(c) DSA conflicts

0

1000

2000

3000

4000

5000



(d) CPU(s)



269 conflicts 1D router8 conflicts SPIE’14


Comparison between W/ and WO Net Planning

36

0.9

0.95

1

1.05

1.1

1.15

1.2

1.25


w/ net planning wo net planning

(a) Number of Vias

0.9

0.95

1

1.05

1.1

1.15



(b) Wirelength

0

0.2

0.4

0.6

0.8

1

1.2



(c) CPU(s)

With v.s. without net planning

▷ 19% less via number

▷ 8% less wirelength

▷ 7% more runtime

Conclusion

DSA and double patterning for via layer in detailed routing

Pre-route net planning

Routing model with DSA-DP consideration

Post-routing optimization to improve DSA guiding pattern assignment and decomposition

Future work

Adaptive to more routing layers

General to more DSA and multiple patterning considerations

37

THANK YOUQ&A

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dsar: dsa aware routing with simultaneous dsa guiding ...byu/papers/c56-ispd2017-dsar-slides.pdf ·...

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