IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 6. JUNE 1989 1125

Drain-Engineered Hot-Electron-Resistant Device Structures: A Review

JULIAN J . SANCHEZ, MEMBER, IEEE, KELVIN K. HSUEH, MEMBER, IEEE, AND THOMAS A. DEMASSA, SENIOR MEMBER, IEEE

Abstract-In this paper various MOS structures with specially de- signed drain regions are reviewed. Guidelines are established for the fabrication of hot-electron-resistant device structures. Additionally, suggestions are made with reference to device structures suitable for a manufacturing environment.

I. INTRODUCTION HE number of new hot-electron-resistant device T structures is linked to the fine degree of tailoring ac-

cessible through the combination of both ion implantation and sidewall spacer technology. The ability to tailor the drain has allowed the creation of a number of “drain-en- gineered structures” able to satisfy specific design re- quirements. This is especially advantageous since natural tradeoffs arise between device performance and reliabil- ity. The drain can be tailored to emphasize either im- proved device performance or reliability, as design re- quirements dictate.

It is well known that high electric fields near the drain induce hot-electron injection into the gate. Thus, to re- duce hot-electron injection, the peak electric field must be reduced. In earlier work performed by Miller [l], a re- duction in doping increased the junction breakdown volt- age by reducing the peak electric field. Later work per- formed on diffused junctions indicated that the breakdown voltage also depends directly upon the gradient of the dopant distribution [2], with increased grading resulting in devices with increased breakdown resistance. The in- crease in breakdown resistance was again attributed to a reduction of the peak electric field and led to one of the first hot-electron-resistant devices that employed a graded drain [ 3 ] . In this device, the sourceldrain was formed using a phosphorus implant rather than the conventional arsenic implant. Unfortunately, the penalty paid for using this technique is increased short-channel effects.

To reduce short-channel effects, both the dose and the energy of the As sourceldrain implant were lowered. This

Manuscript received April 21, 1988; revised February 21, 1989. The review of this paper was arranged by Associate Editor K . C. Saraswat.

J . J . Sanchez is with the CTMG Division, Intel Corp., Chandler, AZ 85224.

K. K. Hsueh is with the Semiconductor Division, Gould Inc., Pocatello, ID 83201.

T. A. DeMassa is with the College of Engineering and Applied Sci- ences, Department of Electrical and Computer Engineering, Arizona State University, Tempe, AZ 85287-5706.

IEEE Log Number 8927639.

proved to be an impractical solution since increased series resistance reduced drive capability. This problem was eventually resolved using tip [9] or spacer technology [ l l ] . Spacer technology has evolved as the preferable choice due to its simplicity, consistency, and manufac- turability. The majority of the devices discussed in this paper employ the spacer technology.

11. DEVICE STRUCTURES

Table I illustrates the large number of hot-electron de- vice structures that have been suggested to limit hot-elec- tron effects. Most of these devices have been fabricated with gate 9xide thicknesses (to,) between the range of 200-350 A and channel doping ( N B ) ranging from 1 x 10l6 cmP3 to 3 X 10” ~ r n - ~ . The hot-electron techniques employed in a particular structure as well as the advan- tages of the structure are indicated in this table. Doping profiles and references are also provided.

To more clearly comprehend each design criteria and device structure, the devices in Table I have been grouped according to a particular structure type or electrical char- acteristic. Strictly speaking, the grouping of the devices in such a manner is somewhat arbitrary to the extent that many of the devices employ several of these qualities. Nevertheless, proceeding in this manner allows us to categorize each device according to either the dominant characteristic or a newly added attribute to a previous hot- electron structure. The following labels are used in Table I to identify the different categories:

Si Devices with minimum short-channel effects. Gi Devices that employ graded drains. Li Devices that use low doping drains. Dj Devices with improved drive capability. Ji Devices in which the maximum current density is

below the surface.

We will now review each of these categories. The first class of drain-engineered structures ( S i ) placed

emphasis on minimizing short-channel effects. Initially, the conventional arsenic drain junction [ 3 ] was contin- ually scaled, reducing lateral penetration under the poly. This in turn increased device density and total die output while minimizing short-channel effects. The continual scaling of the junction eroded the conductivity of the

0018-9383/89/0600-1125$01.00 0 1989 IEEE

1126 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL 16. NO 6 . JUNE 1989

DEVlCE STRUCTURE

A s D R A I N

MINIMUM OVERLAP

H t l 4

D O U b L Y IMPLANTED A s D R A I N ,)

I

REF 5.6

TABLE I DEVICE S T R U C T U R E S W I T H REDUCED HOT-ELECTRON EFFECTS

I M P L A N T PROFILE ;ECHNIOUE/PERFORMANCf

IECHNIPUE

* Eo UNDER GATE

'ERFORMANCE

* GOOU ORlVE CAPABILIT GOOD SHORI CHANNf l PHOPE R T i t s

TECHNIQUE

+ NONE

'ERFORMANCE . I U I L L ~ N T %non[ ( t iANNLL P R O P t R l l f 5

I t C H N I O U E . t n t uu( t D * i p LJNOt R C A l t

PERFORMANCE

* tAIR RELlABl l l lY VERY GOOD SHORT CHANNEL PROPERTIES

CAPABILITY * W R Y GOOD OHlVE

DEVlCE STRUCTURE

GRADED D R A I N

G .

1 I

FULLY GRADED DRAIN

c2

K t F 5 6

'ARTIALLY GRADED DRAIN

6,

REF 5.6

I M P L A N T PROFILE

',IMII 4 k 10 I'AR IlAI L Y L K A D i U DRAIN B i l l I O W t H D I A K LONCLNIHAIION ANI) W D C H U i s i t w u i i o ~

TECHNIPLIE

GRADED DRAIN I t p REDUCED

PERFORMANCE

GOOD RELlABlLllY

TECHNIQUE

* L R A D t D DRAIN . iP atoucco t v UNOtH GATE

PERFORMANCE

+ COO0 REl lA8lLI IY I COO0 ORlVL CAPABILITY

TECHNIQUE. . t P nt i )ucED s GHAUED URAlN

PERFORMANCE - GOOD RELIABILITY * GOOD D R l M CAPABILITY . GOOD SHORT CHANNEL

PROPtRTlE 5

drain, thereby increasing drain resistance. Other than a slight drain overlap, the arsenic junction had little con- cern for reliability. The slight overlap to some extent min- imized the peak electric field, thus reducing hot electrons. However, the tradeoff between device performance and reliability with respect to drain overlap, was not clearly understood then. To estimate the minimum possible chan- nel length for this structure, both the processing parame- ters as well as a reasonable set of reliability criteria must be established. The processing parameterso for a typical conventional drain structure are to, = 230 A with the As drain implanted at 70 keV at a dose of 1 X loi5 cmP2. Threshold and punchthrough implants are performed at 40 keV (1 X 1012 cm-2) and at 100 keV (3 X 10l2 crnp2), respectively. For threshold voltage shifts AV, I 10 mV for 10 years, bipolar breakdown VBD 2 7 V, minimal V , lowering at VD = 5 V and punchthrough voltage VPt L 5.5 V, the minimum channel length suggested for this structure is 1.5 pm [7]. Variations from this minimum dimension will, of course, exist as one tradeoff between performance and reliability. It should be mentioned that AV, < 10 mV over 10 years may not be sufficient for many designs. Other benchmarks also used to assess de-

vice lifetimes are shifts in transconductance, drive capa- bility, and subthreshold conduction. However, the pres- ent criteria are widely used and many of the devices evaluated in this paper use these criteria. Therefore, we will use these criteria as a reference noting that this may not be sufficient for all designs.

The minimum overlap structures [4] represented the class of As drain structures that leaned heavily to device performance. Slight grading, which naturally arises at the edge of the junction, did little to minimize hot-electron generation. Though device performance did indeed in- crease in these minimum overlap structures, it was done at the expense of reduced reliability. In an effort to solve both the short-channel effects and drain-resistance prob- lem, a second minimum overlap structure, the doubly im- planted As drain [ 5 ] , [6], was introduced. The reduced junction depth near the drain promised to reduce the short- channel effects while the larger drain junction would re- duce the resistance. An added advantage was the in- creased drain-gate breakdown voltage that resulted from a softer drain comer. In terms of reliability, this structure has little to offer other than a softer drain corner, which at that time was not optimized in terms of reliability.

SANCHEZ er a / . : DRAIN-ENGINEERED HOT-ELECTRON-RESISTANT DEVICE STRUCTURES 1127

DEVlCE STRUCTURE

D O U B L Y DOPED D R A I N (DDD) L,

K t f tLY

REF 16

IMPLANT PROFILE

TABLE I (Continued from page 1126.)

TECHNIQUE/PERFORMANCF

TECHNlOUt

* LIGHTLY DOPED DRAIN * DRAIN GRADED I Ep REOUCtD

f p UNDER GAIL

P C H t OHMANCL

* GOOD RELIABIII IY COOU UKlVt LAPABIL l l>

TLCt INIQUt

P t l<t OHMANCt

* COOU K t l l A t l l l l l i + LOO[, StIOU1 CHANNt l

P n o P t k i i t i

t't kt UHMANC F . V L H i L O W R t l l A t 3 l l l I l * COO0 SHOKI C l iANNt l

PHDt't R I l E S VtRY LOOD DRIVE CAPABILITY

The search for improved device lifetimes resulted in the second class of structures (G;). These devices employed grading of the drain [3], [7] as a means of reducing the peak lateral electric field under the gate, which in turn reduced hot-electron generation. The first graded-drain structure was designed with a phosphorus drain. Phos- phorus was the dopant of choice since the diffusing coef- ficient was higher than that of arsenic's thus resulting in a larger graded region during anneal. Significant reduc- tion in hot-electron generation was obtained with the graded drain though both drain resistance and short-chan- ne1 effects increased.

The fully graded drain [5], [6] solved the resistance problem associated with the graded drain and if optimized properly could minimize short-channel effects to some de- gree. Further reductions in short-channel effects, while maintaining low drain resistance, could be obtained using a variation of the fully graded drain referred to as the par- tially graded drain. The partially graded drain [5], [6] minimizes short-channel effects by not enclosing the en- tire arsenic junction with phosphorus as suggested by Ta- ble I. With respect to conventional drains, this structure

DEVICE STRUCTURE

PROFILED LDD ( P L D D )

4

K t l 1 )

K t F 18

BURIED C t i A N N L 1

J,

REF 3

IMPLANT PROFILE

i !ou, , , , , , , ,

TECHNlQUE/PERFORMANCE

TECHNIQUE

* MEDIUM DOPED DRAIN * DRAIN GRADED - Ep REDUCED - Ep UNDER GATE

Pt R I OHMANCC

* VtRY 6001) RELlA0lLl lY V t R Y GOOD URlVt LAPAHILITY

1t ( HNlOUf

MtDlUM DOPLD DRAIN DRAIN GRAIXD . t p RLnucEn

l't HFOHMANLE . VERY GOOD R~LIABILIIY * VtRY GOOD SHORT

CtlANNCL PROI'ERll fS LlJOi1 DHlM CAPABILIIY

I t ( HNlOUL . Jp R t l O W SUHFACC

I't RF OHMANCL

t IA IH RtLIARILITY

spreads the drain potential over a larger surface area, re- ducing junction curvature and thus minimizing the peak electric field. The partially graded drain has been used successfully with 1.5 pm design rules [5].

The next category of devices employ a lightly doped drain [3], [7]-[ll]. The lightly doped drain reduces the peak electric field by spreading the drain voltage drop over a wider depletion region. This is accomplished by using both a lower dose and by grading the impurity profile. The lower dose and grading affect both the magnitude as well as the location of the lateral electric field. The peak lateral electric field for the conventional device lies just within the drain region, while the peak electric field for the lightly doped devices lies within the n- region near the n+ drain. This leads to electron injection taking place within the n- region of the lightly doped drain devices, while the con- ventional As drain has most of its injection taking place inside the n+ drain region. The location of the injection mechanism with respect to the drain influences the deg- radation rate as well shall later see.

The doubly doped drain [3], [5], [7], [12] (DDD) is the first of the lightly doped drain structures ( L ; ) to be dis-

1128 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 6. JUNE 19x9

DEVlCE STRUCTURE

R L f 19

H t F 20

BURIED I D D (BLDU)

J.

REF 21

~ ~~~

IMPLANT PROt I1 f

OIPW 1"")

TABLE I (Continued from page 1127.)

IfCHNIQIJF /PCRf OHMANCt

l L C H N l O U E . L i c H i i Y DOPED DRAIN DRAIN GRADEU

* Jp BElOW SURfACE

PCRf ORMANCC

GOOD RELlABlLllY * GOOD URlVt CAPABII I T Y

11 CHNlQUk

e I lGHlLY DOPECI [IRAIN * Jp Bf I OW SURF ACE

PIKFORMANC t . mou RFLIABII I T Y LOO0 DRIVE C A P A R l l I I ~

T I L H N l Q U E

* 1 IGHTLY DOPED DRAIN * Jp BFLOW SURFACE

PERFORMANCE

GOOD RELIABILITY GOOD DRIVE CAPABlLlTI

* GOOD SHORT CHANNEL PROPERTIES

DFVICE STRUCTURE

A.'

n RtGlON

REF 7 2

ALIGNLI) GRADED

( ACU L DO) J,

n <*.I'

RFF 21

JMOSFEl

J,

REF 23.24

OEPW 1"")

TtCHNIPUE/PERFORMANCE

TETIlNlOUt * MEDIUM DOPED DRAIN

* GRADFD DRAIN * Lp RLDUCED . JD BLLOW SURFACE

Pt K f ORMANCE

* VERY GOOD RCLlABlllTY * VlRY IIOOU D R I R

CAPARlLlTY

CHARAC IERISIICS . GOOD SHORT CIiANNLL

r r c t i N i a u t

LIGHTLY DOPED DRAIN GRADED DRAIN

I Lp HEDUCEO * Jp BELOW SURfACC

PE RFORMANCE

* tXCELLFNT RELlABlLllY E XCEL L f N 1 DRIVE CAPABILITY

CHARACTERISTICS . GOOD SHORT CHANNLL

TL CHNIQUE

* MEDIUM DOPED DRAIN * GRADED DRAIN

t p REDUCED * Jp BELOW SURFACE

PERFORMANCE

GOOD RELIABILITY * GOOD D R l M CAPABILITY

GOOD SHORT CHANNEL PROPERTIES

cussed and is quite similar to the fully graded drain except that the phosphorus doping is much lower. This drain is composed of a shallow heavily doped arsenic region sur- rounded by a lightly doped phosphorus region. This struc- ture can be optimized quite well to minimize short-chan- ne1 effects and is highly manufacturable due to its simplicity. Assuming the same processing parameters, as well as the reliability criteria described earlier for the con- ventional As drain, the minimum channel length for the doubly doped drain with a phosphorus drain implant at 40 keV (5 x lOI3 cmP2) is 0.7 pm 171. Minimum gate lengths (poly line widths) for doubly doped drains are 1.1 pm.

Further reductions in gate lengths (not channel lengths) can be obtained with the LDD structure. The reduction in gate lengths is obtained by reducing the depth of the phos- phorus junction thus minimizing lateral penetration under the poly gate. Minimum channel lengths for the LDD structures are 0.7 pm (same as DDD). However, gate lengths for LDD devices under the same reliability crite- ria as DDD are significantly smaller. The reduction in gate lengths of the LDD device leads to increased packing densities. However, the DDD drive capability is superior to the LDD structure due to its higher drain doping. This results in higher switching speed for the DDD devices.

In early work on LDD devices, then n- drain doping was suggested to be about = 10"/cm3 [SI, 191. This cor- responds to a dose in the range of 5 x 10l2 to 2 X I0l3 /cm2. Unfortunately, though the LDD devices did reduce hot-carrier generation with respect to conventional devices, degradation was accelerated [ 131, [ 141. Fig. 1 illustrates this case. For the same level of hot-electron activity (same substrate current and stress time), the LDD (note Table I) device exhibits a higher reduction in drive current, implying that the LDD is more susceptible to damage from the generation of hot electrons. Though the device is more susceptible to hot-electron damage (higher degradation rate), it suffers less degradation for a given set of bias conditions, relative to conventional As drains. The reduced electron activity of LDD devices is directly attributed to the reduction in the drain electric field. The reduction in electric field reduces the level of substrate current and gate current as opposed to the conventional device.

The higher degradation rate of the LDD device was at- tributed to highly localized interface states and/or trap charge located above the lightly doped drain, resulting in increased drain resistance [ 141. Evidence suggesting that this was the case was obtained by measuring the substrate

SANCHEZ et al . : DRAIN-ENGINEERED HOT-ELECTRON-RESISTANT DEVICE STRUCTURES 1129

01 '1 01 I I

I I O

I sUb/w ( p A / p m )

SUBSTRATE CURRENT Fig. 1. (a) The relationship between the drain current reduction and sub-

strate current under stress for PLDD, LDD, and conventional [17].

current. Fig. 2 illustrates the substrate current versus gate voltage for different stress times. Observe that the in- creased substrate current occurs at a larger gate voltage (triode region) and stress time. These curves are similar to the curves that Katto et al. [15] generated by reducing the drain doping sufficiently.

It is rather curious that, as the gate voltage increases, the substrate current in the LDD device (Fig. 2) also in- creases. This is not the case for high drain doping. In the high drain doping case, the localized charge near the drain after stress cannot deplete the surface region below it. Hence, the substrate current characteristics remain essen- tially the same. However, in the low doping case, the lo- calized charge in the spacer region can deplete the region below it, even when the device has entered the triode re- gion [lo]. This localized depletion is able to support a high electric field inducing impact ionization between the nf As drain edge and the conducting channel, resulting in increased substrate current with respect to stress time. Since this localized charge lies outside the influence of the gate in the spacer region, increasing the gate voltage has two effects on the lateral electric field. First, the in- version layer moves toward the drain increasing the po- tential gradient between the n+ drain and the channel edge. Second, the conductivity of the channel increases reducing its ability to support a voltage drop. Therefore, as the gate voltage increases, the voltage drop across the drain end of the channel increases, leading to a rise in the lateral electric field. This in turn leads to impact ioniza- tion increasing the substrate current with V , as shown in Fig. 2. As the substrate current increases so does the gate current leading to a faster degradation of the device. This was observed by Katto et al. [ 151.

To avoid reduction in drive capability, one can increase the doping in the drain region, reducing drain resistance. This, of course, increases the peak electric field surround- ing the drain, thus increasing hot-carrier generation and quite possibly interface charge. Therefore, one must op- timize the doping such that the peak electric field is re- duced and the drain resistance due to localized charge is still minimized. One of the first devices in this class (0,) to employ this technique is the medium lightly doped drain

L 6 t

8 -

-

IO -

- 12 -

30000 -

STRESS. VD' 7 5v

i VG' 3v

GATE VOLTAGE V G ( V )

Fig. 2. The variation of the Ilub-VC characteristics for different stress times [141.

(MLDD) [ 161. The MLDD uses a dose concentration in the range of 4 X 10'3/cm2 to 1 X 10t4/cm2. This has resulted in four to five orders of improvement in lifetimes over the traditional LDD's with channel lengths down to 0.8 pm for V, = 5 V. It should be mentioned that the nomenclature (MLDD) has not traditionally been used and, to a large extent, many present day devices classified as LDD are really MLDD.

Drive capability can be further enhanced using the pro- filed lightly doped drain (PLDD) [17] structure. The PLDD is similar to the LDD with one exception. It em- ploys an additional As implant to further minimize reduc- tion in drain conductivity from oxide or interface charge. Channel lengths down to 1 pm have been fabricated using this structure. However, since the PLDD wa not opti- mized, the l-pm channel should not impose the limit.

Both the MLDD and PLDD increase drain doping in order to improve drive capability. Increasing the drain doping results in the peak electric field being located un- derneath the gate. Location of the peak electric field un- derneath the gate leads to an increase in the lifetime of the device by minimizing the drain-gate voltage drop when the gate voltage is high. More importantly, locating the peak electric field underneath the gate minimizes the ability of the localized charge to raise the drain resistance. That is, the gate is more able to control the conductance of the channel if the localized charge is underneath it. Therefore, at high gate biases the LDD device experi- ences more transconductance degradation after stress than the conventional device with its highly doped drain [ 131. This confirms the notion that reductions in drive capabil- ity can be minimized by locating the peak electric field underneath the gate.

So far we have discussed one method used to locate the peak electric field under the gate, that is, increase the drain doping. Another method that can be employed is to in- crease the drain-gate overlap region [4]. Unfortunately, this design philosophy is in contention with increased de- vice performance. Increasing the overlap region increases

1130 IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 6. J U N E 1989

the gate-to-drain capacitance, degrading rise and fall times. In addition, circuitry density decreases, punch- through voltages degrade, and threshold variation and other short-channel effects increase. Therefore, tradeoffs are involved between the desired hot-electron resistance and device performance, suggesting a compromise.

The DILDD [ 181, in addition to incorporating a me- dium doped drain, employs a p-type guard ring around the drain to minimize the extension of the drain depletion re- gion. This is advantageous in reducing short-channel ef- fects that eventually become the lower limit in optimized drain structures. To reduce dradsource resistance, the DILDD structure is fabricated with a platinum silicide drain. The platinum silicide also reduces gate resistance. Though the processing is quite complicated, the minimum channel length fabricated is 0.2 pm with a power supply of 3.5 V. It is expected that the smallest channels of all the drain-engineered structures presented in this review can be obtained using the DILDD.

The next class of structures ( I ; ) , in addition to some of the other hot-electron techniques discussed so far, direct the maximum current density away from the surface of the device. This reduces the probability of hot electrons reaching the gate. The buried channel [3] employs this technique quite effectively in reducing hot electrons. Over one order of magnitude improvement in device lifetimes can be obtained using a buried-channel device relative to conventional devices. The buried-channel device can be further improved using a lightly doped drain. In this case the device is referred to as the buried-channel LDD, which is a buried-channel device that incorporates a lightly doped drain. The buried LDD [19] exhibits two orders of mag- nitude improvement in gate current over a surface LDD. Channel lengths of 0.8 pm have been processed using this device structure.

The MLD [20] device varies the depth of the n- region. Two advantages result from this approach. First, the max- imum current density is directed away from the surface. Second, the maximum electric field and the maximum current density do not coincide, further reducing the num- ber of hpt electrons able to enter the oxide. In addition to reduction in hot electrons, the MLD reduces the drain- source resistance by using tungsten silicide over the drain/ source junction. Channel lengths of 0.8 pm have been fabricated using this technique.

The buried lightly doped drain (BLDD) [21] is similar to the MLD except no silicides are used when processing the drain, source, or gate regions. The major difference between the MLD and BLDD lies in the peak doping of the n- region. Simulation suggests that, for the MLD, the peak doping should be around 3 x lOI7/cm3 while the BLDD uses a peak doping of 1 X lOI8/cm3, the mini- mum channel length processed for the BLDD was 0.8 pm. The BLDD improves device lifetimes by over one order of magnitude over the conventional drain structure. To further reduce hot-electron generation, a graded BLDD (GBLDD) [22] drain can be incorporated. An n- phos-

- v) I I I I I I

12prn x 5 p m NMOS FET

0 SURFACE LDD

n BURIED LDD

0 GRADED/BURIED LDD '. I-

0 I I I I I

5 0 5 5 7.0 7 . 5 0.0 6 . 0 6 .5 * 16'1

DRAIN VOLTAGE ( V I

Fig. 3. Hot-electron limited lifetime as a function of drain voltage. Stress conditions are Vo = 6.5 V , V , = 3 V , and Vss = 0; channel length is 1.2 p n [21].

phorus implant is incorporated in addition to the buried n- As region used in the BLDD device. Again, 0.8 pm was the minimum channel length reported using this tech- nique. Finally, one can employ an aligned phosphorus graded drain [21] around the n- As buried drain. This should draw the maximum current density away from the surface, improving hot-electron reliability. Demonstra- tion of the inherent advantage of the aligned graded BLDD (AGBLDD) over the BLDD and the surface LDD struc- tures for devices under stress, are shown in Fig. 3 . The AGBLDD structure has been fabricated with channel lengths down to 1.2 pm. Since many of the devices re- ported in this class (Ii) were not optimized, further re- ductions in channel lengths should be possible. It should be noted that the hot-electron lifetimes of Fig. 3 are de- fined for devices under accelerated stress. Thus, under normal operating conditions, the device lifetimes are much higher.

Finally, an interesting structure that forces the current to flow below the surface is the JMOSFET [23]. The JMOSFET incorporates a p-type junction that works much in the same way as a JFET. The p-type junction pinches off the flow of current along the surface toward the drain, forcing the current to flow below the surface. In addition to forcing the current below the surface, the JMOSFET reduces the internal device voltages. That is, the effective drain bias can be set by device design, independent of the maximum externally applied drain and gate biases [24]. Furthermore, the JMOSFET allows a lower concentration to be used in the lightly doped n- regions without suffer- ing the adverse effects of hot-carrier injection into the sidewalls common to LDD's. The combination of these effects suggests that the JMOSFET should find applica- tion in submicrometer technology. Simulation suggests that channel lengths down to 0.7 pm are possible [23]. Though the JMOSFET does display some interesting ad- vantages, it is not simple to process or control.

SANCHEZ er al . : DRAIN-ENGINEERED HOT-ELECTRON-RESISTANT DEVICE STRUCTURES 1131

111. CONCLUSIONS Many types of modem MOS device structures have been

reviewed. The most successful hot-electron-resistant de- vice structures employ the following attributes:

1) The electric field should be spread over a wider re- gion (lighter doping, grading of drain, etc.).

2) The doping should be optimized so as not to reduce drive capability and interface state resistance, while reducing peak electric fields.

3 ) The peak electric field should be located underneath the gate (adjust drain doping and overlap region).

4) The short-channel effects should be minimized (threshold, DIBL, punchthrough, bipolar break- down, subthreshold slope, etc.).

5 ) The maximum current density should be directed away from the surface (increase depth of n- region).

6) The maximum current density should not coincide with the maximum field (adjust depth of n- region).

Further hot-electron-resistant device structures can be enhanced by following the processing guidelines as dis- cussed by Sanchez et al. [25]. Additional gains in hot- electron resistance can be obtained by employing circuit design techniques. In this approach, one attempts to re- duce the effective stress bias across the device during switching transients [26]. The tradeoff involved in em- ploying this technique is speed.

Though many of the devices reviewed have been built or simulated with channel lengths between 0.7 and 0.8 pm, it should not be construed that this is the limit for 5-V operation. Many of these devices have not been fully optimized. Furthermore, development of new devices in- corporating many of the desirable characteristics of sev- eral of these structures will allow further reductions of channel lengths. Therefore, scaling channel lengths down to 0.5 pm with minimal reductions in device performance should be feasible.

Most of the discussions on hot-electron-resistant device structures have centered on n-channel devices. However, with respect to p-channel devices some comments can be made. First, since the dominant degradation mode in p-channel devices (as in n-channel devices) occurs in the avalanche regime where ionized electrons form the gate current, the ionization rate plays an important role in de- termining the extent of the degradation. The p-channel devices traditionally have lower ionization rates than n-channel devices, due to the lower drift velocities of holes [27]. However, this advantage decreases as p-chan- ne1 devices enter the submicrometer regime. For tradi- tional stress voltages applied, drain-engineered p-channel devices will most likely be required for channel lengths below 0.9 pm. It should be mentioned that the establish- ment of a particular channel length specifying the need for drain-engineered structures depends on the process, technology, and reliability criteria required. Hence, the various effective channel lengths presented in this paper

serve only as guidelines describing the relative merits of each structure.

In terms of manufacturability, several structures can be recommended. The simplest structure to fabricate is the doubly doped drain. This structure does not require spacer technology and employs only two implants. The DDD also exhibits good drive capability. Channels down to 0.7 pm should be possible. The MLDD, BLDD, GBLDD, and AGBLDD are quite simple to fabricate; however, they do incorporate sidewall spacer technology. Devices down to 0.8 pm have been fabricated. Finally, for high perfor- mance, the DILDD should serve well in this role. Gate lengths down to 0.2 pm with a supply voltage of 3.5 V have been reported; however, this technology is not as manufacturable as the previously mentioned device struc- tures.

ACKNOWLEDGMENT The authors are greatly indebted to J. St. Vincent for

generating the illustrations in the table. Additionally, we would like to thank M. Burhans and A. Furgesson for making this work possible.

REFERENCES [ I ] S . Miller, “Ionization rates for holes and electrons in silicon,” Phys.

Rev., vol. 105, p. 1246, 1957. [2] D. Kennedy and R. O’Brien, “Avalanche breakdown characteristics

of a diffused p-n junction,” IRE Trans. Electron Devices, vol. ED-4, p. 15, 1957.

[3] E. Takeda, H. Kume, T. Toyahe, and S. Asai, “Sub-micron MOS- FET structure for minimizing channel hot-electron injection,” IEEE Trans. Electron Devices, vol. ED-26, pp. 22-23, 1979.

[4] F. Hsu, J . Hui, and K. Chiu, “Hot-electron degradation in sub-mi- cron VLSI,” in IEDM Tech. Dig. , 1985, pp. 48-51.

[5] S . Satoh and H. Abe, “Self-aligned graded-drain structure for VLSI,” Jaret, vol. 13, pp. 121-135, 1984.

[6] S . Satoh, Y. Ohbayashi, K. Mizuguchi, M. Yoneda, and H. Abe, “ Self-aligned graded-drain structure for short channel MOS transis- tor,” in Proc. VLSI Symp., 1982, pp. 38-39.

[7] H. Mikoshiba, T. Horiuchi, and K. Hamano, “Comparison of drain structures in n-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. ED-33, no. 1, pp. 140-144, 1986.

181 P. Tsang, S. Ogura, W. Walker, J . Shepard, and D. Critchlow, “Fabrication of high-performance LDDFET’s with oxide sidewall- spacer technology,” IEEE Trans. Electron Devices, vol. ED-29, pp. 590-596, 1982.

[9] S,. Ogura, P. Tsang, W . Walker, D. Critchlow, and J . Shepard, “De- sign and characteristics of the lightly doped drain-source (LDD) in- sulated gate field-effect transistor,” IEEE Trans. Electron Devices,

[IO] Y. Matsumoto, T. Higuchi, S. Sawada, S. Shinozaka, and 0. Ozawa, “Optimized and reliable LDD structure for 1 Fm NMOSFET,” in IEDM Tech. Dig., 1983, pp. 392-395.

[ l l ] S . Ogura, P. Tsang, W. Walker, D. Critchlow, and J . Shepard, “Elimination of hot-electron gate by the lightly doped drain-source structure,” in IEDM Tech. Dig. , 1981, pp. 654-656.

[12] K. Balasubramanyam et al . , “Characterization of As-P double dif- fused drain,” in IEDM Tech. Dig. , 1984, pp. 121-135.

[ 131 F. Hsu and H. Grinolds, “Structure-enhanced MOSFET degradation due to hot-electron injection,” IEEE Electron Device Lett., vol. EDL-5, pp. 71-74, 1984.

[I41 Y. Toyoshima, H. Nihira, M. Wada, and K. Kanzaki, “Mechanisms of hot electron induced degradation in LDD NMOS-FET,” in IEDM Tech. Dig., 1984, pp. 786-789.

[15] H. Katto, K. Okuyama, S . Meguro, R. Nagai, and S. Ikeda, “Hot carrier degradation modes and optimization of LDD MOSFETs,” in IEDM Tech. Dig., 1984, pp. 774-777.

vol. ED-27, pp. 1359-1367, 1980.

IEEE TRANSACTIONS ON ELECTRON DEVICES. VOL. 36. NO. 6. JUNE 1989

M. Kinugawa, M. Kakuma, S . Yokogawa, and K . Hashimoto, “sub. micron MLDD NMOSFET’s for 5V operation,” in Proc, VLSl symp., 1985, pp. 116-117. Y. Toyoshima, N. Nihara, and K. Kanzaki, “Profiled lightly doped drain (PLDD) structure for high reliable NMOS-FET’s,” in Proc, VZSlSymp., 1985, pp. 118-119. C. Codella and S . Ogura, “Halo doping effects in sub-micron

in& at Arizona State University. His general research interests are in the understanding, modeling, and measurement of small-geometry devices. Since 1987, he has also been involved in the investigation of hot-electron degradation of sihcon dioxide.

Dr. Sanchez is a member of Phi Kappa Phi and Tau Beta Pi.

* DI-LDD device design,” in IEDM tech.^ Dig., 1985, pp. 230-233. M . Nakahara et a l . , “Relief of hot-carrier constraint on submicron CMOS devices by use of a buried channel structure,” in IEDM Tech.

Y. Tsunashima et a l . , “Metal-coated lightly-doped drain (MLD) MOSFET’s for submicron VLSI’s,” in Proc. VLSI Symp., 1985, pp. 114-115. C. Wei, J . Pimbley, and Y. Nissan-Cohen, “Buried and gradedlbur- ied LDD structures for improved hot electron reliability,” IEEE Elec- tron Device Lett . , vol. EDL-7, no. 6 , pp. 380-382, 1986. H. Grinolds, M. Kinugawa, and M. Kakuma, “Reliability and per- formance of submicron LDD MOSFET’s with buried-As n impurity profiles,” in IEDM Tech. Dig . , 1985, pp. 246-249. S . Bampi and J. Plummer, “Modified LDD device structures for VLSI,” in IEDM Tech. Dig . , 1985, pp. 234-237. -, “A modified lightly doped drain structure for VLSI MOS- FET’s,” IEEE Trans. Electron Devices, vol. ED-33, pp. 1769-1779, 1986. J . Sanchez, H. Hsueh, and T . DeMassa, “Hot electron resistant de- vice processing,” IEEE Trans. Semiconductor Manufacturing, Feb. 1989. T . Sakurai, M. Kakumu, T. Iizuka, “Hot-carrier suppressed VLSI with submicron geometry,” in Proc. ISSCC, 1985, pp. 272-273. T . Kaga and Y. Sakai, “Effects of lightly doped drain structures with optimum ion dose on p-channel MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, pp. 2384-2390, 1988.

Dig., 1985, pp. 238-241.

* Julian J . Sanchez (S’81-M’86) received the B.S.E.E. degree and the B.S. degree in applied mathematics from the University of Maryland, College Park, in 1979, and the M.S. and Ph.D. degrees in electrical engineering from Arizona State University (ASU), Tempe, in 1986 and 1987. respectively.

From 1980 to 1981, he was with Motorola G.E.G., where he worked on surface acoustic wave devices. From 1981 to 1987, he attended ASU where he was involved in the research of

Kelvin K. Hsueh (S’83-M’85) was born in Tainan, Taiwan. He received the B S.E.E. degree from the Tatung Institute of Technology, Taipei, Taiwan, the M.E. degree in automatic control from Fengchia University, Taiwan, and the M S E.E. degree and the Ph D degree in electri- cal and computer engineering from Arizona State University in 1983 and 1987, respectively

He worked with Tatung CO and Tatung Tech from 1973 and 1981 after completing his compul- sory military service in Taiwan He was a Grad-

uate Research Associate of the Center for Solid-state Electronics Research, Arizona State University, from 1981 to 1987 He joined Gould Electronics/ A M.I. in 1987 where he is a Design Researcher His research interests include MOS (analog/digital) circuit design, device modeling, multidimen- sional simulation, and the physics of small-geometry MOSFET’s.

* Thomas A. DeMassa (S’60-M’66-SM’83) re- ceived the B.S.E.E. degree in 1960, the M.S.E.E. degree in 1961, the M.S. degree in physics in 1962, and the Ph.D. degree in 1966 from The University of Michigan. His Ph.D. dissertation involved microwave tube analysis and was enti- tled “Nonlinear Interaction Theory for Crossed- Field Distributed-Emission Amplifiers.”

After receiving the Ph.D. degree, he became an Assistant Professor and a member of the engi- neering facultv at Arizona State Universitv. He

Y

was promoted to Associate Professor in 1968 and full Professor in 1973. He has published numerous technical articles in the area of semiconductor device analysis and fabrication. He also authored the textbook entitled Electrical and Electronic Devices, Circuits and Instruments (West Edu- cational Publishing, 1989). His principal areas of teaching include elec- tronics, semiconductor devices, and microelectronics. He has also been a consultant and taught special courses for various companies. He has lec- tured at universities in the United States as well as abroad.

Dr. DeMassa has held several several offices of the Phoenix section of small-geometry MOSFET’s. In addition, he served as a Consultant to the CTMG division of Intel from 1983 to 1987. In 1987. he joined the Intel Corporation in Chandler, AZ. In November 1987, he became an Adjunct Faculty Member in the Department of Electrical and Computer Engineer-

the IEEE, and held all offices in the IEEE Waves and Devices Society of Phoenix. He is also a member of Tau Beta Pi, Eta Kappa Nu, and Sigma Xi. One of his proudest honors was receiving the Tau Beta Pi Outstanding Teacher Award.