dr stein introduction to microelectronics
TRANSCRIPT
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Chemical Processing for
Microelectronics
CHEE 1131
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Introduction
1. Moores Law - a predictor of transistor packing density inSilicon integrated circuits.
2. Building semiconductor devices.
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The Incredible Shrinking Transistor1947 1997
1 cm 60 nm
2007
FUTURE?
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Moores Law
Moores Law has been the economic driving force behind the
semiconductor industry for the past ~40 years. It will continue to be a driving force in the future, but for how long?
The number of transistors in an integrated circuit (e.g., Intel micro-processors)continues to increase as the size of each transistor shrinks. Check out Intels
website.
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Scaling Enabler of Moores Law*
*cf. Robert Doering, Texas Instruments
500
350
250
180
130
95 97 99 01 04 07 10 13 16
90
65
45
32
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95 97 99 01 04 07 10 13 16
FeatureSize[nm]
Year of Production
ITRS Gate Length
9
13
* For Speed, Low-Cost,
Low-Power, etc.
ITRS Lithography Half-Pitch (DRAM)
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Moores Law
My first portable computer!IBM compatibleApprox 30 lbs
128 KB; Two 5.25"
My current laptop Approx 3 lbs4 GB memory; 150 GB hard drive
Compaq Portable (1980s)
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What Are Semiconductor Devices?
Solid-state electronic components based on semiconducting
materials. Usually inorganic.
Discrete (single) devices Diodes
Transistors
light-emitting diodes (LED) lasers
Integrated devices (many devices on the same substrate) silicon integrated circuit (SIC) consists of millions of transistors,
capacitors, resistors. gallium arsenide IC
optoelectronic circuits (lasers, detectors, modulation circuitry all onsame chip)
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Semiconductor Manufacturing
1. Grow large (many kilogram) crystals
2. Slice them up into wafers (i.e. substrates) and polish them
3. Deposit layers on the polished substrate
4. Define patterns on top of the layers by photolithography(also called optical lithography, projection lithography)
5. Transfer the pattern to the film and sometimes the wafer byplasma etching.
6. Repeat steps 3-5 many times (20+)
7. Slice the wafer into devices (IC, laser, etc.)8. Package the devices (put it in a case, attach wires, etc.)
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Integrated Devices
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Environment
UH Nanofab (class 10/100 clean room).
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Class Particles per Cubic Foot
ParticleSize:
0.1m 0.2m 0.3m 0.5m
10 350 75 3 1
100 NA 750 30 101000 NA NA 300 100
Lithography Bay Plasma Etching Wet Chemistry
Reference:http://nanofab.uh.edu
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Unit Operations
Many unit operations in semiconductor fabrication
Today overview of the following steps: Silicon growth
Ion implantation (silicon doping)
Optical lithography
Plasma Etching
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c-Silicon Silicon is used in many types of semiconductor devices (FETs, etc.).
Usually single crystal is needed. Usually silicon is doped to increase the density of charge carriers (electrons, holes)
at room temperature.
Intrinsic and doped Si.
Doped Si is n-type, 1021/m3.
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Silicon Growth
1. Purification of silica sand to produce 98% pure silicon: Reduce with
carbon (coke, wood chips).
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Metallurgical grade silicon (MGS)
2( ) ( ) ( ) ( ) ( )SiC s SiO s Si s SiO g CO g+ + +
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Silicon Growth
2. Convert MGS to trichlorosilane: Pulverize Si, react with HCl in fluidized
bed:
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3 2( ) 3 ( ) ( ) ( )Si s HCl g SiHCl g H g+ +
31.8C boiling pt
Main impurities in reactant are Fe, B, P. So impurities in product are
Low bp (12.5 C)
High bp (315, 76, 160C)
* Purify trichlorosilane with distillation
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Silicon Growth
3. Convert back to solid silicon by decomposition of silane:
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3 2( ) ( ) ( ) 3 ( )SiHCl g H g Si s HCl g+ +
Electronic Grade Si (EGS)Polycrystalline! (known as Polysilicon)Purity of 99.9999999%
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Process Flow Diagram
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http://www.greenrhinoenergy.com/solar/technologies/pv_manufacturing.php
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Silicon Growth
4. Convert polysilicon to c-Si with czochralski (CZ) crystal growth.
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Fill silica crucible (SiO2) with undopedEGS
Add dopant: Pieces of doped of silicon (for
low doping concentrations); Elemental dopants (high doping
concentrations). Heat crucible in vacuum to 1420 C to
melt poly Si. Add single-crystal Si seed of known
crystal orientation. This directs the
growth of Si into a single crystal solid.
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Silicon Growth
4. Convert polysilicon to c-Si with Czochralski (CZ) crystal growth.
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After seeding, quickly draw a thinneck. This suppresses defects due tolarge temperature gradient betweenmelt and solid.
After neck forms, lower the pullingrate. Lower pulling rates give largercrystal diameters.
Crystal length depends on yieldstrength of silicon neck, crucible size.
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Silicon Growth
Common challenges: Contamination.
Silica crucible is slightly dissolved, generates oxygen. CZ-Si has around 10 ppma oxygen (partsper million atoms)
Silica crucible has impurities like B, Na, Al. These can be incorporated into the CZ-Si.
Silica crucible is not very strong. Reinforced by graphite cup. Reaction between crucible andcup generates CO, this leads to carbon contamination in CZ-Si (1016/cm3).
Time and energy consumption ($$$$$).
For 200 mm wafers, pulling time is 30 h. Heating and cooling time takes another 30 h.
Slow, high temperature, batch process.
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Ion Implantation
More common approach for building junctions (doping
silicon). Used since the 1980s. Ionized impurity atoms are accelerated through an
electrostatic field, strike the surface of the wafer. Typicalenergies of 5-200 keV.
Dose controls implant concentration (measure the ioncurrent).
Electrostatic field controls penetration depth (junction depth).
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Ion Implantation
Advantages: Low temp, good control and reproducibility,
flexible. Can use photoresist as implant mask. Disadvantages: Throughput, capital cost ($2MM each), and
damage to the semiconductor lattice.
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Ion Implantation
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1. Ion Source
2. Mass Spectrometer
3. High-Voltage Accelerator (Up to 5 MeV)
4. Scanning System
5. Target Chamber
Includes Faradaycup for dosemeasurement
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Optical Lithography
Lithography: Lithos (stone), graphos (writing)
Critical step topattern microscale or nanoscale devices.
Replicate a master pattern.
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Optical Lithography
Pattern transfer (to build a device).
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Optical Lithography
Initial template is called a mask.
Typical mask is fused silica with chromium patterns.
Quartz = UV transparent, Chrome = opaque.
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http://www.phonon.com
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Optical Lithography
Different ways to transfer the mask pattern:
1. Contact printing (press mask onto the resist-coated wafer). 1960s.Damage to the mask was a problem.
2. Proximity printing (mask near the wafer). No damage to mask, butlots of blur.
3. Projection lithography (image projected with lenses). 1970s. Nodamage, minimal blur.
Projection lithography is the current industry standard. Stepper design.
Systems have evolved to meet the demands of Moores Law.
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Optical Lithography
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Optical Lithography
Light sources: Hg lamp (80s to early 90s):
g-line: 436 nm
h-line: 405 nm
i-line: 365 nm Excimer lasers (90s to Now):
Krypton fluoride: 248 nm
Argon fluoride: 193 nm
Future?
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Decrease(historically) Increase
(recent)
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Lithography
Light sources: 157 nm was next. However, the industry could not develop
appropriate ``glass for optics and masks.
In general, when you move to shorter wavelengths you encounterproblems with transparency.
Next-generation light sources: Extreme ultraviolet: 13.5 nm. Reflection optics.
Electrons: 0.62 . Usually mask-less.
Ions: 0.12 . Usually mask-less.
Hard X-rays: < 4 nm. Masks and optics OK. Hard to develop resists.
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Projection Lithography
Resolution limit = Rmin = k1 */NA = wavelength of light source;
k1 = process parameter;
NA = numerical aperture of your optics.
For academic lithography: = g, h, and i-line. Rmin 1- 2 m.
NA < 1.
For industrial lithography:
= 193 nm. Rmin 20-40 nm.
NA 0.9-1.3.
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Tricks to Enhance Resolution
1. New optics
2. New light sources
3. New technologies
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These are techniques used in industrial manufacturing, not academic facilities.
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New Optics
193 nm light. Optics immersed in water
(n=1.33). Similar to opticalmicroscopes!
Single exposure resolves 40
nm (half-pitch). (k1 0.3) Double exposure hits 32 nm.
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Source: IBM
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New Light Source
=13.5 nm. Soft X-Rays. Called EUV. NA 0.25-0.45.
Reflective optics and masks
Vacuum operation
Single exposure, so might be
simpler than multiple patterning. Very expensive tools (ca. $80 MM)
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Decrease(historically)
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EUV Lithography: Reflective Mask
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http://www.photomask.com/products/euv-masks
40-50 alternating layers of silicon and molybdenum,Period /2.Low thermal expansion substrate.
Absorber/buffer
13.5 nm
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Academic Instrumentation
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Lithography Contact aligner (academic facility).
Broadband light (436, 405, 365 nm). Resolution limit of approximately 1-2 m.
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Reference:
http://nanofab.uh.edu
What you need: Photomask, resist and developer.
mask
substrate joystick
microscope
timer
hv
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Contact/Proximity Printing
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Reference:
http://www.cleanroom.byu.edu
Instrumentation:
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Contact/Proximity Lithography
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Reference:
http://www.cleanroom.byu.edu
Operation:
Alignment is criticalto build a multilayerdevice.
Wafer must belevel, or your imagewill look terrible.This means yoursubstrate should be
free of dust.
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Process Flow Diagram for
PhotolithographyValid for academic or industrial lithography
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Depends on resistchemistry.
HMDS = hexamethyldisilizane
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Materials Overview
Common positive-tone, negative-tone resistmaterials for academia and industry.
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Positive-Tone DQN Resist
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Positive-Tone DQN Resist
Diazo compounds are of the general structure:
Solvent removed by baking after spin-on
Matrix : PAC = 1:1
Expose to UV light (g, h, i-line). Matrix is not changed, butPAC is:
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+
== NNR
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Positive-Tone DQN Resist
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R =
Developer
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Positive-Tone DQN Resist
Developer is a basic solution (such as TMAH dissolved in
water, or KOH dissolved in water). Carboxylic acid dissolves, but un-exposed DQ does not.
Typically, you post-bake the resist to drive off volatilecompounds and make the resist better for plasma etching.
The DQN chemistry is very popular for academic lithography.For example, S1813 by MicroChem.
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Chemically-Amplified Resists
Industry standard. Invented at IBM by Willson, Ito, and Frechet.
Can be positive or negative tone. Positive tone is standard in industry.
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Chemically-Amplified Resists
Advantages: Really fast exposures. (Very sensitive to radiation.)
Tons of choices for resin and catalyst, so can be used withmany different types of radiation sources.
Disadvantages: Resolution will ultimately be limited by acid catalyst
diffusion.
Sensitivity and resolution are inversely proportional:
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Plasma Etching
Critical pattern transfer unit operation.
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Plasma Etching
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Important classifications:Isotropic vs. anisotropic
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Plasma Basics
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A partially ionized gas. Equal number of positive charges (e.g.
positive ions) and negative charges (e.g. electrons, negative ions).
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Plasma Overview
Types of processes:
Ion milling: Uses A+ (noble gas ions like Ar+) to physicallysputter material.
Ion etching: Radicals and ions react with sample. Volatileproducts.
54* Means an excited state with energy much higher than ground state
(produces radicals)
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Plasma Reactor1. Two parallel plate electrodes attached to power supply (DC or RF, DC in cartoon below).
2. Gas initially acts as an insulator.
3. Connect high-voltage source to start the plasma. Electric field in the reactor exceeds thebreakdown field of the gas. High voltage arc will flash between the two electrodes, create alarge number of ions and free electrons.
4. Electrons are accelerated toward the anode (fast), ions move to cathode (slow).
5. Ions strike the sample at the cathode, sputters and/or etches material. Volatile products.
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+
++
electron Ion
Cathode Anode
V R I
Gas breakdown by avalanche ionization
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Plasma Etching at UH Nanofab
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Nano Cougar