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Clock Distribution Networks
Yunan Xiang
Department of Electrical and Computer Engineering
University of Rochester
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Outline
Motivation Introduction
Design of clock distribution networks Summary
Future directions
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Motivation
Why clock distribution is important? Synchronous system requires high precise
clock signal across the entire chip
Clock signal has the longest interconnect,feeds the greatest fan out, operate at highest
frequency Noise and variation makes clock
distribution difficult
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Outline
MotivationMotivationMotivation
Introduction
Basic Concepts
Data Path of Clocked Registers Timing Constraints: Positive and Negative Clock Skew
Design of clock distribution networksDesign of clock distribution networksDesign of clock distribution networks
Clock skew modeling and analysisClock skew modeling and analysisClock skew modeling and analysis SummarySummarySummary
Future directionsFuture directionsFuture directions
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Basic Concepts Clock delay
Clock skew Clock jitter
Clock skew and clock jitter [1]
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Data Path of Clocked Registers [2]
Timing diagram of clocked data path [2]
TPD = TC-Q + TLogic + TInt + TSet-up
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Positive Clock Skew [2]Timing constraints:
Positive skew: longer clock period, slowerfrequency
Tskew
TCP
(TC-Q
+ TLogic(max)
+ TInt
+ TSet-up
)
[2]
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Negative Clock Skew [2]Timing constraints:
Negative skew: faster clock, race condition
|Tskew | TC-Q + TLogic(min) + Tint - THold
[2]
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Outline
MotivationMotivationMotivation
IntroductionIntroductionIntroduction
Design of clock distribution networks Design challenges
Clock distribution topologies
Low power clock distribution network design
Clock distribution for microprocessors
Clock skew modeling and analysisClock skew modeling and analysisClock skew modeling and analysis SummarySummarySummary
FutureFutureFuture direcitonsdirecitonsdirecitons
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Design Challenges
Increased clock frequency limit the budget ofclock skews
Increased clock load due to more transistors/larger
die Aggravated on-chip variations increase clockuncertainty
Process parameter variations Environmental variations
Power supply noise, Interconnect noise due to
capacitive and inductive coupling
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Clock Distribution Topologies
Tree structures Buffered tree: asymmetric
Symmetric trees: H tree, X tree
Mesh
Grid
Serpentine
Automated layout created from algorithm
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Tree Structures [2]
Common clock distribution networks [2]
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Grid and Serpentine Structures [3]
Grid structure used in DEC 21264 [3]Length matched serpentine structure used
in Intel P6 [3]
[3]
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Automated Clock Routing
Optimized algorithm example [4]Geometric matching for zero clock skew [2]
Clock trees created from automated layout algorithms
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Low Power Clock Distribution
Network Design
Clock distribution networks consumes large
portion of power: CLVDD2f
Operate the clock distribution networks at reduced
(half) power supply voltage swing Decreasing the total effective capacitance when
implement clock tree
Local conditioned clock gating
Use different frequencies for different blocks
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Clock Distribution for Microprocessors
Issues to be considered: global and localclock distribution, clock skew and jitter,transmission line effects, global clock
uncertainty, power dissipation Case study:
DEC 600 MHz Alpha [5]
Intel Itanium IA 64 [6]
Intel Pentium 4 [7]
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DEC 600 MHz Alpha Microprocessor [5]
Clock hierarchy [5]
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DEC 600 MHz Alpha Microprocessor [5]
Global clock distribution network [5]
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DEC 600 MHz Alpha Microprocessor [5]
MeasuredSimulated
global clock skew (5)
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Intel Itanium IA 64 Microprocessor [6]
Clock distribution topology (6)
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Intel Itanium IA 64 Microprocessor [6]
Global H-tree and regional blocks [6] DSK: Clusters of 4 deskew buffers
CDC: Center deskew controller
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Intel Itanium IA 64 Microprocessor [6]
Deskew buffer architecture [6]
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Intel Itanium IA 64 Microprocessor [6]
DSK variable delay circuit [6]
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Intel Itanium IA 64 Microprocessor [6]
Experimental skew measurements [6]
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Intel Pentium 4 Microprocessor [7]
High-level clock system architecture [7]
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Intel Pentium 4 Microprocessor [7]
Binary distribution tree in three clock spines [1]
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Summary
Clock distribution network presents circuit-based fundamental limitation in high-speed
digital synchronous circuits design
Great effect has been and will still be put
into modeling and designing of clock
distribution networks
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Future Directions
New approaches for global clockdistributions
Standing wave structure [11]
Resonant global clock distribution [12] [13]
Optical clock distribution [15]
Design of clock distribution network that isinsensitive to on die process variations
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References[1] Ian Young, Design of Clock Distribution in HighPerformance Processors,
http://www.mmv.vic.gov.au/web5/MDN.nsf/fll
[2] Eby G. Friedman, Clock Distribution Networks in Synchronous Digital Integrated Circuits,Proceedings of IEEE, pp.665 692, Vol. 89, No. 5, May 2001
[3] Phillip J. Restle, Alina Deutch, Designing the Best Clock Distribution Network,1998 Symposium on VLSI CircuitsDigest of Technical Papers, pp. 2-5, 1998
[4] Michael A.B. Jackson, Arvind Srinivasan,et al., Clock Routing for High-Performance ICs, 27th ACM/IEEE DesignAutomation Conference, pp. 573-579, 1990
[5] Daniel W. Bailey and Bradley J. Benschneider, Clocking design and analysis for a 600-MHz alpha microprocessor,IEEE Journal of Solid-State Circuits, Vol.3 pp1627-1633, Nov. 1998
[6] Simon Tam, Stefan Rusu, et al., Clock Generation and Distribution for the First IA-64 Microprocessor,IEEE Journalof Solid-State Circuits, pp. 1545-1552, Vol. 35, No. 11, Nov. 2000
[7] G. Geannopoulos, X. Dai, An Adaptive Digital Deskewing Circuit for Clock Distribution Networks,ISSCC 1998, pp.25.3-1-25.3-2, 1998
[8] Utpal Desai, Simon Tam, et al., Itanium Processor Clock Design,ISPD 2000, pp. 94-98, 2000
[9] Nasser A. Kurd, Javed S. Barkatullah, et al., A Multigigahertz Clock Scheme for the Pentium 4 Microprocessor,IEEEJournal of Solid-State Circuits, pp. 1647-1653, Vol. 36, No. 11, Nov. 2001
[10] Phillip J. Restle, Timothy G. McNamara, et al., A Clock Distribution Network for Microprocessors,IEEE Journal ofSolid-state Circuits, Vol. 36, No. 5, May 2001
[11] Frank OMahony, C. Patrick Yue, et al., A 10-GHz Global Clock Distribution Using Coupled Standing-WaveOscillators,IEEE Journal of Solid-State Circuits, pp. 1813-1820, Vol. 38, No. 11, Nov. 2003
[12] Steven C. Chan, Kenneth L. Shepard, Design of Resonant Glbal Clock Distributions,Proceedings of the 21thInternational Conference on Computer Design, 2003
[13] Steven C. Chan, Phillip J. Restle, et al., A 4.6 GHz Resonant Global Clock Distribution Network,ISSCC, 2004
[14] Anthony V. Mule, Elias N. Glytsis, et al., Electrical and Optical Clock Distribution Networks for GigascaleMicroprocessors,IEEE Transactions on Very Large Scale Integration (VLSI) Systems ,pp. 582-594 , Vol. 10, No. 5,Oct. 2002
http://www.mmv.vic.gov.au/web5/MDN.nsf/fllhttp://www.mmv.vic.gov.au/web5/MDN.nsf/fllhttp://www.mmv.vic.gov.au/web5/MDN.nsf/fll