1
What is needed under the hood What is needed under the hood of Nanotechnology...of Nanotechnology...
Shekhar Borkar Shekhar Borkar Intel Corp.Intel Corp.
Feb 10, 2007Feb 10, 2007
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OutlineOutline
Evolution of Electronics to CMOSEvolution of Electronics to CMOS
The three tenetsThe three tenets
Technology outlookTechnology outlook
ChallengesChallenges
Potential solutionsPotential solutions
SummarySummary
3
Evolution of ElectronicsEvolution of Electronics0
1
1850 1875 1900 1925 1950 1975 2000 2025
Mechanical
Electro-Mechanical
Electronic-VT
Bipolar
NMOS
CMOS…….���� ?
All cross-road technologies show1. Gain2. Signal/Noise3. Scalability
PerformanceEnergyPrice/Performance
4
The Three TenetsThe Three Tenets
GainInput Output
Energy
(1)
Signal/NoiseInput Output
(2)
Scalability, in some shape or form
(3)
5
ElectroElectro --Mechanical scalingMechanical scaling ——RelaysRelays
1928, Otis Elevator
6
Vacuum TubesVacuum Tubes
1930’s
1920’s
1950’s & 60’s
7
SemiconductorsSemiconductors
The first transistor
The first integrated circuit 4004 Pentium® 4
8
1.E-211.E-18
1.E-151.E-12
1.E-091.E-06
1.E-031.E+00
1940 1960 1980 2000 2020
Cub
ic M
eter
Vacuum tube
Transistor
NMOS
CMOS
Benefits of ScalingBenefits of Scaling
1.E-11
1.E-09
1.E-07
1.E-05
1.E-03
1.E-01
1.E+01
1940 1960 1980 2000 2020
Del
ay (
Sec
) Vacuum tube
Transistor
NMOS
CMOS
1.E-161.E-141.E-121.E-101.E-081.E-061.E-041.E-021.E+00
1940 1960 1980 2000 2020
Joul
es
Vacuum tube
Transistor
NMOS
CMOS
1.E-061.E-051.E-041.E-031.E-021.E-011.E+001.E+011.E+02
1940 1960 1980 2000 2020
Cos
t ($)
Vacuum tubeTransistor
NMOS
CMOS
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Technology OutlookTechnology Outlook
Medium High Very HighMedium High Very HighVariabilityVariability
Energy scaling will slow downEnergy scaling will slow down>0.5>0.5>0.5>0.5>0.35>0.35Energy/Logic Op Energy/Logic Op scalingscaling
0.5 to 1 layer per generation0.5 to 1 layer per generation88--9977--8866--77Metal LayersMetal Layers
1111111111111111RC DelayRC Delay
Reduce slowly towards 2Reduce slowly towards 2--2.52.5<3<3~3~3ILD (K)ILD (K)
Low Probability High ProbabilitLow Probability High ProbabilityyAlternate, 3G etcAlternate, 3G etc
128
1111
20162016
High Probability Low ProbabilitHigh Probability Low ProbabilityyBulk Planar Bulk Planar CMOSCMOS
Delay scaling will slow downDelay scaling will slow down>0.7>0.7~0.7~0.70.70.7Delay = CV/I Delay = CV/I scalingscaling
256643216842Integration Integration Capacity (BT)Capacity (BT)
88161622223232454565659090Technology Technology Node (nm)Node (nm)
20182018201420142012201220102010200820082006200620042004High Volume High Volume ManufacturingManufacturing
10
Si Substrate
Metal Gate
High-kTri-Gate
S
G
D
III-V
S
Carbon Nanotube FET
50 nm
35 nm
30 nm
SiGe S/D
Strained Silicon
SiGe S/D
Strained Silicon
90 nm65 nm
45 nm32 nm
20042006
20082010
2012+
Technology Generation
20 nm 10 nm
5 nm5 nm
5 nm
Nanowire
Manufacturing Development Research
CMOS Research ContinuesCMOS Research Continues ……
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CMOSCMOS——Cross Road?Cross Road?
………………
Cross Road False AlarmsCross Road False Alarms
< 1.5nm< 1.5nm
22 nm22 nm
65 nm65 nm
130 nm130 nm
0.5 0.5 µµ
1 1 µµ
??SD TunnelingSD Tunneling
EUV, Self assemblyEUV, Self assemblyLithographyLithography
HiHi--K + Metal GateK + Metal GateGate LeakageGate Leakage
Leakage control, Leakage control, avoidance, toleranceavoidance, tolerance
SD LeakageSD Leakage
More metals, Cu Low K More metals, Cu Low K ILDILD
InterconnectsInterconnects
Device EngineeringDevice EngineeringShort Channel EffectsShort Channel Effects
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WhatWhat ’’s in sight after CMOS?s in sight after CMOS?
Which technology shows gain?Which technology shows gain?
Satisfactory signal to noise ratio?Satisfactory signal to noise ratio?
• At room temperature?
Scalability in some shape or form?Scalability in some shape or form?
• Performance, Energy, Cost
Research must continue to find oneResearch must continue to find one
Then it will take 10Then it will take 10--15 years to mature15 years to mature
Until thenUntil then……
CMOS will continue…CMOS will continueCMOS will continue ……
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……But With Challenges!But With Challenges!
0
50
100
150
200
250H
eat F
lux
(W/c
m2)
Heat Flux (W/cm 2)—Vcc variation
40
50
60
70
80
90
100
110
Tem
pera
ture
(C
)
Temp Variation & Hot spots
10
100
1000
10000
1000 500 250 130 65 32
Technology Node (nm)
Mea
n N
umbe
r of
Dop
ant
Ato
ms
Random Dopant Fluctuations
0.01
0.1
1
1980 1990 2000 2010 2020
micron
10
100
1000
nm193nm193nm248nm248nm365nm365nm LithographyLithography
WavelengthWavelength
65nm65nm90nm90nm
130nm130nm
GenerationGeneration
GapGap
45nm45nm32nm32nm
13nm 13nm EUVEUV
180nm180nm
Source: Mark Bohr, Intel
Sub-wavelength Lithography
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YesterdayYesterday ’’s Freelance Layouts Freelance Layout
Vss
Vdd
OpIp
Vss
Vdd
Op
No layout restrictionsNo layout restrictionsNo layout restrictions
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Transistor Orientation RestrictionsTransistor Orientation Restrictions
Vss
Vdd
OpIp
Vss
Vdd
Op
Transistor orientation restricted to improve manufacturing control
Transistor orientation restricted to improve Transistor orientation restricted to improve manufacturing controlmanufacturing control
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Op
Vss
Vdd
Ip
Vss
Vdd
Op
Transistor Width QuantizationTransistor Width Quantization
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TodayToday ’’s Unrestricted Routings Unrestricted Routing
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Future Metal RestrictionsFuture Metal Restrictions
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ReliabilityReliability
Soft Error FIT/Chip (Logic & Mem)
0
50
100
150
180
130 90 65 45 32 22 16
Rel
ativ
e
Time dependent device degradation
0
1
1 2 3 4 5 6 7 8 9 10
Time
Ion
Rel
ativ
e
Burn-in may phase out…?
1
10
100
1000
10000
180 90 45 22
Jox
(Rel
ativ
e)Hi-K?
?
Extreme device variations
0
50
100
100 120 140 160 180 200
Vt(mV)
Rel
ativ
e
Wider
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Implications to ReliabilityImplications to ReliabilityExtreme variations (Static & Dynamic) will Extreme variations (Static & Dynamic) will result in unreliable componentsresult in unreliable components
Impossible to design reliable system as we Impossible to design reliable system as we know todayknow today
• Transient errors (Soft Errors)
• Gradual errors (Variations)
• Time dependent (Degradation)
Reliable systems with unreliable components —Resilient µµµµArchitectures
Reliable systems with unreliable components Reliable systems with unreliable components ——Resilient Resilient µµµµµµµµArchitecturesArchitectures
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Implications to Design & TestImplications to Design & Test
Design with regular fabricDesign with regular fabric
OneOne--timetime--factory testing will be outfactory testing will be out
BurnBurn--in to catch chip infantin to catch chip infant--mortality will not mortality will not be practicalbe practical
Test HW will be part of the designTest HW will be part of the design
Dynamically selfDynamically self--test, detect errors, test, detect errors, reconfigure, & adaptreconfigure, & adapt
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In a NutIn a Nut --shellshell ……
100 Billion
Transistors
100 BT integration capacity
Billions unusable (variations)
Some will fail over time
Yet, deliver high performance in the power & cost envelope
Yet, deliver high performance in the power & Yet, deliver high performance in the power & cost envelopecost envelope
Intermittent failures
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Recipe for ResiliencyRecipe for Resiliency
1.1. DetectDetect
2.2. IsolateIsolate
3.3. ConfineConfine
4.4. ReconfigureReconfigure
5.5. Recover & adaptRecover & adapt
1.1. CircuitCircuit
2.2. FirmwareFirmware
3.3. PlatformPlatform
4.4. SoftwareSoftware
5.5. ApplicationApplication
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Resiliency with ReconfigurationResiliency with Reconfiguration
Dynamic onDynamic on--chip testingchip testing
Performance profilingPerformance profiling
Spare hardwareSpare hardware
Binning strategyBinning strategy
Dynamic, fine grain, Dynamic, fine grain, performance and power performance and power managementmanagement
CoarseCoarse--grain redundancy grain redundancy checkingchecking
Dynamic error detection & Dynamic error detection & reconfiguration reconfiguration
Decommission aging HW, swap Decommission aging HW, swap with sparewith spare
Dynamically…1. Self test & detect2. Isolate errors3. Confine4. Reconfigure, and5. Adapt
DynamicallyDynamically ……1.1. Self test & detectSelf test & detect2.2. Isolate errorsIsolate errors3.3. ConfineConfine4.4. Reconfigure, andReconfigure, and5.5. AdaptAdapt
CC
CC
CC
CC
CC
CC
CC
CC
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Shifts towards the Shifts towards the NanoNano --eraera
Reliable systems with Reliable systems with unreliable componentsunreliable components
Reliable componentsReliable components
Regular design fabricRegular design fabricIrregular, freeIrregular, free--lance designlance design
Global optimizationGlobal optimizationLocal optimizationLocal optimization
Probabilistic designProbabilistic designDeterministic designDeterministic design
ToToFromFrom
Do not try to mimic CMOS with Nano-technology(Imagine trying to build Babbage’s difference engine with CMOS)
Invent a new theory of computation
Time will be just ripe then for Time will be just ripe then for NanoNano--technologytechnology
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Why Bother?Why Bother?
$1
$10
$100
$1,000
$10,000
$100,000
1960 1970 1980 1990 2000 2010
Lith
o T
ool C
ost (
$K)
G. MooreISSCC 03
Litho Cost
$1
$10
$100
$1,000
$10,000
1960 1970 1980 1990 2000 2010
Fab
Cos
t ($M
)
www.icknowledge.com
FAB Cost
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1960 1970 1980 1990 2000 2010
$/T
rans
isto
r
$ per Transistor
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1960 1970 1980 1990 2000 2010
$/M
IPs
$ per MIPS
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SummarySummary
Three tenets: Gain, Signal/Noise, ScalabilityThree tenets: Gain, Signal/Noise, Scalability
Nothing on the horizon yet that satisfies themNothing on the horizon yet that satisfies them
But research must continue to find oneBut research must continue to find one
Probably a lot different than CMOSProbably a lot different than CMOS——dondon’’t try to t try to mimic CMOS!mimic CMOS!
Several challenges lay ahead, but when have they Several challenges lay ahead, but when have they not?not?