Agenda
• Recap• 15 Years of Evolution to Virtex• Four generations of Spartan• Project discussion• Questions
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… which brings us to Spartan 3
(uh, we did skip a bunch of stuff, but the progression for our needs works out . . .)
Spartan 3
• Xilinx and the industry track silicon technology– XC2000 @1.5 micron– XC3000 @ 1 micron– XC4000 @ 0.8 to 0.35 micron– Virtex @ 0.25 micron, V-II @ 0.18-0.13 micron– Spartan 3 & Virtex 4 @ 90 nm – Virtex 5 @65 nm– Spartan 6 @ 45 nm– Virtex 6 @ 40 nm– Etc.
Spartan Philosophy
• Offer a more cost effective solution for higher volume markets
• Need to reduce costs to do that– Trim features– Reduce test cost– Sacrifice speed over die size– Cheaper packages– Etc.
• Spartan is the overall result
Projects Depend
• On your knowledge• Your skill level• Your confidence• Your interest• Uh . . .I don’t know any of the above points about
you!• Only YOU know where you are at on this continuum• My goal is to get you to where you can design on
Xilinx FPGAs, which has a LOT to do with the S/W!
Some Ideas
• Interfaces – MIX & MATCH things
• Buses and memories• Peripherals & memories• Buses & peripherals• Processors & the above
• Systems– Build single function
items– Combine two or more
items– Invent something new
Ahh, the Good Old Days . . .
Basic idea: Create useful, correct standard functions then . . . HOOK ‘EM UP!
Possible Projects
• The Light bulb area has design templates for both VHDL and Verilog
• I’d like to expand the documentation on them along the lines of the TTL Catalog, and Doug Smith’s book.
• Need volunteers to take say 10 of the templates, instantiate into a design, capture the schematic (automatic) and simulate to verify the operation
Possible Project Continued
• The Deliverable would be a WORD file organized to have: – Template code– Graphic– Simulation
• I can make these available to the rest of the class and to future classes
Another Idea
• The Digilent NEXYS2 board is supported by VHDL solutions, which are available.
• Most of them are 1-2 sheets of code.• I’d like to get them in Verilog, with simulations
and compiled onto Xilinx Spartan 3 parts.• Take a look at the “pmod” code chunks