Download - VIIT-GRAPES Collaboration C S Garde Vishwakarma Institute of Information Technology (VIIT), Pune
VIIT-GRAPES Collaboration
C S GardeVishwakarma Institute of Information Technology (VIIT),
Pune
VIIT-TIFR collaboration
Year No. of projects No. of BE students
No. of faculty (VIIT)
No. of scientists/ engineers
(TIFR)
Departments (VIIT)
2009-2010 1 2 2 1 E&TC
2010-2011 8 19 7 8 E&TC
2011-2012 11 33 9 15 E& TC, Computer Engg.
2012-2013 13 38 12 10 E& TC, Computer Engg., IT
2013-2014 17 47 12 10 E& TC, Computer Engg., IT
VIIT students in TIFR
Sr. No. Name of student (Batch) Project at TIFR Post Lab at TIFR
1 Sanket Kamathe (2010) Silicon Photo Multiplier (SiPM)
Jr. Research FellowSolid State Electronics, Mumbai2 Ameya Deshpande (2010) Tera Hertz Spectroscopy Jr. Research Fellow
3 Raj Patil (2011) Plasmonics NRIM National Photonics Fellowship
4 Aniket Patil (2011) Plasmonic Interconnects National Photonics Fellowship
5 Harshad Surdi (2012) Tera Hertz Spectroscopy Jr. Research Fellow
6 Raghunandan Shukla (2011) SiPM, VLSI, Embedded High Energy Physics, Mumbai7 Sarrah Lokahandwala (2013) FPGA based systems, SiPM Jr. Research Fellow
8 Suraj Kolhe (2012) VLSI, Embedded Jr. Research Fellow Cosmic Rays Laboratory, Ooty9 Serin V. John (2013) High voltage DAS, Embedded Jr. Research Fellow
Software Projects
Sr. No.
1 Data management for Muon Detector Station
2 Data Management for Scintillator Detector system
3 Parallelization of Corsika
4 Parallelization of G3SIM (C++ programme)
5 Dynamic ROOT plotting
Hardware Projects
Sr. No.
Project
1 32-channel FPGA based counter with USB interface
2 64-channel FPGA based counter with ethernet interface
3 FPGA based I2C communication
4 High voltage Data acquisition system
5 Solar PV
6 High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier
32 Channel FPGA Based Counter
•Last year:•32 channel 24 bit high-speed counter implemented on a Actel FPGA (counter and digital logic part)•FPGA and PIC micro-controller interfacing done•Data logging to PC by a PIC micro-controller via USB protocol (Linux compatible)
32 Channel FPGA Based Counter
• This year:• FPGA programming – VHDL to Verilog conversion is in
progress (small Verilog programs (counter, etc.) implemented and tested on hardware)•Pulse width measurement logic under development•New counter logic development in Verilog is in
progress
64 Channel FPGA Based Counter (Scalar)• Last year:
• Simulations of 32 bit 64 channel counter• 4 channel 16 bit Counter (Scalar) implementation on SPARTAN3E
FPGA using VHDL• Data transfer to PC through ARM7 controller, via Ethernet protocol
(UDP/IP) demonstrated• Multi-board configuration (IP Address based) with 2 ARM boards• Multi-threading approach demonstrated for data reception on PC
64 Channel FPGA Based Counter (Scalar)• This year:• FPGA programming – VHDL to Verilog conversion is in progress• 4 channel 4 bit counter demonstrated SPARTAN3E FPGA in Verilog • Automated approach to toggle between 64 channels is demonstrated• Multi-board configuration: synchronization of boards with I2C protocol
demonstrated for 2 ARM Boards• Time stamping with milliseconds accuracy is demonstrated• Pulse width measurement logic under development• Ethernet part : Data transfer with TCP/IP protocol is under development
High Voltage Data Acquisition System• Last year:
•48 channels system for PMT voltage monitoring developed •1 V resolution in 2500 V• This system tested on actual PMT setup at CRL, Ooty•Data logging via USB every 5 sec
Block diagram
High voltage monitoring
High Voltage Data Acquisition System• This year:
•Different protection Circuits for already developed high voltage data acquisition board being developed and tested• Temperature, Humidity etc. sensors being tested for
inclusion in high voltage data acquisition board
Design and Implementation of Multiple Panels Solar Power System• Last year:
•Maximum Power Point Tracking (MPPT) based charger developed for 25W solar panel•Data logging system (Voltage, Current, Power) for a
single solar panel developed (via USB protocol)
Design and Implementation of Multiple Panels Solar Power System• This year:
• Improvement on MPPT charger circuit• Inclusion of Buck-Boost converter for high efficiency•Multiple Solar Panel Configuration with Data logging•Different Protection Circuits inclusion• Temperature Sensing
Design and Implementation of Multiple Panels Solar Power System• This year:-• Design of solar power system for 1kW of power with 4 solar panels and 8 batteries.• Design of a Buck Boost Converter.• Design of a Isolated Boost Converter.• To design a Load Sharing System.
• Specifications of PV Panels :-• Voc for each panel = 42V• Isc for each panel = 7.6A• Vmpp for each panel= 35.25V• Impp for each panel=7.4A
I2C based multiple FPGA Configuration• Started from this year•Counter based projects uses FPGA, so in future a
multiple FPGA configuration will be needed•Multiple FPGA’s (slaves) will communicate to PIC
based microcontroller (master) via I2C protocol•PIC micro-controller to PC communication via USB is
developed previously and used for various projects
High Precision Temperature Compensated Power Supply For Silicon Photo-Multiplier
Silicon Photo-Multiplier (SiPM)• Multi-pixel semiconductor Avalanchephotodiode.
• A Solid State Device
• Operating voltage (30-120V)
• Resolution - Single photon detection
• Response time – ~1 ns
• High gain -
• High Quantum Efficiency – 90%
• High Photon Detection Efficiency – 60%
FIIG, University of Pisa, Italy
SiPM Biasing
Specifications of Power SupplyParameters Value
Maximum Output Voltage 100 V
Output Voltage Resolution 25 mV
Output Channels 16
Maximum Current Limit (Per Channel) 100 uA
Typical SiPM Temperature Compensation Coeff. 50 mV/˚C
Temperature Detection Resolution 0.1 ˚C
* Also, total power supply unit should be as small as possible.
Temperature Compensation Test• First Passive Compensation is done for
proof of principle
• SiPM typical temperature coeff. = 50 mV/˚C
• LM 35 temp. Coeff. = 10 mV/˚C
• A Circuit is connected to SiPM supply directly, that will change the supply voltage ground according to temperature
SiPM
Test Setup for Compensation test
SiPM Power Supply
Compensation Circuit
SiPM VMETest Setup
PCData logger for Temperature measurement
Blower(Heat)
Results of Compensation Required Compensation is a non-linear Function
27 28 29 30 31 32 330
5
10
15
20
25
30
Temperature Compensation Test
without compensation
with compensation
Temperature (˚C)
Gai
n
Block Diagram for Proposed Power Supply High Voltage
Generation (Voltage Multiplier
Chain)
Control Unit (Micro-controller)
Temperature Sensors
Voltage Regulation Scheme
PC
USB
SiPMCurrent Sense
DAC
Test Board
Tests Performed
•DAC Stability• Line Regulation• Load Regulation• Linearity• Time Drift •Capacitor for Noise elimination at output and stability
DAC Stability5.102 uV variation in 5 V
Line Regulation 0.04113% for 10% change in line voltage0.03% for 20% change in line voltage
Load RegulationNo load to Full load (100uA)Best 0.6025% Channel 2Worst 1.55% Channel 8
Linearity
0 10 20 30 40 50 60 70 80 90 1000
20
40
60
80
100
120Linearity of 8 channels
Channel 1Channel 2Channel 3Channel 4Channel 5Channel 6Channel 7Channel 8
Set Voltage (V)
Regu
lato
r Out
put (
V)
Time Drift (Channel 1)
SupplyVoltage
RegulatorOutput
Time Drift Error Plots
600 mVp-p change 100 mV change
Supply Voltage Error Plot Regulator Output Error Plot
Ceramic Capacitor for reducing ripple
• Where • Iout = 100 uA, dc = 0.98• fsw = 19.52 (in KHz), Vp = 1 mV
• Cmin = 0.0995 uf
• C1 = 0.1 uf , C2 = 0.01 uf
Time Drift (Improved) with 0.1 f Capacitor
Without Capacitor
With 0.1 uf Cap
15 mV Change
Channel 1
Histograms
Comparison Between 0.1f and 0.01f
Histograms
Voltage Generation (Voltage Multiplier)
•A simple 10-stage Voltage multiplier chain is build with diodes (1N4148) and capacitors (0.22 F)
• The chain is tested for input frequencies 50 Hz to 5 MHz and for sine and square inputs.
Chain testing
10 100 1000 10000 100000 1000000 100000000
10
20
30
40
50
60
70
80
90
100
Multiplier Chain Test
With Square wave input
with Sine wave input
Frequency (Hz)
Out
put V
olta
ge (V
)
Specifications achieved on test board
Parameters Required Value Achieved Value
Maximum Output Voltage 100 V 88.5 V with chain
Output Voltage Resolution 25 mV 50 mV
Output Channels 16 8
Maximum Current Limit (Per Channel) 100 uA 100 uA
Typical SiPM Temperature Compensation Coeff.
50 mV/˚C
Temperature Resolution 0.1 ˚C
A stability of 10 mV in 50 mV resolution is achieved
Conclusions
• Software project: Except Parallelization of CORSIKA all other software projects have been partially
implemented and are being fine tuned• Hardware projects:1. Standard PIC micro-controller based USB has been standardized2. ARM7 based Ethernet - UDP implemented, TCP in advanced stage3. FPGA – VHDL to Verilog transition made, 32 channel counter in advanced stage,
64 channel also in good shape, I2C in initial stage4. High Voltage Monitoring – Advanced stage5. Solar PV – R&D on Multiple panel, high power system optimization6. SiPM power supply – In advanced stage
Guides from VIIT
• C S Garde - Coordinator• V M Aranake• M S Karyakarte• S J Thaware• K J Raut• Mrs S Y Desai
Guides from TIFR
• S K Gupta - Coordinator• S R Dugad• Atul Jain• Jagdeesan• Mohanty• Hariharan• Raghunandan• Sarah• Serin• Suraj
Students (Computer)
1. Mustafa Adib 2. Modak Ameya3. Marathe Amogh4. Rachit Kulshrestha5. Shushupti Ajmire6. Tejasvi Belsare7. Dhawal Priyadarshi8. Ms Devanshi Shah9. Shubham Gupta10. Irom Ajay Singh11. Kishan Rao12. Tejas Rao
Students (IT)
1. Qaidjohar Jawadwala2. Harsh Kundnani3. Dyaneshwar Kothule4. Ms Shivangi Hiray5. Ms Rekha Sangwan6. Runa Ganeshan7. Ayushi Tripathi8. Ankit Bhavsar9. Nikhil Mantri
Students (Electronics)
1. Aditya Godbole, Veronica D’Souza, Saumitra Kale2. Akshay Manjare, Digvijay Tambhale, Shefali Rai3. Afshan Shaikh, Akhil Kurup, Syed Shadab4. Kamlesh Shinde, Bhagyashree Kalaskar, S Venkatesh 5. Ravi Prakash, Vinit Shah, Sanket Dahiwal 6. Jaydeep Kshirsagar, Kushal Kshirsagar 7. Pankaj Rakshe (ME)
Thank you
Work Plan
Tasks Duration
Sophisticated Voltage Multiplier Chain Building November 2013
Temperature Compensation Algorithm implementation in micro-controller
November 2013
Current Sensing Implementation November 2013
Testing with Actual SiPM Setup December 2013
All modules-on-one-board PCB design December 2013
New Board testing and data analysis January 2014
References
[1] K.C. Ravindran, “Silicon Photo-multiplier development at GRAPES- 3”, WAPP workshop, CRL, Ooty.
[2] Bajarang Sutar, “A talk on study of characteristics of SiPM”, TIFR, Mumbai.
[3] R. Bencardino, J.E. Eberhardt, “Development of a Fast-Neutron Detector With Silicon Photomultiplier Readout”, IEEE Trans. On Nuclear Science, 2009
ERP system for Muon Detector Stations
Problem Statement
• Manufacturing of muon detector stations.• Lack of integrated solutions• Collaboration between departments• Analysis and performance checking• Inventory Management• Ease of retrieval in data
• Management of manufacturing process and employees
Objectives
To maintain and manage the data from production to construction stage of muon detector station
To generate various reports
To perform the analysis based on failure rate of component ,user performance etc.
Enhancing the operational efficiency of business resources.
What we have done until now ?
• Requirement Gathering• Literature Survey• Study about ERP system• ER diagram• Schema Diagram• Proposed System• Features• Users and their roles
Literature Survey Software package that integrates all necessary business functions into a
single system
Features of ERP system-Componentized, Integrated, Flexible
ERP follows three-tier architecture
• Application Layer• Presentation Layer• Database Layer
Literature Survey(Continued…)
• Functionalities Of ERP system• Financial Management• Human Resource Management• Manufacturing Management• Product Lifecycle Management• Inventory Management• Security
Literature Survey(Continued…)