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Agenda
INTRODUCTIONELEMENTS OF VHDL
LANGUAGE ELEMENTS
CONCURRENT STATEMENTS
SEQUENTIAL STATEMENTS
SIGNALS & VARIABLES
GENERICS
MULTIVALUED LOGIC SYSTEM
OPERATOR OVERLOADING
PACKAGES
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Introduction
WHAT IS VHDL?
FEATURES OF VHDL
HISTORY OF VHDL
LEVELS OF ABSTRACTION
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What is VHDL?
VHDL stands for
Very High Speed Integrated Circuits Hardware
Description Language.
It is a Hardware description Language
Digital system design using HDLs is an established methodology in
EDA ( Electronic Design Automation).
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Features of VHDL
VHDL is the amalgamation of following languages:
Concurrent Language
Sequential Language
Timing Specification
Simulation Language
Test Language
Design Hierarchies to create Modular designs
Facilitates device independent design and Portability
It has all the features that
real life hardware has
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Concurrent Language
Concurrent Statements execute at the same time in parallel, as inHardware.
Z
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Sequential Language
Sequential Statements execute one at a time in sequence.As the case with any conventional language
Sequence of statements is important.
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Timing Specification
clock waveform
process
beginclock
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Test Language
Test bench- Is part of a VHDL model that generates a set of test vectors and
sends them to the Module being tested.
- Collects the responses made by the Module Under Test and
compares them against a specification of correct results.
Need
To ensure that design is correct.
Model is operating as required.
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Design Hierarchy
Hierarchy can be represented using VHDL.
Consider example of a Full-adder which is the top-level module,
being composed of three lower level modules i.e. Half-Adder and
OR gate.
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History of VHDL
In 1981 the Institute for Defense Analysis (IDA) had arranged aworkshop to study
Various Hardware Description methods
Need for a standard language
Features required by such a standard.
A team of three companies, IBM, Texas Instruments, and Intermetricswere awarded contract by DoD to develop a language.
Version 7.2 of VHDL was released along with Language Reference
Manual (LRM) in 1985.
Standardized by IEEE in 1987 known as the IEEE Std 1076-1987.
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DETAIL
ABSTRACTION =DETAIL
1
OR
ABSTRACTION =
Abstraction
THEREFORE Highest Level of abstraction means Lowest Level Ofdetail.
DETAILS OF WHAT ??Finally we want to make a Chip,Hence Levels of Abstraction Tell us as too how close is our descriptionto What is required to make a chip.
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Levels of Abstraction
Different styles are adopted for writing VHDL code.
Abstraction defines how much detail about the design is specified in
a particular description.
There are four main levels of Abstraction.
Layout Level
Logic level
Register Transfer Level
Behavioral Level
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Layout Level
Lowest level of Abstraction.
Specifies
Actual layout of design on
Silicon
Contains
Detailed timing information,
and analog effects.
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Logic Level
Design has information about
Function
Architecture
Technology
Detailed timings
Layout information and analog
effects are ignored.
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Register Transfer Level
Using HDLs every register in
the design, and the logic in
between is defined
Design contains Architecture information
No details of Technology
No specification of
absolute timing delays.
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Register Transfer Level
Entire Design is partitioned between clocked and combinationalprocesses. E.g. up down / synchronous counter
Comblogic
ComblogicFLIP
FLOP
FLIP
FLOP
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Behavioral Level
Describing function of a designusing HDLs, without specifying
the architecture of registers.
Contains timing information
required to represent a function.
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Behavioral Level
Behavioral Model of an AND gate.
architecture and_gate_arch of and_gate is
begin
process(a,b)
begin
if (a = '1' and b = '1') then
c
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Entity
Equivalent to pin configuration of an IC.
Syntax:
entity entity_name is
port (port_list) ;
end entity_name;
Example :
entity and_gate is
port ( 1A, 2A, 3A, 4A : in std_logic;1B, 2B, 3B, 4B : in std_logic;
1Y, 2Y, 3Y, 4Y : out std_logic
) ;
end and_gate ;
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Entity
VHDL design description must include, ONLY ONE ENTITY
Entity Declaration
Defines the input and output ports of the design.
Each port in the port list must be given,
a name
data flow direction
a type.
Can be used as a component in other entities after being compiledinto a library.
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Entity
Proper documentation of the ports in an entity is very important.
A specified port should have a self explanatory name that provides
information about its function.
Ports should be well documented with comments at the end of the
line providing additional information about the signal.
Consider example of an ALU.
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Entity
entity ALU isport (
In1 : in std_logic_vector (3 downto 0); -- first operand
In2 : in std_logic_vector (3 downto 0); -- second operand
Opsel : in std_logic_vector (3 downto 0); -- operation select
Cin : in std_logic; -- carry in
Mode : in std_logic; -- mode arithm/logic
Result : out std_logic_vector (3 downto 0); -- operation result
Cout : out std_logic; -- carry out
Equal : out std_logic ); -- Is 1 when In1 = In2end ALU;
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Modes
Signal in the port has a Mode which indicates the driver direction.
Mode also indicates whether or not the port can be read from within
the entity.
Four types of Modes are used in VHDL.
Mode IN
Mode OUT
Mode INOUT
Mode BUFFER
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Mode IN
Value can be read but not assigned.
Example:
entity driver isport ( A : in std_logic;
) ;
end driver ;
Drivers reside
outside the entity
Port Signal Entity
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Mode OUT
Value can be assigned but not read.
Example:
entity driver is
port ( B : out std_logic;
) ;
end driver ;
Entity
Drivers resideinside the entity
Port Signal
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Mode INOUT
Bi-directionalValue can be read and
assigned
Example:
entity driver is
port (Data : inout std_logic) ;
end driver;
Entity
Drivers may reside both
inside and outside the entity
Port signal
Signal can be
read insidethe entity.
Data
Always need a control signal to control direction of signal flow.
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Mode BUFFER
Output port with Internal read
capability
Example:
entity driver is
port (Count : buffer std_logic ) ;
end driver ;
Count
Entity
Driver reside
Inside the entity
Signal inside can beread inside the entity
Note does not exists in real life hardware but are included for
convenience.
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Architecture
Specifies,
Behavior
Function
Relationship between inputs and outputs of an entity.
Syntax:
architecture architecture_name ofentity_name is
declarations
beginconcurrent_statements
end [ architecture_name ];
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Architecture
Equivalent to truth table.
Example:
A B C
L L L
L H L
H L L
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Architecture
Can contain only Concurrent Statements.
A design can be described in an Architecture using various Levels
of Abstraction.
To facilitate faster design
Better understanding
Lesser complexity.
AN ENTITY CAN HAVE MORE THAN ONE ARCHITECTURE!!
There can be no architecture without an Entity.
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Architecture Bodies
Behavioral
Also known as High-level
Descriptions.
Consists of a set of
assignment statements to
represent behavior.
No need to focus on thegate-level implementation
of a design.
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Architecture Bodies
Dataflow
Use concurrent signal assignment statements.
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Architecture Bodies
Structural
Components from libraries are
connected together.
Designs are hierarchical.
Each component can be
individually simulated.
Consists of VHDL netlists.
It is possible to mix the three Modeling styles in a single
architecture body.
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Comparing Architectural Bodies
A structural design methodology is used to
Split a design into manageable units.
Silicon vendors provide libraries which can be used to instantiatecomponents that represent device-specific resources and
optimized structures.
eg. LogiBLOX in Xilinx Tool.
Synthesis tools have in-built algorithms that find the optimal
solution regardless of the form of description.
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Configuration
NEED:
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Configuration declaration is used to select one of the many
architectures that an entity may have.
Syntax:
Configuration
configuration configuration_name of entity_name is
for architecture_name
for instantiation:component_name
use library_name.entity_name(architecture_name);
end for;
end for;
end configuration_name;
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Configuration
entity gates is
port (a,b : in STD_LOGIC;
c: out STD_LOGIC );
end gates;
architecture and2_arch of gates isbegin
c
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Language Elements
VHDL is a strongly TYPED Language.
VHDL is not case sensitive.
VHDL supports a variety of data types and operators.
OBJECTS
OPERATORS
AGGREGATES
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OBJECTS
Objects are used to represent & store the data in the system being
described in VHDL.
Object contains a value of a specific type. For ex:
object
SIGNAL COUNT : INTEGER
class Data type
The name given to object (also port ) is called as identifier.
RESERVED WORDS cannot be used as identifiesEach object has a type & class.
Class indicates how the object is used in the model & what can bedone with the object.
Type indicates what type of data the object contains.
results in an object calledcount which holds integer value
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OBJECTS
Each object belong to one of the following
CLASS
CONSTANT SIGNAL VARIABLE
The set of values that each object can hold is specified byDATA TYPES
SCALAR ACCESS FILE COMPOSITE
Integer Real Enumerated Physical Array
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CONSTANTS
These are identifiers with fixed value.
The value is assigned only once, when declared.
Value cannot be changed during simulation.
Example:
constant Bus_Width : Integer := 16;
constant CLK_Period : Time := 15 ns;
Constants makes the design description more readable.
Design changes at later time becomes easy.
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Scalar data types Enumerated
This declaration defines a set of user-defined values consisting of
identifiers & character literals.
User defined enumeration
type micro_op is ( load, store, add, sub, mul, div )
As shown micro_op is enumerated types & supports the values load,
store, add & sub. Values of enumeration type has position number associated with them.
Compiler encodes these enumeration literals in ascending order.
Predefined enumeration types :
Bit :Supports the values 0 & 1.
Boolean : Supports literals FALSE & TRUE is defined as
variable error_flag : boolean := true.
Std_logic_type : Data type defined in the std_logic_1164 package of
IEEE library. It is defined as
type std_logic is (U, X, 0, 1, Z, W, L, H);
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SCALAR DATA TYPES
OBJECTS OF PHYSICAL TYPE ARE NOT SYNTHESISABLE ??
Data type Meaning Example
Integer Has set of values that
follow within specific range
signal count : integer range 0
to 8
Real Has a set of values ingiven range of real
numbers.
signal real_data : real range0.0 to 35.5
Physical Used to represent physical
quantities such as current,
time distance
Constant set_up : time := 2 ns.
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COMPOSITE DATA TYPES
Composite Data Types represents collection of values.
ARRAY - : Consists of the elements that have same type.
Vector ( special case of single dimensional array )
Ex signal A : std_logic_vector (7 downto 0);
Two dimensional array (typical application is a memory device)
Ex : type memory_1K4 is array ( 0 to 1023 ) of std_logic_vector
( 3 downto 0);
signal memory : memory_1K4
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Operators
Logical Operators Lowest priority (except not) ??
Relational Operators
Shift Operators
Adding Operators
Multiplying Operators
Miscellaneous Operators Highest priority
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Logical Operators
Are defined for
Types BIT and BOOLEAN.
One dimensional arrays of BIT and BOOLEAN.
AND OR NAND NOR XOR XNOR NOT
Incorrect Examples:port ( a, b, c : bit_vector (3 downto 0);
d, e, f, g : bit_vector (1 downto 0);h, i, j, k : bit;l, m, n, o, p : boolean );
h
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Relational ( Conditional ) Operators
Are used to check conditions.
= and /= are predefined for all types.= are predefined for
For integer types
Enumerated types
One-dimensional arrays of enumeration and integer types.
= /= < > =
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Relational Operators
No numerical meaning is associated with a BIT vectorElements of a vector are just a collection of objects of the same
type.
For array types operands are aligned to the left and compared to
the right.
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Shift Operators VHDL 93
sll Shift left logical
srl Shift right logicalsla Shift left arithmetic
sra Shift right arithmetic
rol Rotate left logical
ror Rotate right logical
sll srl sla sra ror rol
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Shift Operators
Each operatorTakes an array of BIT or BOOLEAN as the left operand
Integer value as the right operand
Ex: A is a bit_vector equal to 10010101
A sll 2 is 01010100 (shift left logical, filled with 0)
A srl 3 is 00010010 (shift right logical, filled with 0)
A sla 3 is 10101111 (shift left arithmetic, filled with right bit )
A sra 2 is 11100101 (shift right arithmetic, filled with left bit )
A rol 3 is 10101100 (rotate left)A ror 2 is 01100101 (rotate right)
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Adding Operators
Concatenation Operator (&)
Operands can be one-dimensional array type or element type
& Operator works on vectors only.
Example:
signal a: std_logic_vector ( 5 downto 0 );
signal b,c,d: std_logic_vector ( 2 downto 0 );
beginb
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Adding Operators
Do not use Concatenation operator on the left of the assignmentsymbol.
architecture bad of ex is
signal a : std_logic_vector ( 2 downto 0 );
signal b : std_logic_vector ( 3 downto 0 );
begin
0 & a
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Multiplying Operators
( * ) and ( / ) are predefined for: Integers, Floating point numbers
mod ( modulus ) and rem ( remainder ) are predefined for Integersonly.
* / mod rem
Example:
variable A,B : Integer;
Variable C : Real;
C
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Miscellaneous Operators
The abs operator has only one operand. It allows defining the
operands absolute value. The result is of the same type as the
operand.
** ( Exponential Operator ) is defined for any integer or floating point
number
Abs **
Examples :
2 ** 8 = 256
3.8 ** 3 = 54.872
abs (-1) = 1
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Aggregates
Assigns values to the elements of an array.
Example :
a 0; ) identical to a 1, others =>0 );
signal data_bus : std_logic_vector ( 15 downto 0 );
data_bus '0', others => '1 );
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Aggregates
Elements in a vector can also be assigned values of other signals.
Example : a has a length of 5 bits.
a c(2), 3=> c(1), others => d(0);
identical to
a
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Concurrent Statements
MEANING IN HARDWARE TERMS
CONCURRENT CONSTRUCTS
WHEN_ELSE STATEMENT
WITH_SELECT STATEMENT
COMPONENT INSTANTIATION
USE OF GENERATE STATEMENT
CONCURRENT STATEMENT CHARACTERISTICS
C t St t t
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Concurrent Statements
ConsiderX = X+Y;
In software:
X and Y are register
locations
The contents of X and Y
are added and the result is
stored in X.
C t St t t
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Concurrent Statements
In concurrent statements,there are no implied registers.
Feedback is described around
Combinational logic.
S l t d Si l A i t h t t t
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Selected Signal Assignmentwhen statement
Z
>
>
z
S l t d Si l A i t h t t t
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Selected Signal Assignmentwhen statement
Z A
z
x
??
S l t d Si l A i t h t t t
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Selected Signal Assignmentwhen statement
Z A
z
x
0
1
y
B
C
>
>
S l t d Si l A i t h t t t
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Selected Signal Assignmentwhen statement
Modeling Tri-state buffer
architecture tri_ex_a of tri_ex is
begin
out1
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Syntax
with...select statement evaluates choice_expression and compares
that value to each choice value.
In when statement the matching choice value has its expression
assigned to target.
Each value in the range of the choice_expression type must be
covered by one choice.
Selected Signal Assignmentwith statement
with choice_expression selecttarget
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Selected Signal Assignmentwith statement
signal A, B, C, D, Z: std_logic;
signal CONTROL:std_logic_vector (1 downto 0);
with CONTROL select
Z
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Selected Signal Assignmentwith statement
Modeling multiplexer
architecture with_ex_a of with_ex is
begin
with in1 select
out1
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Design Hierarchy
Hierarchy can be implemented using VHDL. Predefined design can be
used to model complex functionality.
Full adder can be implemented using two half adders as shown below
A S
U1
B C
A S
U2
B C
IN1
IN2
IN3
sum
carry
Top level
Component
Design Hierarchy
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Design Hierarchy
entity half is
port ( A,B : in BIT;S1,Carry : out BIT);
end half;
architecture add_arch of half is
component xor
port ( A,B : in BIT;
C : out BIT);
end component;
component nd2
port ( A,B : in BIT;
C : out BIT);
end componentsignal s1,c1, c2 : BIT;
begin
U1: xor port map (A => a, B =>b, S => S1);
U2: ND2 port map ( A =>a, B =>b, C=>carry);
Component Instantiation
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Component Instantiation
Component
Represents a precompiled Entity- Architecture pair.
Instantiation
Is selecting a compiled specification in the library and linking it
with the architecture where it will be used.
Port mapping
Assignment ofactual signals in the system to the formal ports of
the component declaration.
Component Instantiation
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Syntax:
instance_name names this instance of the component type by
component_name - WHY?port map connects each port of this instance of component_name to a
signal-valued expression in the current entity.
Component Instantiation
instance_name : component_name
port map (
[ port_name => ] expression
[port_name => ] expression );
Component Instantiation
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Component Instantiation
entity ND4 IS
port ( IN1,IN2,IN3,IN4 : in BIT;Z : out BIT);
end ND4;
architecture gate_arch of ND4 is
component ND2port ( A, B: in BIT;
C : out BIT);
end component;
signal TEMP_1,TEMP_2 : BIT;
begin
U1: ND2 port map ( A =>IN1, B =>IN2, C=>TEMP1 );
U2: ND2 port map ( A =>IN3, B =>IN4, C=>TEMP2 );
U3: ND2 port map ( A =>TEMP1, B =>TEMP2, C=>Z );
Component Instantiation
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Component Instantiation
Ports can be mapped to signals by Positional or mixed notation.
U1: ND2 port map ( IN1,IN2, TEMP_1 ); -- positional
U2: ND2 port map (A => X, C => Z, B => Y); -- Named
U3: ND2 port map (IN1,IN2, C => TEMP1); -- Mixed
Named association is preferred because it makes the code more
readable and pins can be specified in any order.
All positional connections should be placed before any namedconnections.
Generate Statement
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Generate Statement
Concurrent statements can be conditionally selected or replicated
using generate statement.
Used to create multiple copies of components, processes, or blocks.
For ex: Provides a compact description of regular structuressuch as memories, registers, and counters.
No simulation semantics are associated.
Generate Statement
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Generate Statement
Two forms of generate statement
Note: Range must be a computable integer, in either of these forms:
integer_expression to integer_expression
integer_expression downto integer_expression
Each integer_expression evaluates to an integer.
forgenerate
Number of copies is determined
by a discrete range
Syntax:label: foridentifierinrangegenerate
{ concurrent_statement }
end generate [ label] ;
ifgenerate
Zero or one copy is made,
conditionally
Syntax:label: ifexpressiongenerate
{ concurrent_statement }
end generate [ label];
Generate Statement
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Generate Statement
for.generate
Example:
Generate Statement
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Generate Statement
Example:
Generate Statement
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Generate Statement
ifgenerate
Example:
Generate Statement
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Generate Statement
Example:
Drivers
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Drivers
Are created by signal assignment statements
Concurrent signal assignment produces one driver for each signal
assignment
Drivers
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Drivers
As shown Z is assigned two times. Hence has multiple drives
Drivers
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Drivers
Signals with multiple sources can be found in numerousapplications.
Ex. : Computer data bus may receive data from the processor,memory, disks, and I/o devices.
Each of the above devices drives the bus and each bus signalline may have multiple drivers.
Such multiple source signals require a method for determining theresulting value when several sources are concurrently feeding thesame signal line.
When defining a synthesizable design do not initialize ports orsignals.
Resolution Function
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Resolution Function
VHDL uses a Resolution Function to determine the actual output.
For a multiple driven signal, values of all drivers are resolved together
to create a single value for the signal.
This is known as Resolution Function
Examines the values of all of the drivers and returns a single
value called the resolved value of the signal.
Std_Logic and Std_Logic_Vector are resolved Functions. The de facto industrial standard types.
Resolution Function
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Bad Model
ENTITY mux ISPORT (i0, i1, i2, i3, a, b : INstd_logic;
q : OUT std_logic);
END mux;
ARCHITECTURE bad OF mux
ISBEGIN
q
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SEQUENTIAL STATEMENTS
HOW DOES PROCESS WORK?
SEQUENTIAL CONSTRUCTS
IF STATEMENT
CASE STATEMENT
TYPES OF PROCESSES
HARDWARE MODELING EXAMPLES
SEQUENTIAL STATEMENTS CHARACTERISTICS
WAIT STATEMENT
LOOP STATEMENTS
Process Statement characteristics
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Process Statement characteristics
Are executed one after another, in the order in which they are written.Can appear only in a Process.
Only sequential statements can use Variables.
Process is the primary concurrent VHDL statement used to describe
sequential behavior.Statements in a process, are executed sequentially in zero time.
All processes in an architecture behave concurrently.
Process repeats forever, unless suspended.
NOTE : SEQUENTIAL STATEMENTS DO NOT GENERATE
SEQUENTIAL HARDWARE
Sensitivity List
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Simulator runs a process when any one of the signals in the sensitivitylist changes.
Process should either have a sensitivity list or a wait statement atthe end.
Only static signal names for which reading is permitted may appear inthe sensitivity list of a process statement.
The execution of a process statement consists of the repetitiveexecution of its sequence of statements.
If Statement
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If Statement
Syntax:
If Statement evaluates each condition in order.
Statements can be nested.
Generates a priority structure.
Corresponds to when-else command in the concurrent part.
ifcondition1 then
{ sequential_statement }
elsifcondition2 then
{ sequential_statement }
else
{ sequential_statement }
end if;
if Statement
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if Statement
Avoid using more than three levels ofIfelse
statements .
When defining the condition, use parentheses to differentiate levels of
operations on the condition.
If statement
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If statement
process (sel, a, b, c, d)
begin
If sel(2) = 1 then
y
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Syntax:
Case Statement is a series of parallel checks to check a condition.
It selects, for execution one of a number of alternative sequences of
statements.
Statements following each when clause is evaluated, only if the
choice value matches the expression value.
Case State e t
case expression iswhen choice1 => { statements }
when choice2 => { statements }
when others => { statements }
end case;
Case statement
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process (sel,a,b,c,d)
begin
case sel is
when 0=> y y y
y
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Every possible value of the case expression must be covered in
one and only one when clause.
Each choice can be either a static expression ( such as 3 ) or a
static range ( such as 1 to 3 ). we cannot have a when condition
that changes when it is being evaluated.
Invalid Case Statements
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signal VALUE: INTEGER range 0 to 15;
signal OUT_1: BIT;
EX2: case VALUE is
when 0 to 10 =>
OUT_1
OUT_1
OUT_1
OUT_1
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Does not perform any action
Can be used to indicate that when some conditions are met no action
is to be performed
Example: case a is
when 00 => q1 q2 q3
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p g
If statement produces priority-encoded logic
Example:
process ( s,c,d,e,f )
begin
if s = 00 then
pout
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p g
Case statement produces parallel logic
Example
process ( s, c, d, e, f )
begin
case s is
when 00 =>pout
pout
pout
pout
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Two types of processes:
Combinatorial
Clocked
Combinatorial Process
Generates combinational logic
All inputs must be present in the sensitivity list.
process (a,b,c)
begin
x
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Clocked Process: Generates synchronous logic.
Any signal assigned under a clkevent generates a Flip-flop.
process (clk)
begin
if (clk event and clk =1 ) then
Q < = D;
end if;
end process;
Process Statement
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Clocked processes having an else clause will generate wronghardware.
process(clk)
beginif (clk'event and clk = '1') then
out1
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Flip-flops should be reset or preset to a value on start-up because:
- Initial state of the flip-flop may not be known after power-up.
- Initial state of the flip-flop may not be the desired value after power-up.
- To place the system into a known state during operation.
Hardware Modeling Examples
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Process(CLK)begin
If CLK=1 and CLKevent then
Q
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Synchronous Reset : Flip-flops are reset on the active edge of theclock when reset is held active.
process (CLK)
begin
if ( CLK event and CLK = 1)then
if ( RST = 1 ) then
Q
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Asynchronous Reset : Flip-flops are cleared as soon as reset isasserted.
process (CLK, RST)
beginif ( RST = 1 ) then
Q
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process (clk)
begin
if (clkevent and clk = '1') then
out1
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process (clk, reset)begin
if (reset = '1' ) then
out1
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ENTITY add IS
port (a, b : IN INTEGER range 0 to 7;
z : OUT INTEGER range 0 to 15);
END add;
ARCHITECTURE arithm OF add IS
BEGIN
z
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entity test_14 is
port (
a, b, SEL : in std_logic;
c : out std_logic
);
end test_14;
architecture test_14_arch of test_14 is
begin
C
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entity test_14 is
port (
a, b, SEL : in integer;
c : out integer
);
end test_14;
architecture test_14_arch of test_14 is
begin
C
>
a [31:0]
b [31:0] c [31:0]
Sel [0]
Sel [31]
Hardware modeling Examples- Latch
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Incompletely specified Conditional expression infers a latch.
Latch is a combinational circuit which necessarily has feedback to
hold the output to previous value for the unspecified
states/conditions.
Avoid the inference of latches in synchronous designs. As latches
infer feedback and they cause difficulties in timing analysis and test
insertion applications. Most synthesizers provide warnings when
latches are inferred.
Hardware modeling Examples Latch
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incompletely specified
Conditional expression.
process (en,a)begin
if en='1' then
out1
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Process places only one driver on a signal.
Value that the signal is updated with is the last value assigned to itwithin the process execution.
Signals assigned to within a process are not updated with their new
values until the process suspends.
Wait Statement
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Wait statement : Suspends the execution of a process or procedureuntil some conditions are met.
Three basic forms:
wait on [sensitivity clause]
wait until [condition clause]
wait for [timeout clause]
Wait statement simulation view.
Wait On Clause
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Wait on statement at the end of the process is equivalent to the
sensitivity list at the beginning of the process.
process -- No Sensitivity list
begin
if ( clk'event and clk = '1')then q
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flipflop inference
process
begin
wait until clk = 1;
q
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Useful in testbenches for generating waveforms.
processbegin
clock
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downto 0) := 000 ;
clk
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g _ g _ ( )
:= "000";
clk
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clk
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Loop statements are used to iterate through a set of sequentialstatements.
Has a Boolean Iteration Scheme.
Condition is evaluated before execution.
Syntax:
loop_label: while condition loop
sequence_of_statementsend loop loop_label
Loop statements
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Loop statements are used to iterate through a set of sequential
statements.
process ( Input )
variable i : POSITIVE := 1;
begin
L1: while i
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Has an Integer Iteration Scheme. Number of repetitions is
determined by an Integer rangeThe loop is executed once for each value in the range
The loop parameters range is tested at the beginning of the loop,
not at the end.
Example : factorial := 1;
for number in 2 to N loop
factorial := factorial * number;
end loop;
Syntax:
loop_label: for loop_parameter in range loopSequence_of_statements
end loop loop_label;
For Loop Rules
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Loop parameter is implicitly defined.
Inside the loop, the loop parameter is a constant. Thus, it may be
used but not altered.
Discrete range of the loop is evaluated before the loop is first
executed.
Loop counter only exists within the loop.
Labels in loop parameters enable better loop control with the
next and exit statements.
Labels also enhance readability and maintainability.
Loop Statements - For Loop
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Bit
ReversalInput_X
7
Output _X
7
Shift_5: process (Input_X)
begin
L5: for index in Input_X'range loop
Output_X(index)
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Skips the remaining statements in the current iteration of the specified
loop.
Execution resumes with the first statement in the next iteration of the loop.
Syntax:
next loop_label when condition;
for J in 10 downto 5 loop
if sum < total_sum then
sum := sum + 2;
elsif sum = total_sum then
next;else null;
end if;
k : k+1;end loop;
Loop statements exit Statement
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Entirely terminates the execution
of the loop in which it is located.
Syntax:
exit;
exit loop_label when condition;
sum := 1; j := 0;L3 : loop
J := J + 21;sum := sum * 10;
if sum > 100 then
exit L3;end if;
end loop L3;
Note:Exit : Causes the specified loop to be
terminated.
Next :Causes the current loop iteration of
the specified loop to be prematurely
terminated; execution resumes with the nextiteration.
Signals and Variables
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SIGNALS & VARIABLES CHARACTERISTICS
SYNTHESIS VIEW
SIMULATION VIEW
Signals
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Represents wires within a circuit.
Thus Signals can be used
To connect design entities together & communicate changes in values
within a design.
Instead of inout signals.
Each signal has a history of values i.e holds a list of values which
include current value of signal & set of possible future values that are
to appear on the signal.
architecture and_gt of anding is
signal temp : std_logic;
begin
U1 : AND2 portmap (a,b,temp);
U2 : AND2 portmap (temp,a,b);
end and_gt;
>
Variables
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These are objects with single current value.
Are used to store the intermediate values between the sequential
VHDL statements.
Variable can be declared & used inside the process statement only.
But retain their value throughout the entire simulation.
process ( a )
variable a_int : integer := 1;
begin
a_int := a_int + 1;
end process;
Note : a_int contains the total
number of events that occurred on
signal a
Signals vs Variables
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Signals or variables are the objects used to store intermediate value insequential region.
A Signal has three properties attached to it Type, Value, Time.
A Variable has only two properties attached to it Type and Value.
Variables are used and declared in a process.
A variable cannot be used to communicate between processes.
Signal assignments are done using
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CASE 2 :
process (clk)
If (clkevent and clk = 1)
then
temp
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CASE 1 :
process (clk)
If (clkevent and clk = 1)
then
y
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process ( clk, a,b,c,d)
variable y, x, w : std_logic;
begin
if clk = '1' and clk'event then
1. z1
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Resulting Hardware:
Draw the Hardware for the statement sequence 3, 2,1, 5,4
Signals and Variables
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Hardware for the statement sequence 3, 2,1, 5,4
Signals and Variables
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architecture var of parity is
begin
process(a)
variable temp : std_logic;
begin
temp := '0';
for i in 0 to n loop
temp:=temp xor a(i);
end loop;
p
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architecture sig of par is
signal temp:std_logic;
begin
process (a)
begin
temp
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tb : process
beginwait for 10 ns;
sum1
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Use Variables in combinatorial processes. ( Less Simulation overhead ).
Order dependency
Signal assignments are order independent. Signals are updated at theend of process.Signals represent physical wires in the circuit.
Variable assignments are order dependent, Variables assignments aredone immediately and are executed sequentially. Variables may or maynot represent physical wires.
Signal assignments under a clocked process are translated into registers.
Variable assignment under a clocked process may or may not be translatedinto registers.
Computed value is assigned to signal after specified delay called delta delay
Variable assignment occurs immediately.
Generics
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Are specified in entities inside the generic clause.
Provides information to a block from its environment.
Example : Size of interface ports, width of components
Syntax :
generic ( [ constant_name : type [ := value ];
constant_name : type [ := value ] );
Generics
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entity AND_GATE is
generic ( N: NATURAL := 3 );
port ( A : in std_logic_vector ( 1 to N );
Z : out bit );
architecture gen_ex of and_gate is
beginprocess (A)variable and_out : bit;
begin
and_out := 1;
for K in 1 to N loop
and_out := and_out and A(K);
exit when and_out = 0;end loop;
Z
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Applications of generics
Can be used anywhere in a code where a static value is needed. Use of generics facilitates easy design changes.
Used in behavioral modeling of components.
For ex. : Timing parameters such as delays, Set-up times,
Hold times can be modeled using Generics.
Generics
Are specified in entities. Hence, any change in the value of a
generic affects all architectures associated with that entity.
Constants
Are specified in architectures. Hence, any change in the value of
a constant will be localized to the selected architecture only.
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Multivalued Logic System
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A 9-value package STD_LOGIC_1164 was developed and accepted
as IEEE Std 1164-1993. Possible states of signal are represented
using the 9 values are given below
U : Uninitialized
X : Unknown
0 : Logic 0
1 : Logic 1Z : High impedance
W : weak unknown
L : weak logic 0
H : weak logic 1
- : Dont care
U, X, W, - represent behavior of model itself rather than the behavior
of hardware being synthesized.
Multivalued Logic System
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Nine values models the behavior of the digital circuit accurately
during simulation.
Unknown, un-initialized, drive strengths - are necessary to model
the simulation. Thus represents behavior of model itself rather than
the behavior of hardware being synthesized
During synthesis high impedance condition is necessary to
describe the circuit with output enables, while the dont care state
can be used to optimize the combinational logic requirements of a
circuit. It may simplify the logic being synthesized
Unknown [X] : Value was known, but is not any more.
Un-initialized [U] : Value was never known in the first place !
High impedance [Z] : Net has no driver.
Drive strengths : Handle different output drivers.
Dont care [-] : Optimizes synthesis implementation.
Operator Overloading Need
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Predefined operators are defined only for the operands of certain
predefined types.
Example:
entity add is
port ( a : in bit;b : in bit;
c : out bit );
end add;
architecture correct of add is
c
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Arithmetic operations are not predefined in the language to work onvectors.
Example:
entity add is
port ( a : in std_logic_vector; -------- Error!b : in std_logic_vector;
c : out std_logic_vector );
end add;
architecture wrong of add is
beginc
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By using Operator Overloading we can extend the definition of
predefined operators.
Function bodies are written to define the behavior of overloaded
operators.
When the compiler encounters a function declaration in which the
function name is an operator enclosed in double quotes, the
compiler treats this function as an operator overloading function.
Ex. : function "+"( L: STD_LOGIC_VECTOR; R:STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
Packages
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Package : A convenient way to store & share declarations that are
common across many design units.
Package consists of two parts
Package declaration
Contains a set of declarations
Defines interface for package
Package body
Specifies the actual behavior
of the package.
A Package Declaration
can have only one Package body. Package body is optional.
package package_name isdeclarations
end package_name;
package bodypackage_nameis
declarations;
end package_name;
Packages
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No Component declaration
USE WORK.DECLARE.ALL;use IEEE.std_logic_1164.all;
entity AND_4BIT is
port ( X, Y, Z : in STD_LOGIC;
P :out STD_LOGIC;
);end AND_4BIT;
architecture AND_4BIT_arch of AND_4BIT is
SIGNAL TEMP1 : STD_LOGIC;
begin
U1 : and_gt PORT MAP (X,Y,TEMP1);
U2 : and_gt PORT MAP (Z,TEMP1,P);
end AND_4BIT_arch;
Component stored in
package named
declare
Packages
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Another example of package declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package declare is
component and_gt
port (
a: in STD_LOGIC;b: in STD_LOGIC;
c: out STD_LOGIC
);
end component;
end declare;
package define is
constant count : integer := 5;
type ALU_OP is(add,sub,mul,div,equ);
end define;
Packages
Package can also have function declaration In such case
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Package can also have function declaration. In such case
package declaration requires a package body which will describe
the behavior of package
package shifting is
function shift (data : std_logic_vector) return std_logic_vector; is
end shifting;
package body shifting is
function shift (data : std_logic_vector) return std_logic_vector is
variable done : std_logic_vector (data'range);
begindone := data sll 2; -- return data sll 2 (no need to declare variable)