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Dr. Ahmed H. Madian-VLSI 1
Very Large Scale Integration (VLSI)
Dr. Ahmed H. [email protected]
Lecture 5
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Dr. Ahmed H. Madian-VLSI 2
ContentsBody effects & delayWiring techniques
Width and spacingLayer selectionShieldingRepeaters
Transmission GatesTG problems
Array subsystemsGate arrays technologySea-of-gatesStandard cellMacrocell TechnologyFPGA Technology
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Dr. Ahmed H. Madian-VLSI 3
Body effect & delay
• If A goes from 0 to 1 while B, C and D are 1, then all the intermediate nodes in the pulldown chain have already been discharged and the top MOSFET sees only a small body effect.
• If D goes from 0 to 1 while A, B and C are 1, then the intermediate nodes are all one Vt below Vdd and the upper MOSFETs see a larger body effect.
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Dr. Ahmed H. Madian-VLSI 4
Wire Engineering
Goal: achieve delay, area, power goals with acceptable noise.Degrees of freedom:
Width SpacingLayerShielding
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Dr. Ahmed H. Madian-VLSI 5
Wiring techniques
Width and spacingIncreasing width of wire minimize its resistance but increase it’s capacitance platesIncreasing spacing minimize the capacitance without affecting the resistance.The best trade off depends mainly in your design
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Dr. Ahmed H. Madian-VLSI 6
Wiring techniques (cont.)Layer selection
Modern processes have six or more metal layers.
The lower layers are thin and optimized for a tight routing pitchMiddle layers often slightly thicker for lower resistance and better current-handling capability.Upper layers may be even thicker to provide a low-resistance power grid and fast global interconnect.
I/O pads, clock, power, ground
Metal 6
Interconnect between cells, critical signals
Metal 4/5
Interconnect between cells
Metal 2/3
Interconnect within cells
Metal 1purposeLayer
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Dr. Ahmed H. Madian-VLSI 7
Power and Ground bounceMetal power-carrying conductors have to be sized for three reasons:
• metal migration• power supply noise• RC delay
General rule:• limit current density• contact replication
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Dr. Ahmed H. Madian-VLSI 8
Wiring techniquesShielding
Coupling from adjacent lines impacts the delaysCoupling could be avoided if the critical signals that has a switching characteristics shielded with power or ground wires.
VDD a1 a2 GND a3 a4 VDD a1 a2GND VDD GNDa3
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Dr. Ahmed H. Madian-VLSI 9
Wiring techniques
RepeatersBoth resistance and capacitance increase with wire length lThis increase the delay
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Dr. Ahmed H. Madian-VLSI 10
Wiring techniquesRepeaters
The delay could be reduced by splitting the wire into N segments and inserting an inverter or buffer called repeater to actively drive the wire.
wwCRRC
Nl 2=Best length between repeaters could be obtained as,
To obtain this delay the inverter should use a nMOS transistor of width
CRRC
Ww
w=
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Dr. Ahmed H. Madian-VLSI 11
ContentsBody effects & delayWiring techniques
Width and spacingLayer selectionShieldingRepeaters
Transmission GatesTG problems
Array subsystemsGate arrays technologySea-of-gatesStandard cellMacrocell TechnologyFPGA Technology
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Dr. Ahmed H. Madian-VLSI 12
Transmission Gates
TG Circuits: 4 to 1 MUX
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Dr. Ahmed H. Madian-VLSI 13
TG Circuits: Problemsdifficult to get compact layoutoutputs behave like bi-directional signalsmany TG in series cause large delays
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Dr. Ahmed H. Madian-VLSI 14
ContentsBody effects & delayWiring techniques
Width and spacingLayer selectionShieldingRepeaters
Transmission GatesTG problems
Array subsystemsGate arrays technologySea-of-gatesStandard cellMacrocell TechnologyFPGA Technology
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Dr. Ahmed H. Madian-VLSI 15
Gate Arrays and Sea-of-Gates
This means to construct a common base array of transistors and personalize the chip by altering the metallization (metal and via masks) that is placed on top of the transistors.
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Dr. Ahmed H. Madian-VLSI 16
Gate Arrays Technologyprefabricated wafers
I/O stages predefinedregular array of fets and interconnection channelsinterconnection defines functionality
featuressize: 100 - 1M gatesshort turn around timecheap at medium quantitiesUnsuitable for regular structures like RAM, PLA, ALU
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Dr. Ahmed H. Madian-VLSI 17
Sea-of-Gate Technologyprefabricated wafers
I/O stages predefinedregular array of fets, no reserved interconnection channelsinterconnection defines functionality
featuressize: 100 - 1M gatesshort turn around timecheap at medium quantitiessuitable for regular structures like RAM, PLA, ALU
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Dr. Ahmed H. Madian-VLSI 18
Standard Cell Technologycomplete fabrication process
predefined library of base functionsmodular similar to TTL families
featureschip size limits complexitycheap at high quantitiesstandardized cell heightunsuitable for regular structuresmore flexible and compact than gate array
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Dr. Ahmed H. Madian-VLSI 19
Full Custom Technology
complete fabrication processtotal flexibility, only limited by layout rules manual design
featureschip size limits complexitylong design and fabrication timeefficient use of silicon areacheap only at highest quantities (ex. uP, memories, ...)
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Dr. Ahmed H. Madian-VLSI 20
Macrocell Technologycomplete fabrication process
combines semi- and full custom technologiespredefined library of base functionsgenerators for regular structures
featureschip size limits complexityshort design, long fabrication timecheap at high quantitieshigh flexibility, compact layouts
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Dr. Ahmed H. Madian-VLSI 21
FPGA Technologyfield programmable device
no fabrication needed for customizingpredefined logic blocks
featuressize: up to 2‘000’000 logic gates (see Virtexfrom Xilinx)large silicon area necessary (72 million fets)short design and customize timecheap for small quantitiescompared to ASICs, FPGAs have a reduced clock speedcircuit configuration downloadable (RAM or PROM)
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Dr. Ahmed H. Madian-VLSI 22
Field Programmable Gate Array (FPGA)
Programming technologyProgrammable logic cellsProgrammable interconnect
Anti fuse (One time programmable, ex. Actel)Static RAM (volatile, ex. Xilinx)EPROM or EEPROM (non-volatile, ex. Altera)
Programmable I/O’s
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Dr. Ahmed H. Madian-VLSI 23
Programmable Logic Cells The logic cells could be programmed to realize a logic function the main blocks are:
Multiplexer based (ACTEL)Look-up tables (XILINX)AND-OR array (ALTERA)
What is the suitable number of input for the logic cell?
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Dr. Ahmed H. Madian-VLSI 24
Programmable Logic CellsMultiplexer Based logic cells
The logic function could be written using shanon’sexpansion theorem:
01 ..,..),,( == += AA FAFACBAF
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Dr. Ahmed H. Madian-VLSI 25
Programmable Logic Cells
Realize the following logic function using Multiplexer Based logic cells
DBCBAF ++= ..
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Dr. Ahmed H. Madian-VLSI 26
Programmable Logic CellsMultiplexer Based logic cells
).().(
1
).(..
DCBDABF
BBwhere
BBDBCBAF
+++=
=+
+++=
FB=1 = A+D = A(1) + A(D)FB=0 = C+D = C(1) + C(D)
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Dr. Ahmed H. Madian-VLSI 27
Programmable Logic CellsMultiplexer Based logic cells
Combinational module (C-module)Sequential module (S-module)
(C-module) (S-module)