Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
VLSI electronics for the read-out of radiation sensors
Angelo Rivetti – INFN - Torino
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Topics
Introduction
Architectures for read-out ASICs
Why deep submicron CMOS?
A detailed example: the ALICE SDD front-end
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Why integrated ?
Historically, dedicated integrated circuits came into play in nuclear electronics with the advent of silicon detectors. Nowadays they are used to read-out most radiation detectors, including gas detectorsThe possible use of APDs as an alternative to PMTs further increase the range of application of custom integrated I.Cs. The use of I.Cs is motivated by the need of reading many channels minizing material and power consumption
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
The LHC scaleThe LHC detectors need an unprecedented number of electronicschannels…
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
ALICE
Silicon pixels: 0.2 m2, 9.3MchSilicon drift: 1.3m2, 133kchSilicon strip: 4.9m2, 2.6MchTPC: Volume 88m3, 1Mch … and many others…
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
ATLAS & CMSIn term of number of channels, ALICE is dwarfed by ATLAS & CMS
CMS210m2 silicon microstrip sensors9.6 Mch
ATLAS61m2 silicon microstrip sensors6.3 Mch
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
A detector example
You have to read-out something like this….(SDD of ALICE)
Many independent channelshave to be read
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Basic design choices
From system specs to
Selection of the architecture
System partitioning
Technology choice
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Architecture selection (1)
Analog read-out
+ No info loss Amplitude preserved Easier to debug
S&H
- Big amount of data Analog data handling
Very common for the read-out of silicon microstrip
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog read-out example
The APV chip for the CMS tracker128 analog channelsPreamp & analog pipelineAnalog deconvolution processorCMOS 0.25m technology46.8 mm2
2mW/channel
Reference:L.L Jones et al.The APV25 Deep Submicron ReadOut Chiphttp://lebwshop.home.cern.ch/lebwshop/LEB99_Book/Tracker/Jones.pdf
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Architecture selection (2)
Binary read-out
+ Simple Fast Minimum amount of data
- No information on
amplitude More difficult to debug
VTH
Standard for the read-out of pixel detectors Common also for strip detectors
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Binary read-out example
The ABCD chip for the ATLAS microstrip128 channelsPreamp & discriminatorDigital pipeline46.8 mm2
2mW/ch
BiCMOS 0.8m rad-hard Reference:W. Dabrowski et al.Design an performance of the ABCD chip for the binary readout of silicon strip detectors in the ATLAS semiconductor trackerIEEE TNS, vol. 47, no. 6, Dec. 2000
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Architecture selection (3)
Mixed-mode readout
+ No information loss Robust
- Large data volume Mixed-mode IC more
difficult to design
We will see more on this later…
ADC
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Mixed-mode readout example
The ALTRO chip for the ALICE TPC16 ADCEmbedded digital processingDigital tail cancellationCMOS 0.25m technology64 mm2
16mW/ch @ 10 MSPSPreamp on a separate IC
Reference:R. Esteve Bosch, L. Musa, et. alThe ALTRO chip: A 16 Channel A-D converter and digital processor for Gas DetectorsIEEE NSS – MIC, Norfolk, Nov. 2002.
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Why deep-submicron CMOS ?
CMOS already popular in the design of front-end
vnoise2Ct
2K2(n)ENC2 = inoise
2K1(n)s + s
Bipolar traditionally better at short shaping time,due to the base current shot noise
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Process trends in CMOS technologies
Year 1992 1995 1999 2001 2003
Minimum size(m)
0.5 0.35 0.25 0.18 0.13
Tox (nm) 9-12 7-10 5-7 3-4 2-3
Metal levels 4 5 6 7 8
Supply (V) 3.3-5 2.5-3.3 2.5-3.3 1.8-2.5 1.2-1.8
Waferdiameter (mm)
200 200 200 300 300
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Interconnection example
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Digital vs analog
The scaling of CMOS technologies is driven by the need of improving the perfomance of digital ICs The need of analog design not taken too much into account Analog features come usually later Digital circuits improve with scaling, but what about analog ones?
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog properties and process scaling: (1)
tOX scales, k=Cox =OX/tOX scales => for the same W /L andthe same current gm improves
Lmin (m) tox (nm) k (A/V2)
1.2 24 68
0.8 14 90
0.5 10 134
0.25 5 280
k for different technologies (NMOS devices)
gm = 2 n COXWL
IDS
This is for strong inversion…
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog properties and process scaling: (2)
k=Cox scales => for the same W and L:
W.I.-S.I. boundary moves towards higher currents:
Ilim=2nk(W/L)UT2
0
5
10
15
20
25
30
1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01
ID [A]
gm/IDS max in W.I.
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog properties and process scaling (3)
tox scales => Cox and k=Cox increase. For the same W and L:
matching improves:
flicker noise is reduced:
transconductance increases:
WLtoxB
VTH
S V
K a
C WLfox2
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
0 VddVTp Vdd-VTn
gds
Vdd=5V
0 VddVdd-VTn VTp
gds
Vdd=1.6Vck
ck_b
Vin
Problem: SC circuits operation (1)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
W/L=200/0.36
CL=20pF
fin=2.5MHz
ck
ck_b
VinCL
Problem: SC circuits operation (2)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Problem: substrate noise
P+
P-digitalanalog
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog properties and process scaling: (3)
tox scales => Vdd must be scaled as well
Minimum power consumption for class A analog circuits:
VVdd
VddfSNRkT8P sig
V is the fraction of the power supply not used for signal swing
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Analog properties : summary
Transistor properties improve, but signal swing is reduced
=> is there an optimum?
Optimal power/performance trade-off may occur with 0.35 - 0.25 m!
(A. J. Annema, IEEE Trans. On Cicuits and Systems, II vol 46, No. 6, June 1999).
In 0.25 m CMOS (2.5V) conventional architectures still work!
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Effect of radiation on MOS (1)
The sensitive part is the oxide A ionizing particle creates electron- hole pairs In the oxide, the mobility of holes is much smaller than the one of electrons (7-12 orders of magnitude) Three main effects arise: => threshold shift of the main device => threshold shift of parasitic devices => interface state generation
SiO2
n+
gate
P-
n+
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Effect of radiation on MOS (2)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Effect of radiation on MOS (3)
polisilicon
nwell
n+
Vdd Vss
source++++++++++
Inter-device leakage via thick oxide
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Rad-tol design approach
SDG
D
S
G
• Thin oxide + enclosed layout & guardring (ELT) = radiation tolerance• Deep submicron CMOS is a good choice for rad-tol IC for HEP• Single Event Effect may worsen, but... • Extesively studied by the CERN RD49 collaboration
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Silicon Drift Detector (SDD)
• Drift of charged particles
in silicon• 2-dimension
measurement• 20m resolution• dE/dx measurement with
analog read-out• “few” read-out channel• drift speed 5m/ns• but…v=E, T-2.4!
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
.....
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Total number of channels: 130000 Input charge 500e- to 250000e- Input signal: Gaussian (amplitude 10nA - 1.6A; 10ns – 30ns) Shaping time: 40ns Sampling frequency: 40 MS/s Bits/sample: 10 Noise < 500 e- rms (250e- rms) Power/channel < 5mW Front-end board: 8 x 2 cm2
System dead time: < 1ms Reduce material as much as possible
SDD system specifications
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
On the front-end board space for 8 VLSI chips Optimize the system for minimum output connections Preamplifier Sampling: 1 FADC/channel: impractical for power and space First level analog buffer (SCA) + slower ADC Commercial slower ADC: impractical for space Commercial slower ADC: analog data handling No analog processing, ADC on the front-end chip Front-end integration: 64 channel/chip as a compromise
between space and yield (8 FE chips per detector)
System partitioning (1)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Output lines @ 40MHz clock: two 10bit busses/chip
16 busses per detector: 160 lines ( too many!)
Solution: local digital buffering (2nd chip)
10bit to 8 bit reduction on the digital buffer
Two 8 bit busses per detector (=less material)
Only one 8 bit bus per front-end with acceptable dead time
8 chips on the FE board, 16 chips per detector
System partitioning (2)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
A look at the system...
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
... and at the chip
Preamp Analog memorySAR ADC
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Preamplifier specs
• Input capacitance capacitance: 1 - 3 pF• Input signal 1 to 8 mips• Peaking time < 50 ns (separation of close tracks)• Noise < 500 e- r.m.s• Power consumption < 2mW/ch
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Preamplifier block diagram (1)
PA SH
BH
In Out
Vref
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Preamplifier block diagram (2)
PA SH
BH
In Out
Vref
Vfeed
Cf Cz
If
Rf Rz
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Core amplifier schematic
In
Vcas
VB VB
VBC VBC
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Baseline holder schematic
VB
VB VB
VB
VB VBVref Out
In_sh
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Buffer schematic
VB
VinVout
Cload
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Shaper time constant tuning
OutSH
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Response to 1 mip
Response for 1 mip
1.72
1.74
1.76
1.78
1.8
1.821.84
1.86
1.88
1.9
1.92
0.0E+00 6.0E-08 1.2E-07 1.8E-07 2.4E-07 3.0E-07
time
volta
ge
V = 164 mV
Tp = 32 ns
(s)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Layout example
PAIn
Vfeed
Cf Cz
If
Rf Rz
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Memory Channel Schematic
Vref_w
IN
+
Vref_r
OUT
Digital Control Logic
SW_W SW_R SW_F
G. Anelli et al.IEEE TNS, vol48 (3), pp. 435 – 439)June 2001
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Which Capacitors for Storage? (1)
p+n+ n+
n well
p substrate
p+n+ n+
p substrate
GND
V
GND
V
NMOS Transistor Inversion Region
PMOS Transistor without S and DAccumulation Region
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Which Capacitors for Storage? (2)
0.20.30.40.50.60.70.80.9
11.1
-2.5 -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 2.5Vbias [ V ]
C /
Co
x
PMOS (no S & D) N+ poly - N wellPMOS (S & D float.) P+ poly - N well
NMOS (S & D connected)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Design of a compact CMOS ADC
• Conventional SAR based successive approximation scheme• Good trade-off between speed, area and power• Clock speed: 20 MHz• Single rail operation
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
ADC design criteria:
Maximum full scale range: Vref
Limit due to noise:
Minimum capacitor allowed by the technology: 75fF
DAC power consumption
Power consumption dominated by the comparator
Vdd, Vin Vref
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
• Capacitive sub-dac without buffer => larger non-linearity, but negligible at 10 bits level
DAC Architecture (3)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
DAC layout
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Comparator block diagram
IN -
+ +IN +
Vref
Vref
S1
S2
S3
S4
S5
S6
LATCH
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Comparator schematic...
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
... and layout
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Prototyping
Microelectronics circuits are cheap in large volumeThe cost of the masks is a fixed offsed (about 100 k$)The cost of the wafers is low (about 2k$)In the research environment the mask costs is usually shared among several users (MPW runs)Typical prototyping cost: 500 $/mm2
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Very first prototypes (RD49)
ADC Analog memory 2 x 2 mm2, cost 2k$ each
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
First SDD front-end prototype
• 32 channels with preamp and analog memory
• 16 ADCs on chip
• Power consumption 5mW/ch
• Noise: 210 e- @ 3pF
• External bias and control for test purposes
• Area: 42mm2, cost: 21k$
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Response to 4fC
0
50
100
150
0 10 20 30 40 50 60
Cell number
AD
C c
ount
s
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Linearity
0
200
400
600
800
1000
0 10 20 30 40
Input charge (fC)
AD
C c
oun
ts
INL < 1%, mainly due to the preamp
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Pulse shape fitting
Fit to a CR – RC3
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Radiation tolerance
Before and after 30 Mrd
0
200
400
600
800
1000
0 10 20 30 40
Input charge (fC)
AD
C c
ount
s
y1=25.9*x+21y2=26.1*x+34
Noise increase <10%
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
From 32 to 64 channels
Final version: 64 channels, same building blocks of the first version plus:
internal bias generators
internal DAC for baseline setting
internal programmable pulse generator
Low drop-out voltage regulators
JTAG protocol for parameters download
LVDS interface.
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
The chip …
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
…and a test set-up
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
A typical problem…
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Probe station testing
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Probe card detail
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
DC parameters
Analog current: average 93.22mA; rms 3.6mA Digital current: average 131.4mA; rms 5.3mA Vref1: average 1.926V; rms 4.2mV (design: 1.925V) Vref0: average 0.524V; rms 2.8mV (design: 0.525V)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of signal
1 mip = 108 ADC counts
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of baseline (1)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of baseline (2)
Noise : 300 e- rms
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of calibration (1)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of calibration (2)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Example of calibration (3)
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Linearity (1)
0
200
400
600
800
1000
0 200 400 600
DAC code
AD
C c
od
e
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Linearity (2)
0,00
1,00
2,00
3,00
4,00
0 200 400 600
DAC code
% D
evi
ati
on
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
On chip uniformity
Baseline average 100.8 ADC counts; rms 3.8 Gain: average 108 ADC counts/mip; rms 0.4
708090
100110120
0 8 16 24 32 40 48 56 64
channel number
bas
elin
e
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
Discrete…
2 cm
1 cm
1 channelminimum power: 10mWpower supply: 4V to 25Vcurrent: 2.3mAshaping time: 2.4snoise < 280 e- rmssize: 2cm x 1cm
Angelo Rivetti – INFN Sezione di Torino University of Siegen – Feb. 20, 2003
… and integratedCMOS 0.25m technology64 channels32 10 bits ADCPower 8mW/chShaping time: 40nsNoise < 280 e- rmsSize: 1cm x 0.9cm
1 cm
Front – end for ALICE SDD