Technische Universität MünchenInstitute forElectronic Design Automation
Unified Generation of Analog Sizing and Placement Constraints
Michael Eick and Helmut Graeb
Institute for Electronic Design AutomationProf. Dr.-Ing. Ulf Schlichtmann
Technische Universität München
Technische Universität MünchenInstitute forElectronic Design Automation
Overview
• Analog constraints
• Unified constraint generation flow– Universal constraint graph– Sizing and placement constraint generation
• Experimental results
• Conclusion
2
Technische Universität MünchenInstitute forElectronic Design Automation
Constraints in Design Flow
3
specification
structure
sizing
placement
routing
analog block
sizing constraints
placement constraints
routing constraints
process variations,parasitic devices etc.
structural analysis
univ
ersa
l co
nstr
aint
s
Technische Universität MünchenInstitute forElectronic Design Automation
Matching Constraints - Sizing
4
[Hastings, The Art of Analog Layout]
equal lengths
fixed ratio (optional)
current matching (optional)
voltage matching (optional)
limited Vgs, Vds mismatch
min
imal
max
imal
mod
erat
e
Technische Universität MünchenInstitute forElectronic Design Automation
Matching Constraints - Placement
5
min
imal
max
imal
mod
erat
e
[Hastings, The Art of Analog Layout]
equal finger geometriesequal orientationclose proximity
common centroid
quadratic common centroid
Technische Universität MünchenInstitute forElectronic Design Automation
More Constraints
6
Operating Point Constraintslinear / saturation region
Symmetric Place & Route Constraints
Technische Universität MünchenInstitute forElectronic Design Automation
State of the Art
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sizingconstraints
Massier et al. TCAD’08
placementconstraints
sensitivityanalysis
building blockanalysis
symmetryanalysis
Eick et al. TCAD’11
Kole et al. ISCAS’94 Hao et al. ICCCS’04
Malavasi et al. TCAD’96 Chen et al. IEE Proc. G’92
Abstract constraint management concepts [Jerke et al. ISPD’09]
Technische Universität MünchenInstitute forElectronic Design Automation
Structural Analysis
Building Block Analysis[Massier et al. TCAD’08]
• comparison with library• ambiguity resolution
Symmetry Analysis[Eick et al. TCAD’11]
• Structural Signal Flow Graph• propagation of symmetry pairs
8
currentmirror
differential pair
Technische Universität MünchenInstitute forElectronic Design Automation
Unified Constraint Generation Flow
9
netlist
building blocks
symmetrical devices
universal constraintgraph
sizing constraints
placement constraints
Technische Universität MünchenInstitute forElectronic Design Automation
Overview
• Analog constraints
• Unified constraint generation flow– Universal constraint graph– Sizing and placement constraint generation
• Experimental results
• Conclusion
10
Technische Universität MünchenInstitute forElectronic Design Automation
Universal Constraint Graph (UCG)
Edge Constraint Attributes
proximity
operating pointrobust operation
region: linear, saturation
matchinggrade: minimal, moderate, maximaltype: undefined, voltage, i currentratio: variable, fixed(value)
symmetry
11
Undirected Graph• Nodes: Devices• Edges:
Technische Universität MünchenInstitute forElectronic Design Automation
UCG Generation - Overview
12
building blocks
netlist
symmetrical devices
Edge Constraint
proximity
op. point / robust op.
matching
symmetry
Technische Universität MünchenInstitute forElectronic Design Automation
UCG Generation - Netlist
13
building blocks
netlist
symmetrical devices
Edge Constraint
proximity
op. point / robust op.
matching
symmetry
Technische Universität MünchenInstitute forElectronic Design Automation
UCG Generation – Building Blocks
14
s s s
s s
min,i,v min,i,v
max,v,f(1)
s
building blocks
netlist
symmetrical devices
Edge Constraint
proximity
op. point / robust op.
matching
symmetry
Technische Universität MünchenInstitute forElectronic Design Automation
UCG Generation - Symmetry
15
building blocks
netlist
symmetrical devices
Edge Constraint
proximity
op. point / robust op.
matching
symmetry
mod,u,f(1)
mod,u,f(1)
mod,u,f(1)
Technische Universität MünchenInstitute forElectronic Design Automation
Unified Constraint Generation Flow
16
netlist
building blocks
symmetrical devices
universal constraintgraph
sizing constraints
placement constraints
Technische Universität MünchenInstitute forElectronic Design Automation
Sizing Constraint Generation
17
operating point
linear saturation
matching
minimal moderate maximal
general
current voltage
variable ratio fixed ratio
robust operation
Edge Constraint
proximity
op. point / robust op.
matching
symmetrygeneral
Technische Universität MünchenInstitute forElectronic Design Automation
Sizing Constraint Examples
18
operating point
linear saturation
matching
minimal moderate maximal
general
current voltage
variable ratio fixed ratio (q=1)
robust operationgeneral
Technische Universität MünchenInstitute forElectronic Design Automation
Placement Constraint Generation
19
proximity
matching
minimal moderate perfect
general
variable ratio fixed ratio
symmetric placement
Edge Constraint
proximity
op. point / robust op.
matching
symmetry
general
general
Technische Universität MünchenInstitute forElectronic Design Automation
Placement Constraint Examples
20
proximity
matching
minimal moderate maximal
general
variable ratio fixed ratio (q=1)
symmetric placement
general
general
Technische Universität MünchenInstitute forElectronic Design Automation
Overview
• Analog constraints
• Unified constraint generation flow– Universal constraint graph– Sizing and placement constraint generation
• Experimental results
• Conclusion
21
Technische Universität MünchenInstitute forElectronic Design Automation
Experimental Results - Placement
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Schematic Layout
A0 [dB] 72 dB 72 dB
fT [MHz] 12.9 MHz 12.6 MHz
CMRR [dB] 138 dB 144 dB
Voffset [mV] 0.008 mV 0.3 mV
Yield [%] 99.0 % 98.8 %
Technische Universität MünchenInstitute forElectronic Design Automation
Conclusion
• Knowledge of constraints necessary for (automatic) design of analog circuits
• Unified constraint generation flow– Structural analysis– Universal constraint graph– Generation of sizing and placement constraints
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