A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Cover Sheet
Custom
1 41
Wednesday, January 16, 2008
2007/12/12 2008/12/12
Schematics Document
U1 - KAL00
Compal Confidential
AMD S1g2/ ATI RS780M / SB700
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Block Diagrams
Custom
2 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Power On/Off CKT.
Project Code: ANRKAL0000(KAL00)
LPC BUS
page 27
Compal confidential
page 23
HT 16x16 1.6G~3.2GHZ
A-Link Express
DC/DC Interface CKT.
Power Circuit DC/DC
PCI BUS
AMD S1g2 CPU
page 33
page 34
ATI-RS780M
page 4,5,6,7
RTC CKT.
page 33
HD-Interface
page 10,11,12,13
ATI-SB700
page 17,18,19,20,21
Audio Jack
Power OK CKT.
page 17
page 31Felica Conn
page 35~42 Touch Pad CONN.
ENE KB926page 29
page 31
Int. KBDpage 31
SPI BIOSpage 29
USB 2.0
SATA GEN2
SATA HDD Conn.
ALC269Audio CKT
File Name : LA-4381P
LCD CONNpage 15
4 x PCIE
page 15
CRT
Clock GeneratorSLG8SP626VTR/ICS9LPRS476BKLFT
page 6 page 14
Thermal SensorADM1032ARM DDR-2 DDR2-SO-DIMM X2
Daul Channel DDR-2Up to 800MHz
page 8,9
page 26
RJ45 CONN
page 25
BroadcomBCM5784M
page 24
Mini Card WLAN
PCI EXPRESS
page 32USB conn x 4USB 2.0
Turion64 x2 TLxx / SempronPCB P/N:
Express Card(New Card)
page 24
Ricoh R5C833Crad Reader Controller
page 22
Media Cardpage 22
SATA ODD Conn.page 23
BUS A-->JDIM2-->UPPER SLOTBUS B-->JDIM1-->LOWER SLOT
SATA GEN2
page 28
HDMI CONNpage 16
page 23Hyper Flash
IDE
ZZZ1
15W_PCB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Notes
Custom
3 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Voltage Rails
VINB++CPU_CORE0,1
Adapter power supply (19V)AC or battery power rail for power circuit.Core voltage for CPU
External PCI DevicesDevice IDSEL# REQ#/GNT# InterruptsCardBus AD21
EC SM Bus1 addressDevice
ADM1032
S1 S3 S4/ S5
ON OFF
Power Plane Description
OFF
EC SM Bus2 addressDevice
Smart Battery
0 PIRQE/PIRQF/PIRQG
EEPROM(24C16/02)
1001 110X b?0001 011X b?
1010 000X b?
(24C04) 1011 000Xb?
SB700 SM Bus addressDevice
Clock Generator (ICS9LPRS476BKLFT)
Address
Address Address
1101 001Xb?
STATESIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Board ID Table for AD channel
DDRII DIMM0 1001 000Xb?
DDRII DIMM1 1001 010Xb?
Vcc 3.3V +/- 5%100K +/- 5%Ra / Rc
Board ID Rb / Rd V min0123
08.2K +/- 5%
0 V0.216 V 0.250 V 0.289 V0.436 V0.712 V
0.503 V0.819 V
0.538 V0.875 V
AD_BID V typAD_BID VAD_BID max
18K +/- 5%33K +/- 5%56K +/- 5%100K +/- 5%200K +/- 5%
3.300 V
0 V 0 V
4567 NC
1.036 V1.453 V 1.650 V 1.759 V1.935 V2.500 V
2.200 V3.300 V
2.341 V
1.185 V 1.264 V
BOARD ID Table Board ID
01234567
PCB Revision
BTO Option TableBTO Item BOM Structure
ON ON ONONONON
0.1 (U1 ES1)0.2 (U1 ES2)0.3 (U1 PP)0.4 (U1 PPR)1.0 (U1 IRT)
+0.9V 0.9V switched power rail for DDR terminator
+1.5VS+1.8VS 1.8V switched power rail+1.8V+3VALW
1.8V power rail for DDR3.3V always on power rail
+1.2VALW 1.2V always on power rail ONONON
ON OFF OFF1.5V switched power rail
+1.2V_HT
ON OFF OFF
1.2V switched power rail
+RTCVCC RTC power+5VS
+3VS+5VALW 5V always on power rail
3.3V switched power rail
5V switched power railON ONON
ONOFF
OFF
OFFON
ONON ON
OFF
ON
ON ON
ON OFFON OFF OFF
ONON OFFON
+VDDNB +0.8V~1.1V CPU NBVDD ON ON OFF
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CADIN[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CADIP[0..15]
FAN1_POWEREN_DFAN1
H_CADIN14
H_CADIN15
H_CADIN12H_CADIP12
H_CADIP13
H_CADIP14H_CADIN13
H_CADIN10H_CADIP10
H_CADIN11
H_CADIN9
H_CADIP11
H_CADIN8H_CADIP9
H_CADIP8H_CADIN7H_CADIP7H_CADIN6
H_CADIP4H_CADIN4H_CADIP5
H_CADIP6H_CADIN5
H_CADIN2
H_CADIN1
H_CADIP3H_CADIN3
H_CADIP1
H_CADIP15
H_CADIP2
H_CADIN0H_CADIP0
H_CADON10
H_CADON1
H_CADON9
H_CADON3
H_CADOP11
H_CADOP15
H_CADOP12
H_CADOP14
H_CADOP13
H_CADOP7
H_CADOP1
H_CADOP8
H_CADOP10
H_CADOP9
H_CADOP6
H_CADOP2
H_CADOP3
H_CADOP4
H_CADOP0
H_CADOP5
H_CADON11
H_CADON12
H_CADON14
H_CADON13
H_CADON15
H_CADON4
H_CADON5
H_CADON6
H_CADON7
H_CADON8
H_CADON0
H_CADON2
H_CLKIN0
H_CLKIN1H_CLKIP1
H_CLKIP0
H_CLKOP1H_CLKON1
H_CTLON0H_CTLOP0H_CTLIP0
H_CTLIN0
H_CLKON0H_CLKOP0
H_CTLOP1H_CTLON1H_CTLIN1
H_CTLIP1
H_CADON[0..15] <10>H_CADIN[0..15]<10>
H_CADOP[0..15] <10>H_CADIP[0..15]<10>
FAN_SPEED1<28>
EN_DFAN1<28>
H_CLKIN1<10>
H_CLKIN0<10>H_CLKIP0<10>
H_CTLIN0<10>
H_CLKIP1<10>
H_CTLIP0<10> H_CTLOP0 <10>
H_CLKOP0 <10>
H_CLKOP1 <10>H_CLKON1 <10>
H_CLKON0 <10>
H_CTLON0 <10>H_CTLOP1 <10>H_CTLON1 <10>
H_CTLIP1<10>H_CTLIN1<10>
+5VS
+5VS
+3VS
+1.2V_HT
+1.2V_HT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Griffin HT I/F & FANCustom
4 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
FAN1
FAN1 Control and Tachometer
40mil
close to CPU Socket
1.5A
C539
0.22
U_0
603_
10V7
K
1
2
C545 10U_0805_10V4Z~N
@1 2
JFAN1
ACES_85205-0300N~NCONN@
123G4G5
C521
180P
_040
2_50
V8J~
N
1
2
C5271000P_0402_50V7K~N
@12
C543
4.7U
_080
5_6.
3V6K
~N
1
2
D26 BAS16_SOT23-3
@12
C523
4.7U
_080
5_6.
3V6K
~N
1
2
C5400.01U_0402_16V7K1
2
C522
0.22
U_0
603_
10V7
K
1
2
C54110U_0805_10V4Z~N
@12
U25
G993P1UF_SOP8
VEN1VIN2
GND 5GND 6
GND 8
VO3VSET4
GND 7
C526
180P
_040
2_50
V8J~
N
1
2HT LINK
JCPU1A
FOX_PZ6382A-284S-41F_TURION<BOM Strucrure>
VLDT_A3D4 VLDT_A2D3 VLDT_A1D2 VLDT_A0D1
VLDT_B3 AE5VLDT_B2 AE4VLDT_B1 AE3VLDT_B0 AE2
L0_CADIN_H15N5L0_CADIN_L15P5
L0_CADIN_H14M3L0_CADIN_L14M4
L0_CADIN_H13L5L0_CADIN_L13M5
L0_CADIN_H12K3L0_CADIN_L12K4
L0_CADIN_H11H3L0_CADIN_L11H4
L0_CADIN_H10G5L0_CADIN_L10H5
L0_CADIN_H9F3L0_CADIN_L9F4
L0_CADIN_H8E5L0_CADIN_L8F5
L0_CADIN_H7N3L0_CADIN_L7N2
L0_CADIN_H6L1L0_CADIN_L6M1
L0_CADIN_H5L3L0_CADIN_L5L2
L0_CADIN_H4J1L0_CADIN_L4K1
L0_CADIN_H3G1L0_CADIN_L3H1
L0_CADIN_H2G3L0_CADIN_L2G2
L0_CADIN_H1E1L0_CADIN_L1F1
L0_CADIN_H0E3L0_CADIN_L0E2
L0_CADOUT_H15 T4L0_CADOUT_L15 T3
L0_CADOUT_H14 V5L0_CADOUT_L14 U5
L0_CADOUT_H13 V4L0_CADOUT_L13 V3
L0_CADOUT_H12 Y5L0_CADOUT_L12 W5
L0_CADOUT_H11 AB5L0_CADOUT_L11 AA5
L0_CADOUT_H10 AB4L0_CADOUT_L10 AB3
L0_CADOUT_H9 AD5L0_CADOUT_L9 AC5
L0_CADOUT_H8 AD4L0_CADOUT_L8 AD3
L0_CADOUT_H7 T1L0_CADOUT_L7 R1
L0_CADOUT_H6 U2L0_CADOUT_L6 U3
L0_CADOUT_H5 V1L0_CADOUT_L5 U1
L0_CADOUT_H4 W2L0_CADOUT_L4 W3
L0_CADOUT_H3 AA2L0_CADOUT_L3 AA3
L0_CADOUT_H2 AB1L0_CADOUT_L2 AA1
L0_CADOUT_H1 AC2L0_CADOUT_L1 AC3
L0_CADOUT_H0 AD1L0_CADOUT_L0 AC1
L0_CLKIN_H1J5L0_CLKIN_L1K5
L0_CLKIN_H0J3L0_CLKIN_L0J2
L0_CTLIN_H1P3L0_CTLIN_L1P4
L0_CTLIN_H0N1L0_CTLIN_L0P1
L0_CLKOUT_H1 Y4L0_CLKOUT_L1 Y3
L0_CLKOUT_H0 Y1L0_CLKOUT_L0 W1
L0_CTLOUT_H1 T5L0_CTLOUT_L1 R5
L0_CTLOUT_H0 R2L0_CTLOUT_L0 R3
D271SS355TE-17_SOD323-2 @
12
C544
4.7U
_080
5_6.
3V6K
~N
1
2
R36410K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
4 4
3 3
2 2
1 1
DDR_A_CLK2
DDR_A_CLK1
DDR_A_CLK#1
DDR_A_CLK#2
DDR_B_CLK2
DDR_B_CLK#2
DDR_B_CLK1
DDR_B_CLK#1
DDR_B_D33
DDR_B_D30DDR_B_D31
DDR_A_D59
DDR_B_D29
DDR_B_D35
DDR_B_D37DDR_B_D36
DDR_B_D32
DDR_B_D40
DDR_A_D9
DDR_B_D38
DDR_B_D42
DDR_B_D39
DDR_B_D41
DDR_B_D44
DDR_B_D46DDR_B_D45
DDR_B_D47DDR_B_D48
DDR_B_D43
DDR_B_D49DDR_B_D50
DDR_B_D52DDR_B_D51
DDR_B_D55DDR_B_D54
DDR_B_D57DDR_B_D56
DDR_B_D58
DDR_B_D60
DDR_B_D53
DDR_B_D62
DDR_A_DM2
DDR_A_D34
DDR_A_D21
DDR_B_D7
DDR_A_DM3
DDR_A_D46
DDR_A_DM4
DDR_B_DM0
DDR_A_D8
DDR_A_D58
DDR_A_DM5
DDR_B_DM1
DDR_B_D8
DDR_A_D33
DDR_A_D20
DDR_A_DM6
DDR_B_DM2
DDR_A_DM7
DDR_B_DM3
DDR_A_D45
DDR_B_DM4
DDR_A_D57
DDR_A_D32
DDR_B_DM5
DDR_A_D7
DDR_B_DM6
DDR_B_D63
DDR_B_D10
DDR_A_D44
DDR_B_DM7
DDR_A_D19
DDR_A_D56
DDR_A_D31
DDR_B_D11
DDR_A_D6
DDR_A_D43
DDR_A_D18
DDR_A_D55
DDR_B_D12
DDR_A_D30
DDR_A_D5
DDR_A_D42
DDR_B_D13
DDR_A_D17
DDR_A_D54
DDR_A_D29
DDR_A_D4
DDR_B_D14
DDR_A_D41
DDR_A_D16
DDR_A_D28
DDR_A_D53
DDR_A_D3
DDR_B_D15
DDR_A_D40
DDR_A_D15DDR_B_D16
DDR_A_D27
DDR_A_D52
DDR_A_D2DDR_A_D1DDR_A_D0
DDR_B_D9
DDR_A_D26
DDR_A_D63
DDR_A_D14
DDR_A_D39
DDR_B_D0
DDR_B_D17
DDR_A_D51
DDR_B_D1
DDR_B_D18
DDR_A_D13
DDR_A_D38
DDR_A_D25
DDR_A_D50
DDR_B_D2
DDR_B_D19
DDR_A_D62
DDR_A_D12
DDR_A_D37
DDR_B_D3
DDR_A_D24
DDR_B_D20
DDR_A_D49
DDR_A_D61
DDR_A_D11
DDR_B_D21
DDR_B_D4
DDR_A_D36
DDR_A_D23
DDR_A_D48
DDR_A_D60
DDR_B_D5
DDR_A_D10
DDR_A_D35
DDR_A_D22
DDR_A_DM0
DDR_B_D6
DDR_A_D47
DDR_A_DM1
DDR_B_D59
DDR_B_D61
DDR_B_DQS6DDR_B_DQS#6
DDR_B_DQS2DDR_B_DQS#2
DDR_B_DQS5DDR_B_DQS#5
DDR_B_DQS1DDR_B_DQS#1
DDR_B_DQS4DDR_B_DQS#4
DDR_B_DQS0DDR_B_DQS#0
DDR_B_DQS7DDR_B_DQS#7
DDR_B_DQS3DDR_B_DQS#3
DDR_A_DQS0DDR_A_DQS#0
DDR_A_DQS7DDR_A_DQS#7
DDR_A_DQS3DDR_A_DQS#3
DDR_A_DQS6DDR_A_DQS#6
DDR_A_DQS2DDR_A_DQS#2
DDR_A_DQS5DDR_A_DQS#5
DDR_A_DQS1DDR_A_DQS#1
DDR_A_DQS4DDR_A_DQS#4
DDR_B_D22DDR_B_D23
DDR_B_D28
DDR_B_D26DDR_B_D25DDR_B_D24
DDR_B_D27
DDR_B_D34
DDR_B_CLK#1
DDR_B_WE#DDR_B_CAS#
DDR_B_BS#0DDR_B_BS#1DDR_B_BS#2
DDR_B_MA5
DDR_B_MA1
DDR_B_RAS#
DDR_B_CLK#2
DDR_B_MA3
DDR_B_MA14
DDR_B_CLK2
DDR_B_ODT1
DDR_B_MA8
DDR_B_MA15
DDR_B_MA4
DDR_B_MA9
DDR_B_CLK1
DDR_B_MA7
DDR_B_MA10
DDR_B_MA12
DDR_B_MA0
DDR_B_ODT0
DDR_B_MA6
DDR_B_MA11
DDR_B_MA13
DDR_B_MA2
DDR_A_CLK#1
DDR_A_CLK#2DDR_A_CLK2
DDR_A_ODT0
DDR_A_CLK1
DDR_A_ODT1
DDR_A_MA9
DDR_A_CS0#
DDR_A_MA14
DDR_A_MA8
DDR_A_MA13
DDR_A_CKE1
DDR_A_MA12
DDR_A_MA7
DDR_A_CKE0
DDR_A_MA10DDR_A_MA11
DDR_A_MA6
DDR_A_CS1#
DDR_A_BS#0
DDR_A_WE#DDR_A_CAS#DDR_A_RAS#
DDR_A_BS#1DDR_A_BS#2
DDR_A_MA15
DDR_A_MA0
DDR_A_MA3
DDR_A_MA1DDR_A_MA2
DDR_A_MA4DDR_A_MA5
DDR_B_CS1#DDR_B_CS0#
DDR_B_CKE0DDR_B_CKE1
M_ZNM_ZP
VTT_SENSE_FB
DDR_B_DQS7<9>DDR_B_DQS#7<9>
DDR_B_DQS6<9>
DDR_B_DQS5<9>
DDR_B_DQS4<9>
DDR_B_DQS3<9>
DDR_B_DQS2<9>
DDR_B_DQS1<9>
DDR_B_DQS0<9>
DDR_B_DQS#6<9>
DDR_B_DQS#5<9>
DDR_B_DQS#4<9>
DDR_B_DQS#3<9>
DDR_B_DQS#2<9>
DDR_B_DQS#1<9>
DDR_B_DQS#0<9>
DDR_B_DM[7..0]<9>
DDR_A_DQS7 <8>
DDR_A_DQS6 <8>
DDR_A_DQS5 <8>
DDR_A_DQS4 <8>
DDR_A_DQS3 <8>
DDR_A_DQS2 <8>
DDR_A_DQS1 <8>
DDR_A_DQS0 <8>
DDR_A_DQS#7 <8>
DDR_A_DQS#6 <8>
DDR_A_DQS#5 <8>
DDR_A_DQS#4 <8>
DDR_A_DQS#3 <8>
DDR_A_DQS#2 <8>
DDR_A_DQS#1 <8>
DDR_A_DQS#0 <8>
DDR_A_DM[7..0] <8>
DDR_A_D[63..0] <8>DDR_B_D[63..0]<9>
DDR_B_CLK1 <9>
DDR_B_CLK#2 <9>DDR_B_CLK2 <9>
DDR_B_ODT0 <9>DDR_B_ODT1 <9>
DDR_B_CLK#1 <9>
DDR_B_MA[15..0] <9>
DDR_B_WE# <9>DDR_B_CAS# <9>DDR_B_RAS# <9>
DDR_B_BS#0 <9>
DDR_B_BS#2 <9>DDR_B_BS#1 <9>
DDR_A_CLK1<8>
DDR_A_CLK#2<8>DDR_A_CLK2<8>
DDR_A_CLK#1<8>
DDR_A_ODT1<8>DDR_A_ODT0<8>
DDR_A_BS#2<8>DDR_A_BS#1<8>DDR_A_BS#0<8>
DDR_A_RAS#<8>DDR_A_CAS#<8>DDR_A_WE#<8>
DDR_A_CS1#<8>DDR_A_CS0#<8>
DDR_A_CKE1<8>DDR_A_CKE0<8>
DDR_A_MA[15..0]<8>
DDR_B_CS1# <9>DDR_B_CS0# <9>
DDR_B_CKE1 <9>DDR_B_CKE0 <9>
+CPU_M_VREF
+1.8V
+1.8V
+0.9V
+CPU_M_VREF
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Griffin DDRII MEMORY I/F
Custom
5 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
LAYOUT:PLACE CLOSE TO CPU
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
PLACE CLOSE TO PROCESSOR WITHIN 1.5 INCH
Place between CPU to DDR area(Reserved for EMI)
To re
vers
e SO
DIM
M s
ocke
t (B
otto
m)
To re
vers
e SO
DIM
M s
ocke
t (TO
P)
Processor DDR2 Memory InterfaceON THE BOARD TO DECOUPLING NEAR THE CPU PACKAGE
VDD_VTT_SUS_CPU IS CONNECTED TO THE VDD_VTT_SUS POWERSUPPLY THROUGH THE PACKAGE OR ON THE DIE. IT IS ONLY CONNECTED
KEEP TRACE TO RESISTORS LESS THAN 1" FROM CPU PIN
0.75A
TP47
TP14
C10
60.
1U_0
402_
16V
7K~N
1
2
TP11
C1251.5P 50V F NPO 0402
1
2
C96
0.1U
_040
2_16
V7K
~N
1
2
C94
0.1U
_040
2_16
V7K
~N
1
2
TP16
MEM:CMD/CTRL/CLK
JCPU1B
FOX_PZ6382A-284S-41F_TURION<BOM Strucrure>
VTT1D10VTT2C10VTT3B10VTT4AD10
VTT5 W10VTT6 AC10VTT7 AB10VTT8 AA10VTT9 A10
MA1_ODT1V19 MA1_ODT0U21 MA0_ODT1V22 MA0_ODT0T19
MB1_ODT0 Y26MB0_ODT1 W23MB0_ODT0 W26
RSVD_M2 B18
MB1_CS_L0 U22MB0_CS_L1 W25MB0_CS_L0 V26MA0_CS_L1U19
MA1_CS_L1V20 MA1_CS_L0U20
MA0_CS_L0T20
MA_ADD15K19 MA_ADD14K24 MA_ADD13V24 MA_ADD12K20 MA_ADD11L22 MA_ADD10R21 MA_ADD9K22 MA_ADD8L19 MA_ADD7L21 MA_ADD6M24 MA_ADD5L20 MA_ADD4M22 MA_ADD3M19 MA_ADD2N22 MA_ADD1M20 MA_ADD0N21
MA_BANK2J21 MA_BANK1R23 MA_BANK0R20
MA_RAS_LR19MA_CAS_LT22MA_WE_LT24
MEMZPAF10MEMZNAE10 VTT_SENSE Y10
MEMVREF W17
MA_CLK_H3P19MA_CLK_L3P20
MA_CLK_H2Y16MA_CLK_L2AA16
MA_CLK_H1E16MA_CLK_L1F16
MA_CLK_H0N19MA_CLK_L0N20
MB_CLK_H3 R26MB_CLK_L3 R25
MB_CLK_H2 AF18MB_CLK_L2 AF17
MB_CLK_H1 A17MB_CLK_L1 A18
MB_CLK_H0 P22MB_CLK_L0 R22
MA_CKE0J22MA_CKE1J20 MB_CKE0 J25
MB_CKE1 H26
MB_ADD15 J24MB_ADD14 J23MB_ADD13 W24MB_ADD12 L25MB_ADD11 L26MB_ADD10 T26MB_ADD9 K26MB_ADD8 M26MB_ADD7 L24MB_ADD6 N25MB_ADD5 L23MB_ADD4 N26MB_ADD3 N23MB_ADD2 P26MB_ADD1 N24MB_ADD0 P24
MB_BANK2 J26MB_BANK1 U26MB_BANK0 R24
MB_RAS_L U25MB_CAS_L U24MB_WE_L U23
RSVD_M1H16
C5491.5P 50V F NPO 0402
1
2
C11
90.
1U_0
402_
16V
7K~N
1
2
TP12
C801.5P 50V F NPO 0402
1
2
C97
0.1U
_040
2_16
V7K
~N
1
2
R346 39.2_0603_1%
1 2
TP22
R640_0402_5%1 2
TP8
C81
1000
P_0
402_
50V
7K~N
1
2
TP13
C82
0.1U
_040
2_16
V7K
~N
1
2
C10
50.
1U_0
402_
16V
7K~N
1
2
TP7
TP6
TP9
R651K_0402_1%
12
MEM:DATAJCPU1C
FOX_PZ6382A-284S-41F_TURION<BOM Strucrure>
MB_DATA63AD11 MB_DATA62AF11 MB_DATA61AF14 MB_DATA60AE14 MB_DATA59Y11 MB_DATA58AB11 MB_DATA57AC12 MB_DATA56AF13 MB_DATA55AF15 MB_DATA54AF16 MB_DATA53AC18 MB_DATA52AF19 MB_DATA51AD14 MB_DATA50AC14 MB_DATA49AE18 MB_DATA48AD18 MB_DATA47AD20 MB_DATA46AC20 MB_DATA45AF23 MB_DATA44AF24 MB_DATA43AF20 MB_DATA42AE20 MB_DATA41AD22 MB_DATA40AC22 MB_DATA39AE25 MB_DATA38AD26 MB_DATA37AA25 MB_DATA36AA26 MB_DATA35AE24 MB_DATA34AD24 MB_DATA33AA23 MB_DATA32AA24 MB_DATA31G24 MB_DATA30G23 MB_DATA29D26 MB_DATA28C26 MB_DATA27G26 MB_DATA26G25 MB_DATA25E24 MB_DATA24E23 MB_DATA23C24 MB_DATA22B24 MB_DATA21C20 MB_DATA20B20 MB_DATA19C25 MB_DATA18D24 MB_DATA17A21 MB_DATA16D20 MB_DATA15D18 MB_DATA14C18 MB_DATA13D14 MB_DATA12C14 MB_DATA11A20 MB_DATA10A19 MB_DATA9A16 MB_DATA8A15 MB_DATA7A13 MB_DATA6D12 MB_DATA5E11 MB_DATA4G11 MB_DATA3B14 MB_DATA2A14 MB_DATA1A11 MB_DATA0C11
MA_DATA63 AA12MA_DATA62 AB12MA_DATA61 AA14MA_DATA60 AB14MA_DATA59 W11MA_DATA58 Y12MA_DATA57 AD13MA_DATA56 AB13MA_DATA55 AD15MA_DATA54 AB15MA_DATA53 AB17MA_DATA52 Y17MA_DATA51 Y14MA_DATA50 W14MA_DATA49 W16MA_DATA48 AD17MA_DATA47 Y18MA_DATA46 AD19MA_DATA45 AD21MA_DATA44 AB21MA_DATA43 AB18MA_DATA42 AA18MA_DATA41 AA20MA_DATA40 Y20MA_DATA39 AA22MA_DATA38 Y22MA_DATA37 W21MA_DATA36 W22MA_DATA35 AA21MA_DATA34 AB22MA_DATA33 AB24MA_DATA32 Y24MA_DATA31 H22MA_DATA30 H20MA_DATA29 E22MA_DATA28 E21MA_DATA27 J19MA_DATA26 H24MA_DATA25 F22MA_DATA24 F20MA_DATA23 C23MA_DATA22 B22MA_DATA21 F18MA_DATA20 E18MA_DATA19 E20MA_DATA18 D22MA_DATA17 C19MA_DATA16 G18MA_DATA15 G17MA_DATA14 C17MA_DATA13 F14MA_DATA12 E14MA_DATA11 H17MA_DATA10 E17MA_DATA9 E15MA_DATA8 H15MA_DATA7 E13MA_DATA6 C13MA_DATA5 H12MA_DATA4 H11MA_DATA3 G14MA_DATA2 H14MA_DATA1 F12MA_DATA0 G12
MB_DM7AD12 MB_DM6AC16 MB_DM5AE22 MB_DM4AB26 MB_DM3E25 MB_DM2A22 MB_DM1B16 MB_DM0A12
MB_DQS_H7AF12MB_DQS_L7AE12
MB_DQS_H6AE16MB_DQS_L6AD16
MB_DQS_H5AF21MB_DQS_L5AF22
MB_DQS_H4AC25MB_DQS_L4AC26
MB_DQS_H3F26MB_DQS_L3E26
MB_DQS_H2A24MB_DQS_L2A23
MB_DQS_H1D16MB_DQS_L1C16
MB_DQS_H0C12MB_DQS_L0B12
MA_DM7 Y13MA_DM6 AB16MA_DM5 Y19MA_DM4 AC24MA_DM3 F24MA_DM2 E19MA_DM1 C15MA_DM0 E12
MA_DQS_H7 W12MA_DQS_L7 W13
MA_DQS_H6 Y15MA_DQS_L6 W15
MA_DQS_H5 AB19MA_DQS_L5 AB20
MA_DQS_H4 AD23MA_DQS_L4 AC23
MA_DQS_H3 G22MA_DQS_L3 G21
MA_DQS_H2 C22MA_DQS_L2 C21
MA_DQS_H1 G16MA_DQS_L1 G15
MA_DQS_H0 G13MA_DQS_L0 H13
R353 39.2_0603_1%
1 2
R661K_0402_1%
12
TP15
C5201.5P 50V F NPO 0402
1
2C
118
0.1U
_040
2_16
V7K
~N
1
2
TP5
TP10
C13
20.
1U_0
402_
16V
7K~N
1
2
C10
40.
1U_0
402_
16V
7K~N
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CPU_ALL_PWROK
CPU_LDTSTOP#
SYSON#
CPU_TEST12_SCANSHIFTENB
CPU_TDI
CPU_CLKIN_SC_P
CPU_TEST25_L_BYPASSCLK_L
CPU_TRST#
CPU_TEST16_BP2CPU_TEST19_PLLTEST0
CPU_TEST14_BP0
CPU_TEST24_SCANCLK1
CPU_TCK
CPU_DBRDY
CPU_TEST18_PLLTEST1
CPU_TEST15_BP1
CPU_LDTSTOP#
CPU_TEST17_BP3
CPU_TEST21_SCANEN
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_HTREF0
CPU_HT_RESET#
CPU_DBREQ#
CPU_TEST25_H_BYPASSCLK_H
CPU_TMS
CPU_TEST29_H_FBCLKOUT_P
CPU_SIC
CPU_HTREF1
CPU_TEST20_SCANCLK2
CPU_TDO
+VDDA_CPU
THERM#
THERMDA_CPU
EC_SMB_DA2
EC_SMB_CK2
THERMDC_CPU
CPU_TEST29_L_FBCLKOUT_N
CPU_TEST8_DIG_T
CPU_TEST10_ANALOGOUTCPU_TEST7_ANALOG_T
CPU_TEST28_L_PLLCHRZ_NCPU_TEST28_H_PLLCHRZ_P
CPU_TEST27_SINGLECHAIN
CPU_TEST6_DIECRACKMON
CPU_SID
THERMDA_CPUTHERMDC_CPU
CPU_THERMTRIP#_RCPU_PROCHOT#_1.8CPU_MEMHOT#_1.8V
CPU_THERMTRIP#_R
CPU_ALL_PWROK
CPU_LDT_REQ#_CPU
SMB_ALERT#
CPU_ALERT#
CPU_TEST19_PLLTEST0CPU_TEST18_PLLTEST1
CPU_TEST12_SCANSHIFTENB
CPU_TEST24_SCANCLK1
CPU_TEST15_BP1
CPU_TEST20_SCANCLK2
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST14_BP0
CPU_TEST27_SINGLECHAIN
CPU_LDT_REQ#_CPU
CPU_SVD
CPU_HT_RESET#
CPU_PROCHOT#_1.8
CPU_ALERT# SMB_ALERT#
CPU_SVC
CPU_THERMTRIP#_R
CPU_MEMHOT#_1.8V
CPU_PROCHOT#_1.8
CPU_SVD
CPU_SVC
+VDDA_CPU
CPU_CLKIN_SC_NCPU_ALL_PWROK
CPU_LDTSTOP#
CPU_HT_RESET#
CPU_LDT_REQ#_CPU
CPU_PWRGD_SVID_REG
CPU_DBRDY
CPU_TDO
CPU_TMSCPU_TCK
CPU_TDICPU_TRST#
CPU_DBREQ#
HDT_RST#LDT_RST#
CPU_SID
CPU_SIC
CPU_PROCHOT#_1.8
CPU_PWRGD<17>
LDT_STOP#<11,17>
LDT_RST#<17>
H_THERMTRIP# <18>CLK_CPUCLK0_L<14>
CLK_CPUCLK0_H<14>
CPU_VDD0_RUN_FB_L<40>CPU_VDD0_RUN_FB_H<40>
SYSON#<32,39>
EC_SMB_CK2<28>
EC_SMB_DA2<28>
CPU_VDD1_RUN_FB_L<40>CPU_VDD1_RUN_FB_H<40>
CPU_LDT_REQ#<11,17>
CPU_VDDIO_FB_H <37>CPU_VDDIO_FB_L <37>
CPU_VDDNB_RUN_FB_H <40>CPU_VDDNB_RUN_FB_L <40>
CPU_SVC <40>CPU_SVD <40>
CPU_PWRGD_SVID_REG <40>
SMB_ALERT# <18>
CPU_PROCHOT# <17>
SB_PWRGD <11,18,28>
EC_SMB_DA1 <28,34>
EC_SMB_CK1 <28,34>
+3VS +2.5VDDA
+3VALW
+1.8V
+1.2V_HT
+2.5VDDA
+1.8V
+3VS
+3VS
+1.8V
+1.8V
+1.8V
+1.8VS+1.8V
+1.8V
+3VS
+1.8V
+1.8V
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Griffin CTRL & ADM1032Custom
6 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
LAYOUT: ROUTE VDDA TRACE APPROX.50 mils WIDE (USE 2x25 mil TRACES TOEXIT BALL FIELD) AND 500 mils LONG.
place them to CPU within 1.5"
Thermal SensorADM1032
SMBus Address: 1001110X (b)
as short as possibleroute as differential
testpoint under package
0.25A
VID BYPASS CIRCUIT
HDT Connector
NOTE: HDT TERMINATION IS REQUIRED FOR REV. Ax SILICON ONLY.
FDV301N, the Vgs is:min = 0.65VTyp = 0.85VMax = 1.5V
EC is PU to 5VALW
2.09V for Gate
R83 1K_0402_5%
12
R35
822
0_04
02_5
%@
12
TP2
R145 0_0402_5%
1 2
R190
34.8K_0402_1%~N
12
R86 1K_0402_5%
12
R123 300_0402_5%
1 2
L8
LQG21F4R7N00_0805 1 2
R112470_0402_5%
12
R67 44.2_0402_1%
1 2
C355 0.1U_0402_16V4Z
1 2
R59 300_0402_5%
1 2
R34710K_0402_5%@1
2
R35
922
0_04
02_5
%@
12
TP19
C213
4.7U_0805_6.3V6K~N
1
2
R35110K_0402_5%
12
C5252200P_0402_50V7K
1
2
TP24TP26
C2600.01U_0402_16V7K
1
2
R352 300_0402_5%@1 2
TP30
TP23
TP29
R355 300_0402_5%
12
R35
722
0_04
02_5
%@
12
TP28
R7010K_0402_5%@
12
R91 0_0402_5%
1 2
R102 0_0805_5%
12
R690_0402_5%@
1 2
R72 300_0402_5%@1 2
R68 44.2_0402_1%
1 2
R354 300_0402_5%
12
C2140.22U_0603_10V7K
1
2
R1030_0805_5%
@
12
R76
10K_
0402
_5%
@
12
R82 300_0402_5%@1 2
R73 300_0402_5%@1 2
R193
390_0402_5%12
Q9
MMBT3904_NL_SOT23-3@
2
3 1
JCPU1D
FOX_PZ6382A-284S-41F_TURIONCONN@
VDDA1F8VDDA2F9
RESET_LB7PWROKA7LDTSTOP_LF10
SICAF4SIDAF5
HT_REF1P6 HT_REF0R6
VDD0_FB_HF6VDD0_FB_LE6 VDDIO_FB_H W9
VDDIO_FB_L Y9
THERMTRIP_L AF6PROCHOT_L AC7
RSVD2A5
LDTREQ_LC6
SVC A6SVD A4
RSVD6 C5RSVD4B5
RSVD1A3
CLKIN_HA9CLKIN_LA8
DBRDYG10TMSAA9TCKAC9TRST_LAD9TDIAF9
DBREQ_L E10
TDO AE9
TEST25_HE9TEST25_LE8
TEST19G9 TEST18H10
RSVD8 AA7
TEST9C2
TEST17 D7TEST16 E7TEST15 F7TEST14 C7
TEST12AC8
TEST7 C3
TEST6AA6
THERMDC W7THERMDA W8
VDD1_FB_HY6VDD1_FB_LAB6
TEST29_H C9TEST29_L C8
TEST24AE7
TEST23AD7
TEST22AE8
TEST21AB8TEST20AF7
TEST28_H J7TEST28_L H8
TEST27AF8
ALERT_LAE6
TEST10 K8
TEST8 C4
RSVD3B3
RSVD5C1
VDDNB_FB_H H6VDDNB_FB_L G6
RSVD7 D5
KEY2 W18
MEMHOT_L AA8
RSVD10 H18RSVD9 H19
KEY1 M11
TP46
TP1
C5553900P_0402_50V7K 1 2
R348 300_0402_5%@1 2
R365169_0402_1%
12
R75
1K_0
402_
5%
12
U23
NC7SZ08P5X_NL_SC70-5@
B 2
A 1Y4
P5
G3
R77 0_0402_5%
1 2
R349 300_0402_5%@1 2
C5240.1U_0402_16V7K~N
1
2
TP17
C2521U_0603_10V6K1
2
C276 0.01U_0402_16V7K@1 2
TP25
R90 300_0402_5%
1 2
C188 0.01U_0402_16V7K@1 2
TP31
G
DS
Q25 FDV301N_NL_SOT23-3
2
13
TP4
R371 0_0402_5%
1 2
SAMTEC_ASP-68200-07
JDB1
CONN@
2468
101214161820222423
21191715131197531
26
R71 300_0402_5%@ 1 2
+C253
150U_D2_6.3VM
1
2
C557 0.01U_0402_16V7K@1 2
R74 300_0402_5%
1 2
R58 300_0402_5%@1 2
C122 0.01U_0402_16V7K@1 2
C189
3300P_0402_50V7K
1
2
TP18
R189
20K_0402_5%
12
R35
622
0_04
02_5
%@
12
G
D
S
Q10SSM3K7002FU_SC70-3@
21
3
R81 0_0402_5%
1 2
R367 300_0402_5%
1 2
TP32
U24
ADM1032ARMZ MSOP 8P
VDD1 1
ALERT# 6
THERM# 4
GND 5
D+2
D-3
SCLK8
SDATA7
Q42
MMBT3904_NL_SOT23-3@
2
3 1
TP21
TP20
R57 300_0402_5%
12
C556 3900P_0402_50V7K 1 2
R350 300_0402_5%
1 2
J12OPEN PADS
12
R345 0_0402_5%1 2
R36
030
0_04
02_5
%
12
TP45
G
DS
Q27 FDV301N_NL_SOT23-3
2
13
TP44
TP27
TP3
U6
G914E_SOT23-5
IN1
GND2
SHDN3 BYP 4
OUT 5
C2511U_0603_10V6K
1
2
Q43
MMBT3904_NL_SOT23-3
2
3 1
TP43
R217
390_0402_5%12
R366 0_0402_5%
1 2
R36
14.
7K_0
402_
5%
@12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCC_CORE0 +VCC_CORE1
+1.8V
+1.8V
+VDDNB
+0.9V
+1.8V
+1.8V
+1.8V
+1.8V +1.8V
+0.9V
+0.9V
+VDDNB
+VCC_CORE0
+VCC_CORE0
+VCC_CORE0+VCC_CORE1
+VCC_CORE1
+VCC_CORE1
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Griffin PWR & GNDCustom
7 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
3A
2A
18A 18A
Under CPU Socket
Near CPU Socket
VDD(+CPU_CORE) decoupling.
A: Add C165 and C176to follow AMD Layoutreview recommand forEMI
Between CPU Socket and DIMM
180PF Qt'y follow the distance betweenCPU socket and DIMM0. <2.5inch>
VTT decoupling.
VDDIO decoupling.+CPU_CORE_NB decoupling.
C: Change to NBO CAP
C: Change to NBO CAP
Under CPU Socket
Near CPU Socket Right side.
Near CPU Socket Left side.
Near Power Supply
C79180P_0402_50V8J
1
2
C95
180P_0402_50V8J
1
2
C864.7U_0805_10V4Z~N
1
2C451000P_0402_25V8J
1
2
+ C90220U_Y_4VM@
1
2C78180P_0402_50V8J
1
2
C1000.01U_0402_25V4Z
1
2
C146
180P_0402_50V8J
1
2
C474.7U_0805_10V4Z~N
1
2
JCPU1E
FOX_PZ6382A-284S-41F_TURION<BOM Strucrure>
VDD1_25 AC4VDD1_26 AD2
VDD0_1G4VDD0_2H2VDD0_3J9VDD0_4J11VDD0_5J13
VDD0_7K6VDD0_8K10VDD0_9K12VDD0_10K14VDD0_11L4VDD0_12L7VDD0_13L9VDD0_14L11VDD0_15L13
VDD0_17M2VDD0_18M6VDD0_19M8VDD0_20M10VDD0_21N7VDD0_22N9VDD0_23N11
VDD1_1 P8VDD1_2 P10VDD1_3 R4VDD1_4 R7VDD1_5 R9VDD1_6 R11VDD1_7 T2VDD1_8 T6VDD1_9 T8
VDD1_10 T10VDD1_11 T12VDD1_12 T14VDD1_13 U7VDD1_14 U9VDD1_15 U11VDD1_16 U13
VDD1_18 V6VDD1_19 V8VDD1_20 V10VDD1_21 V12VDD1_22 V14VDD1_23 W4VDD1_24 Y2
VDD0_6J15
VDDNB_1K16
VDD0_16L15
VDDNB_2M16VDDNB_3P16VDDNB_4T16
VDD1_17 U15
VDDNB_5V16
VDDIO1H25VDDIO2J17VDDIO3K18VDDIO4K21VDDIO5K23VDDIO6K25VDDIO7L17VDDIO8M18VDDIO9M21VDDIO10M23VDDIO11M25VDDIO12N17 VDDIO13 P18VDDIO14 P21VDDIO15 P23VDDIO16 P25VDDIO17 R17VDDIO18 T18VDDIO19 T21VDDIO20 T23VDDIO21 T25VDDIO22 U17VDDIO23 V18VDDIO24 V21VDDIO25 V23VDDIO26 V25VDDIO27 Y25
C2154.7U_0805_10V4Z~N
1
2
C9822U_0805_6.3V6M
1
2
C12322U_0805_6.3V6M
1
2
C12722U_0805_6.3V6M
1
2
C5541000P_0402_25V8J
1
2
C480.22U_0603_16V4Z
1
2
C890.22U_0603_16V4Z
1
2
C121180P_0402_50V8J
1
2
C84180P_0402_50V8J
1
2
C93
0.22U_0603_16V4Z
1
2
C10222U_0805_6.3V6M
1
2
C5510.22U_0603_16V4Z
1
2
C103
0.22U_0603_16V4Z
1
2
C117180P_0402_50V8J
1
2
C1300.22U_0603_16V4Z
1
2
C460.22U_0603_16V4Z
1
2
C874.7U_0805_10V4Z~N
1
2
C2164.7U_0805_10V4Z~N
1
2
C1080.01U_0402_25V4Z
1
2
+ C120330U_X_2VM_R6M
1
2
C10922U_0805_6.3V6M
1
2
C9922U_0805_6.3V6M
1
2
C12422U_0805_6.3V6M
1
2
C5500.22U_0603_16V4Z
1
2
C5531000P_0402_25V8J
1
2
C559180P_0402_50V8J
1
2
+ C50220U_Y_4VM
1
2
C494.7U_0805_10V4Z~N
1
2
C1120.22U_0603_16V4Z
1
2
C830.01U_0402_25V4Z
1
2
C92180P_0402_50V8J
1
2
C11122U_0805_6.3V6M
1
2
C1310.22U_0603_16V4Z
1
2
C552180P_0402_50V8J
1
2
C11422U_0805_6.3V6M
1
2
C11322U_0805_6.3V6M
1
2
JCPU1F
FOX_PZ6382A-284S-41F_TURION<BOM Strucrure>
VSS1AA4VSS2AA11VSS3AA13VSS4AA15VSS5AA17VSS6AA19VSS7AB2VSS8AB7VSS9AB9VSS10AB23VSS11AB25VSS12AC11VSS13AC13VSS14AC15VSS15AC17VSS16AC19VSS17AC21VSS18AD6VSS19AD8VSS20AD25VSS21AE11VSS22AE13VSS23AE15VSS24AE17VSS25AE19VSS26AE21VSS27AE23VSS28B4VSS29B6VSS30B8VSS31B9VSS32B11VSS33B13VSS34B15VSS35B17VSS36B19VSS37B21VSS38B23VSS39B25VSS40D6VSS41D8VSS42D9VSS43D11VSS44D13VSS45D15VSS46D17VSS47D19VSS48D21VSS49D23VSS50D25VSS51E4VSS52F2VSS53F11VSS54F13VSS55F15VSS56F17VSS57F19VSS58F21VSS59F23VSS60F25VSS61H7VSS62H9VSS63H21VSS64H23VSS65J4
VSS66 J6VSS67 J8VSS68 J10VSS69 J12VSS70 J14VSS71 J16VSS72 J18VSS73 K2VSS74 K7VSS75 K9VSS76 K11VSS77 K13VSS78 K15VSS79 K17VSS80 L6VSS81 L8VSS82 L10VSS83 L12VSS84 L14VSS85 L16VSS86 L18VSS87 M7VSS88 M9VSS89 AC6VSS90 M17VSS91 N4VSS92 N8VSS93 N10VSS94 N16VSS95 N18VSS96 P2VSS97 P7VSS98 P9VSS99 P11
VSS100 P17VSS101 R8VSS102 R10VSS103 R16VSS104 R18VSS105 T7VSS106 T9VSS107 T11VSS108 T13VSS109 T15VSS110 T17VSS111 U4VSS112 U6VSS113 U8VSS114 U10VSS115 U12VSS116 U14VSS117 U16VSS118 U18VSS119 V2VSS120 V7VSS121 V9VSS122 V11VSS123 V13VSS124 V15VSS125 V17VSS126 W6VSS127 Y21VSS128 Y23VSS129 N6
+ C75330U_X_2VM_R6M
1
2
C10122U_0805_6.3V6M
1
2
C85180P_0402_50V8J
1
2
C12622U_0805_6.3V6M
1
2
C771000P_0402_25V8J
1
2
C1284.7U_0805_10V4Z~N
1
2
C1160.01U_0402_25V4Z
1
2
+ C91330U_X_2VM_R6M
1
2
C1294.7U_0805_10V4Z~N
1
2
C880.22U_0603_16V4Z
1
2
C760.22U_0603_16V4Z
1
2
C11022U_0805_6.3V6M
1
2
+ C107330U_X_2VM_R6M
1
2
C115180P_0402_50V8J
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_BS#0
DDR_A_D26
DDR_A_D29
DDR_A_D27DDR_A_D30
DDR_A_D33
DDR_A_D31
DDR_A_D32
DDR_A_D28
DDR_A_D34DDR_A_D35
DDR_A_D38
DDR_A_D36
DDR_A_D39
DDR_A_D37
DDR_A_D41
DDR_A_D42
DDR_A_D44DDR_A_D40
DDR_A_D43 DDR_A_D47
DDR_A_D48
DDR_A_D45
DDR_A_D46
DDR_A_D49 DDR_A_D53
DDR_A_D51 DDR_A_D55DDR_A_D50
DDR_A_D52
DDR_A_D56
DDR_A_D54
DDR_A_D59
DDR_A_D57
DDR_A_D58
DDR_A_D61
DDR_A_D63
DDR_A_D60
DDR_A_D3
DDR_A_D8
DDR_A_D6DDR_A_D7
DDR_A_D5
DDR_A_D14
DDR_A_D9
DDR_A_D11DDR_A_D10
DDR_A_D13
DDR_A_D16
DDR_A_D15
DDR_A_D12
DDR_A_D17DDR_A_D20
DDR_A_D18 DDR_A_D22DDR_A_D19
DDR_A_D24
DDR_A_D21
DDR_A_D23
DDR_A_BS#2
DDR_A_BS#1
DDR_A_D25
DDR_A_D62
DDR_A_DM7
DDR_A_DM2
DDR_A_DM4
DDR_A_DM3
DDR_A_DM1
DDR_A_DM0
DDR_A_DM6
DDR_A_DM5
DDR_A_MA4
DDR_A_D0
DDR_A_D2
DDR_A_D1
DDR_A_D4
DDR_A_MA11
DDR_A_MA10
DDR_A_MA12DDR_A_MA9
DDR_A_MA6DDR_A_MA8
DDR_A_MA5
DDR_A_MA7
DDR_A_MA3DDR_A_MA0
DDR_A_MA13
DDR_A_MA15
DDR_A_MA2DDR_A_MA1
DDR_A_MA14
DDR_A_DQS2
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DQS0
DDR_A_DQS#1
DDR_A_DQS5
DDR_A_DQS7
DDR_A_DQS3
DDR_A_DQS6
DDR_A_DQS#7
DDR_A_DQS#4
DDR_A_DQS#2
DDR_A_DQS#6
DDR_A_DQS#3
DDR_A_DQS1
DDR_A_DQS#5
DDR_A_ODT1
DDR_A_CKE0
DDR_A_CS1#
DDR_A_RAS#DDR_A_WE#
DDR_A_CKE1
DDR_A_CAS#
DDR_A_CS0#
DDR_A_CLK#2
DDR_A_ODT0
DDR_A_CLK#1DDR_A_CLK1
DDR_A_CLK2
SMB_CK_DAT0SMB_CK_CLK0
DDR_A_MA10DDR_A_BS#0
DDR_A_D[0..63]
DDR_A_MA[0..15]
DDR_A_DM[0..7]
DDR_A_DQS[0..7]
DDR_A_DQS#[0..7]
DDR_A_MA4
DDR_A_CS1#DDR_A_ODT1
DDR_A_MA0
DDR_A_MA6
DDR_A_ODT0DDR_A_MA13
DDR_A_CS0#
DDR_A_MA2
DDR_A_RAS#
DDR_A_BS#1
DDR_A_CKE1
DDR_A_MA14
DDR_A_MA15
DDR_A_MA7
DDR_A_MA11
DDR_A_CAS#DDR_A_WE#
DDR_A_MA1
DDR_A_MA9DDR_A_MA8
DDR_A_MA3
DDR_A_BS#2DDR_A_CKE0
DDR_A_MA12
DDR_A_MA5
DDR_A_MA[0..15]<5>
DDR_A_D[0..63]<5>
DDR_A_DQS[0..7]<5>
DDR_A_DM[0..7]<5>
DDR_A_DQS#[0..7]<5>
DDR_A_CLK1 <5>DDR_A_CLK#1 <5>
DDR_A_CKE0<5>
DDR_A_BS#2<5>
DDR_A_BS#0<5>DDR_A_WE#<5>
DDR_A_CAS#<5>DDR_A_CS1#<5>
DDR_A_ODT1<5>
DDR_A_CLK2 <5>DDR_A_CLK#2 <5>
DDR_A_CS0# <5>
DDR_A_ODT0 <5>
DDR_A_RAS# <5>DDR_A_BS#1 <5>
DDR_A_CKE1 <5>
SMB_CK_CLK0<9,14,18>SMB_CK_DAT0<9,14,18>
+1.8V+DIMM_VREF+1.8V+1.8V
+3VS
+1.8V
+0.9V
+0.9V
+0.9V
+0.9V
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
DDR2 SODIMM-I Socket
Custom
8 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
2007-01-17 Add
PLACE CLOSE TO SO-DIMM1 AS POSSIBLE
REVERSE TYPELOW SLOT
C21
7
4.7U
_080
5_6.
3V6K
~N
1
2
C169
0.1U_0402_16V7K~N
1
2
R60 0_0402_5%
12
C148
0.1U_0402_16V7K~N
1
2
RP6
47_0804_8P4R_5%
18273645
R61 0_0402_5%12
C150
0.1U_0402_16V7K~N
1
2
C17
0
0.1U
_040
2_16
V7K~
N
1
2
C15
1
0.1U
_040
2_16
V7K~
N
1
2
C152
0.1U_0402_16V7K~N
1
2
C190
0.1U_0402_16V7K~N
1
2
C29
910
00P_
0402
_50V
7K~N
1
2C
179
0.1U_0402_16V7K~N
1
2
C193
0.1U_0402_16V7K~N
1
2
C15
4
0.1U
_040
2_16
V7K~
N
1
2
RP10
47_0804_8P4R_5%
18273645
RP14
47_0804_8P4R_5%
18273645
C13
3
4.7U
_080
5_6.
3V6K
~N
1
2
RP5
47_0804_8P4R_5%
18273645
C14
1
0.1U
_040
2_16
V7K~
N
1
2
C136
0.1U_0402_16V7K~N
1
2
C28
10.
1U_0
402_
16V7
K~N
1
2
C13
8
0.1U
_040
2_16
V7K~
N
1
2
R1521K_0402_1%
12
RP2
47_0804_8P4R_5%
18273645
C19
4
0.1U
_040
2_16
V7K~
N
1
2
C137
0.1U_0402_16V7K~N
1
2
JDIM1
FOX_ASOA426-M2RN-7FCONN@
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144DQS5# 146
DQS5 148VSS 150
DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SA0 198SA1 200
C134
0.1U_0402_16V7K~N
1
2
RP9
47_0804_8P4R_5%
18273645
C135
0.1U_0402_16V7K~N
1
2C192
0.1U_0402_16V7K~N
1
2
C149
0.1U_0402_16V7K~N
1
2C191
0.1U_0402_16V7K~N
1
2
RP1
47_0804_8P4R_5%
18273645
C17
1
0.1U
_040
2_16
V7K~
N
1
2
R1351K_0402_1%
12
+
C147
330U_D
2E_2.5VM
@
1
2
C14
2
0.1U
_040
2_16
V7K~
N
1
2
C21
8
0.1U
_040
2_16
V7K~
N
1
2
RP13
47_0804_8P4R_5%
18273645
C15
3
0.1U
_040
2_16
V7K~
N
1
2
C168
0.1U_0402_16V7K~N
1
2
C29
80.
1U_0
402_
16V7
K~N
1
2
C13
9
0.1U
_040
2_16
V7K~
N
1
2
C19
5
0.1U
_040
2_16
V7K~
N
1
2
C140
0.1U_0402_16V7K~N
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_BS#0
DDR_B_D26
DDR_B_D29
DDR_B_D27DDR_B_D30
DDR_B_D33
DDR_B_D31
DDR_B_D32
DDR_B_D28
DDR_B_D34DDR_B_D35
DDR_B_D38
DDR_B_D36
DDR_B_D39
DDR_B_D37
DDR_B_D41
DDR_B_D42
DDR_B_D44DDR_B_D40
DDR_B_D43 DDR_B_D47
DDR_B_D48
DDR_B_D45
DDR_B_D46
DDR_B_D49 DDR_B_D53
DDR_B_D51 DDR_B_D55DDR_B_D50
DDR_B_D52
DDR_B_D56
DDR_B_D54
DDR_B_D59
DDR_B_D57
DDR_B_D58
DDR_B_D61
DDR_B_D63
DDR_B_D60
DDR_B_D3
DDR_B_D8
DDR_B_D6DDR_B_D7
DDR_B_D5
DDR_B_D14
DDR_B_D9
DDR_B_D11DDR_B_D10
DDR_B_D13
DDR_B_D16
DDR_B_D15
DDR_B_D12
DDR_B_D17DDR_B_D20
DDR_B_D18 DDR_B_D22DDR_B_D19
DDR_B_D24
DDR_B_D21
DDR_B_D23
DDR_B_BS#2
DDR_B_BS#1
DDR_B_D25
DDR_B_D62
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_DM3
DDR_B_DM1
DDR_B_DM0
DDR_B_DM6
DDR_B_DM5
DDR_B_MA4
DDR_B_D0
DDR_B_D2
DDR_B_D1
DDR_B_D4
DDR_B_MA11
DDR_B_MA10
DDR_B_MA12DDR_B_MA9
DDR_B_MA6DDR_B_MA8
DDR_B_MA5
DDR_B_MA7
DDR_B_MA3DDR_B_MA0
DDR_B_MA13
DDR_B_MA15
DDR_B_MA2DDR_B_MA1
DDR_B_MA14
DDR_B_DQS2
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DQS0
DDR_B_DQS#1
DDR_B_DQS5
DDR_B_DQS7
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS#7
DDR_B_DQS#4
DDR_B_DQS#2
DDR_B_DQS#6
DDR_B_DQS#3
DDR_B_DQS1
DDR_B_DQS#5
DDR_B_ODT1
DDR_B_CKE0
DDR_B_CS1#
DDR_B_RAS#DDR_B_WE#
DDR_B_CKE1
DDR_B_CAS#
DDR_B_CS0#
DDR_B_CLK#2
DDR_B_ODT0
DDR_B_CLK#1DDR_B_CLK1
DDR_B_CLK2
SMB_CK_DAT0SMB_CK_CLK0
DDR_B_D[0..63]
DDR_B_MA[0..15]
DDR_B_DM[0..7]
DDR_B_DQS[0..7]
DDR_B_DQS#[0..7]
DDR_B_ODT1
DDR_B_CKE0DDR_B_BS#2
DDR_B_CS1#
DDR_B_MA3
DDR_B_MA12
DDR_B_CAS#
DDR_B_MA11
DDR_B_MA15
DDR_B_MA14
DDR_B_CKE1
DDR_B_MA7
DDR_B_MA4
DDR_B_MA6
DDR_B_MA0
DDR_B_BS#1
DDR_B_MA2
DDR_B_MA13DDR_B_ODT0
DDR_B_BS#0
DDR_B_MA10
DDR_B_WE#
DDR_B_MA5
DDR_B_MA1
DDR_B_MA9
DDR_B_MA8
DDR_B_RAS#
DDR_B_CS0#
DDR_B_MA[0..15]<5>
DDR_B_D[0..63]<5>
DDR_B_DQS[0..7]<5>
DDR_B_DM[0..7]<5>
DDR_B_DQS#[0..7]<5>
DDR_B_CLK1 <5>DDR_B_CLK#1 <5>
DDR_B_CKE0<5>
DDR_B_BS#2<5>
DDR_B_BS#0<5>DDR_B_WE#<5>
DDR_B_CAS#<5>DDR_B_CS1#<5>
DDR_B_ODT1<5>
DDR_B_CLK2 <5>DDR_B_CLK#2 <5>
DDR_B_CS0# <5>
DDR_B_ODT0 <5>
DDR_B_RAS# <5>DDR_B_BS#1 <5>
DDR_B_CKE1 <5>
SMB_CK_CLK0<8,14,18>SMB_CK_DAT0<8,14,18>
+DIMM_VREF+1.8V+1.8V
+3VS
+0.9V
+1.8V
+0.9V
+0.9V
+3VS
+1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
DDR2 SODIMM-II Socket
Custom
9 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
Layout Note:Place one cap close to every 2 pullup resistors terminated to +0.9V
PLACE CLOSE TO SO-DIMM2 AS POSSIBLE
REVERSE TYPETOP SLOT
RP3
47_0804_8P4R_5%
1 82 73 64 5
C22
1
0.1U
_040
2_16
V7K~
N
1
2
C178
0.1U_0402_16V7K~N
1
2
RP4
47_0804_8P4R_5%
1 82 73 64 5
C17
6
0.1U
_040
2_16
V7K~
N
1
2
C14
4
0.1U
_040
2_16
V7K~
N
1
2
C29
710
00P_
0402
_50V
7K~N
1
2
C19
7
0.1U
_040
2_16
V7K~
N
1
2
R63 4.7K_0402_5%1 2
C17
4
0.1U
_040
2_16
V7K~
N
1
2
C225
0.1U_0402_16V7K~N
1
2C224
0.1U_0402_16V7K~N
1
2 C160
0.1U_0402_16V7K~N
1
2 C177
0.1U_0402_16V7K~N
1
2
C175
0.1U_0402_16V7K~N
1
2C234
0.1U_0402_16V7K~N
1
2
RP12
47_0804_8P4R_5%
1 82 73 64 5
C158
0.1U_0402_16V7K~N
1
2
RP16
47_0804_8P4R_5%
1 82 73 64 5
C17
3
0.1U
_040
2_16
V7K~
N
1
2
C159
0.1U_0402_16V7K~N
1
2
C22
2
4.7U
_080
5_6.
3V6K
~N
1
2
C220
0.1U_0402_16V7K~N
1
2
C17
2
0.1U
_040
2_16
V7K~
N
1
2
C219
0.1U_0402_16V7K~N
1
2
RP8
47_0804_8P4R_5%
1 82 73 64 5
C14
5
0.1U
_040
2_16
V7K~
N
1
2
JDIM2
FOX_AS0A426-NARN-7F~NCONN@
VREF1VSS3DQ05DQ17VSS9DQS0#11DQS013VSS15DQ217DQ319VSS21DQ823DQ925VSS27DQS1#29DQS131VSS33DQ1035DQ1137VSS39
VSS41DQ1643DQ1745VSS47DQS2#49DQS251VSS53DQ1855DQ1957VSS59DQ2461DQ2563VSS65DM367NC69VSS71DQ2673DQ2775VSS77CKE079VDD81NC83BA285VDD87A1289A991A893VDD95A597A399A1101VDD103A10/AP105BA0107WE#109VDD111CAS#113NC/S1#115VDD117NC/ODT1119VSS121DQ32123DQ33125VSS127DQS4#129DQS4131VSS133DQ34135DQ35137VSS139DQ40141DQ41143
VSS 2DQ4 4DQ5 6VSS 8DM0 10VSS 12DQ6 14DQ7 16VSS 18
DQ12 20DQ13 22
VSS 24DM1 26VSS 28CK0 30
CK0# 32VSS 34
DQ14 36DQ15 38
VSS 40
VSS 42DQ20 44DQ21 46
VSS 48NC 50
DM2 52VSS 54
DQ22 56DQ23 58
VSS 60DQ28 62DQ29 64
VSS 66DQS3# 68
DQS3 70VSS 72
DQ30 74DQ31 76
VSS 78NC/CKE1 80
VDD 82NC/A15 84NC/A14 86
VDD 88A11 90
A7 92A6 94
VDD 96A4 98A2 100A0 102
VDD 104BA1 106
RAS# 108S0# 110
VDD 112ODT0 114
NC/A13 116VDD 118
NC 120VSS 122
DQ36 124DQ37 126
VSS 128DM4 130VSS 132
DQ38 134DQ39 136
VSS 138DQ44 140DQ45 142
VSS 144VSS145DM5147VSS149DQ42151DQ43153VSS155DQ48157DQ49159VSS161NC,TEST163VSS165DQS6#167DQS6169VSS171DQ50173DQ51175VSS177DQ56179DQ57181VSS183DM7185VSS187DQ58189DQ59191VSS193SDA195SCL197VDDSPD199
DQS5# 146DQS5 148
VSS 150DQ46 152DQ47 154
VSS 156DQ52 158DQ53 160
VSS 162CK1 164
CK1# 166VSS 168DM6 170VSS 172
DQ54 174DQ55 176
VSS 178DQ60 180DQ61 182
VSS 184DQS7# 186
DQS7 188VSS 190
DQ62 192DQ63 194
VSS 196SAO 198SA1 200
RP11
47_0804_8P4R_5%
1 82 73 64 5
C198
0.1U_0402_16V7K~N
1
2
RP7
47_0804_8P4R_5%
1 82 73 64 5
C15
7
0.1U
_040
2_16
V7K~
N
1
2
C15
5
0.1U
_040
2_16
V7K~
N
1
2
R62 0_0402_5%12
C196
0.1U_0402_16V7K~N
1
2 C199
0.1U_0402_16V7K~N
1
2
RP15
47_0804_8P4R_5%
1 82 73 64 5
C235
0.1U_0402_16V7K~N
1
2
+
C254
330U_D
2E_2.5VM
1
2
C15
6
0.1U
_040
2_16
V7K~
N
1
2
C22
3
0.1U
_040
2_16
V7K~
N
1
2
C161
0.1U_0402_16V7K~N
1
2
C14
3
4.7U
_080
5_6.
3V6K
~N
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_CADIN[0..15]
H_CADIP[0..15]
H_CADOP[0..15]
H_CADON[0..15]
H_CTLIP1H_CTLIN1
HT_TXCALPHT_TXCALN
SB_RX0PSB_RX0NSB_RX1PSB_RX1N
SB_TX0P_C
SB_TX1P_CSB_TX0N_C
SB_TX1N_C
SB_TX0PSB_TX0NSB_TX1PSB_TX1N
H_CADIN5H_CADIP5H_CADIN4H_CADIP4H_CADIN3
H_CADIP0
H_CADIN1H_CADIP2
H_CADIP1
H_CADIN2H_CADIP3
H_CADIN15H_CADIP15H_CADIN14H_CADIP14
H_CADIN0
H_CADIN13H_CADIP13H_CADIN12H_CADIP12
H_CADIP11H_CADIN11
H_CADIN10H_CADIP10H_CADIN9H_CADIP9H_CADIN8H_CADIP8
H_CADIN7H_CADIP7H_CADIN6H_CADIP6
H_CLKIN1H_CLKIP1
H_CTLIN0
H_CLKIN0H_CLKIP0
H_CTLIP0
H_CLKON1H_CLKOP1
H_CTLOP0H_CTLON0
SB_RX2PSB_RX2NSB_RX3PSB_RX3N
SB_TX2P_CSB_TX2N_C
SB_TX2PSB_TX2N
SB_TX3P_C SB_TX3PSB_TX3N_C SB_TX3N
PCE_PCALPCE_NCAL
H_CLKOP0H_CLKON0
H_CTLON1H_CTLOP1
HT_RXCALN
H_CADOP15
H_CADOP14
H_CADOP13
H_CADOP12
H_CADOP11
H_CADON15
H_CADON14
H_CADON12
H_CADON11
H_CADON13
H_CADON10H_CADOP10H_CADON9H_CADOP9
H_CADOP8H_CADON8
H_CADOP7H_CADON7
H_CADOP6H_CADON6
H_CADOP5H_CADON5
H_CADOP4H_CADON4
H_CADON3H_CADOP3
H_CADOP2H_CADON2
H_CADON0H_CADOP0
H_CADON1H_CADOP1
PCIE_LAN_C_RX_P0
PCIE_WLAN_C_RX_P1PCIE_WLAN_C_RX_N1
PCIE_LAN_C_RX_N0
PCIE_WLAN_C_TX_N1PCIE_WLAN_C_TX_P1PCIE_WLAN_TX_P1
PCIE_WLAN_TX_N1
PCIE_LAN_C_TX_P0PCIE_LAN_C_TX_N0PCIE_LAN_TX_N0
PCIE_LAN_TX_P0
PCIE_CARD_C_RX_P2PCIE_CARD_C_RX_N2
PCIE_CARD_TX_P2PCIE_CARD_TX_N2
PCIE_CARD_C_TX_P2PCIE_CARD_C_TX_N2
HT_RXCALP
TMDS_B_CLKTMDS_B_CLK#
TMDS_B_DATA0TMDS_B_DATA0#
TMDS_B_DATA1TMDS_B_DATA1#
TMDS_B_DATA2TMDS_B_DATA2#
TMDS_B_DATA2#
TMDS_B_DATA1#
TMDS_B_CLK#
TMDS_B_DATA2
TMDS_B_DATA0#
TMDS_B_DATA1
TMDS_B_DATA0
TMDS_B_CLK H_CADIP[0..15]<4>
H_CADON[0..15]<4>
H_CADIN[0..15]<4>
H_CADOP[0..15]<4>
H_CLKOP1<4>H_CLKON1<4>
H_CTLOP0<4>H_CTLON0<4>
SB_TX0P <17>SB_TX0N <17>SB_TX1P <17>SB_TX1N <17>
SB_RX0P<17>
SB_RX1N<17>
SB_RX0N<17>SB_RX1P<17>
H_CLKON0<4>H_CLKOP0<4>
H_CTLON1<4>H_CTLOP1<4>
H_CTLIN0 <4>
H_CLKIP0 <4>
H_CLKIP1 <4>H_CLKIN0 <4>
H_CLKIN1 <4>
H_CTLIP0 <4>
H_CTLIP1 <4>H_CTLIN1 <4>
SB_RX2P<17>SB_RX2N<17>SB_RX3P<17>SB_RX3N<17>
SB_TX2N <17>SB_TX2P <17>
SB_TX3P <17>SB_TX3N <17>
PCIE_WLAN_C_RX_P1<24>
PCIE_LAN_C_RX_P0<25>PCIE_LAN_C_RX_N0<25>
PCIE_WLAN_C_RX_N1<24>PCIE_WLAN_C_TX_P1 <24>PCIE_WLAN_C_TX_N1 <24>
PCIE_LAN_C_TX_P0 <25>PCIE_LAN_C_TX_N0 <25>
PCIE_CARD_C_RX_P2<24>PCIE_CARD_C_RX_N2<24>
PCIE_CARD_C_TX_P2 <24>PCIE_CARD_C_TX_N2 <24>
TMDS_B_CLK <16>TMDS_B_CLK# <16>
TMDS_B_DATA0 <16>TMDS_B_DATA0# <16>
TMDS_B_DATA1 <16>TMDS_B_DATA1# <16>
TMDS_B_DATA2 <16>TMDS_B_DATA2# <16>
+1.1VS
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
RS780MC HT / PCIE / DVI
Custom
10 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Place < 100mils from pin B25 and B24Place < 100mils from pin AC8 and AB8 Place < 100mils from pin C23 and A24
R85 1.27K_0402_1%
1 2
C548 0.1U_0402_16V7K~N 1 2C558 0.1U_0402_16V7K~N 1 2
C536 0.1U_0402_16V7K~N 1 2
R386 301_0402_1%1 2R84 2K_0402_1%
1 2
R390 10_0402_5%@1 2
R388 10_0402_5%@1 2
C183 0.1U_0402_16V7K~N 1 2
C532 0.1U_0402_16V7K~N 1 2
PART 1 OF 6
HY
PE
R T
RA
NS
PO
RT
CP
U I/
F
U780MA
RS780M_FCBGA528
HT_RXCAD15PU19HT_RXCAD15NU18
HT_RXCAD14PU20HT_RXCAD14NU21
HT_RXCAD13PV21HT_RXCAD13NV20
HT_RXCAD12PW21HT_RXCAD12NW20
HT_RXCAD11PY22HT_RXCAD11NY23
HT_RXCAD10PAA24HT_RXCAD10NAA25
HT_RXCAD9PAB25HT_RXCAD9NAB24
HT_RXCAD8PAC24HT_RXCAD8NAC25
HT_RXCAD7PN24HT_RXCAD7NN25
HT_RXCAD6PP25HT_RXCAD6NP24
HT_RXCAD5PP22HT_RXCAD5NP23
HT_RXCAD4PT25HT_RXCAD4NT24
HT_RXCAD3PU24HT_RXCAD3NU25
HT_RXCAD2PV25HT_RXCAD2NV24
HT_RXCAD1PV22HT_RXCAD1NV23
HT_RXCAD0PY25HT_RXCAD0NY24
HT_RXCLK1PAB23HT_RXCLK1NAA22
HT_RXCLK0PT22HT_RXCLK0NT23
HT_RXCTL0PM22HT_RXCTL0NM23HT_RXCTL1PR21HT_RXCTL1NR20
HT_RXCALPC23HT_RXCALNA24
HT_TXCAD15P P18HT_TXCAD15N M18
HT_TXCAD14P M21HT_TXCAD14N P21
HT_TXCAD13P M19HT_TXCAD13N L18
HT_TXCAD12P L19HT_TXCAD12N J19
HT_TXCAD11P J18HT_TXCAD11N K17
HT_TXCAD10P J20HT_TXCAD10N J21
HT_TXCAD9P G20HT_TXCAD9N H21
HT_TXCAD8P F21HT_TXCAD8N G21
HT_TXCAD7P K23HT_TXCAD7N K22
HT_TXCAD6P K24HT_TXCAD6N K25
HT_TXCAD5P J25HT_TXCAD5N J24
HT_TXCAD4P H23HT_TXCAD4N H22
HT_TXCAD3P F23HT_TXCAD3N F22
HT_TXCAD2P F24HT_TXCAD2N F25
HT_TXCAD1P E24HT_TXCAD1N E25
HT_TXCAD0P D24HT_TXCAD0N D25
HT_TXCLK1P L21HT_TXCLK1N L20
HT_TXCLK0P H24HT_TXCLK0N H25
HT_TXCTL0P M24HT_TXCTL0N M25HT_TXCTL1P P19HT_TXCTL1N R18
HT_TXCALP B24HT_TXCALN B25
R389 10_0402_5%@1 2
PART 2 OF 6
PC
IE I/
F G
FX
PCIE I/F GPP
PCIE I/F SB
U780MB
RS780M_FCBGA528
SB_TX3P AD5SB_TX3N AE5
GPP_TX2P AA2GPP_TX2N AA1GPP_TX3P Y1GPP_TX3N Y2
SB_RX3PW5SB_RX3NY5
GPP_RX2PAD1GPP_RX2NAD2GPP_RX3PV5GPP_RX3NW6
SB_TX0P AD7SB_TX0N AE7SB_TX1P AE6SB_TX1N AD6
SB_RX0PAA8SB_RX0NY8SB_RX1PAA7SB_RX1NY7
PCE_CALRP(PCE_BCALRP) AC8PCE_CALRN(PCE_BCALRN) AB8
SB_TX2N AC6SB_RX2PAA5SB_RX2NAA6 SB_TX2P AB6
GPP_RX0PAE3GPP_RX0NAD4GPP_RX1PAE2GPP_RX1NAD3
GPP_TX0P AC1GPP_TX0N AC2GPP_TX1P AB4GPP_TX1N AB3
GFX_RX0PD4GFX_RX0NC4GFX_RX1PA3GFX_RX1NB3GFX_RX2PC2GFX_RX2NC1GFX_RX3PE5GFX_RX3NF5GFX_RX4PG5GFX_RX4NG6GFX_RX5PH5GFX_RX5NH6GFX_RX6PJ6GFX_RX6NJ5GFX_RX7PJ7GFX_RX7NJ8GFX_RX8PL5GFX_RX8NL6GFX_RX9PM8GFX_RX9NL8GFX_RX10PP7GFX_RX10NM7GFX_RX11PP5GFX_RX11NM5GFX_RX12PR8GFX_RX12NP8GFX_RX13PR6GFX_RX13NR5GFX_RX14PP4GFX_RX14NP3GFX_RX15PT4GFX_RX15NT3
GFX_TX0P A5GFX_TX0N B5GFX_TX1P A4GFX_TX1N B4GFX_TX2P C3GFX_TX2N B2GFX_TX3P D1GFX_TX3N D2GFX_TX4P E2GFX_TX4N E1GFX_TX5P F4GFX_TX5N F3GFX_TX6P F1GFX_TX6N F2GFX_TX7P H4GFX_TX7N H3GFX_TX8P H1GFX_TX8N H2GFX_TX9P J2GFX_TX9N J1
GFX_TX10P K4GFX_TX10N K3GFX_TX11P K1GFX_TX11N K2GFX_TX12P M4GFX_TX12N M3GFX_TX13P M1GFX_TX13N M2GFX_TX14P N2GFX_TX14N N1GFX_TX15P P1GFX_TX15N P2
GPP_TX4P Y4GPP_TX4N Y3GPP_TX5P V1GPP_TX5N V2
GPP_RX4PU5GPP_RX4NU6GPP_RX5PU8GPP_RX5NU7
R40549.9_0402_1% @
12
C535 0.1U_0402_16V7K~N 1 2
C547 0.1U_0402_16V7K~N 1 2
R40649.9_0402_1%@
12
C546 0.1U_0402_16V7K~N 1 2
C542 0.1U_0402_16V7K~N 1 2
R387 301_0402_1%1 2
C534 0.1U_0402_16V7K~N 1 2
C538 0.1U_0402_16V7K~N 1 2
C182 0.1U_0402_16V7K~N 1 2
C537 0.1U_0402_16V7K~N 1 2
C533 0.1U_0402_16V7K~N 1 2
R105 10_0402_5%@1 2
CLK_SBLINKCLK#
EDID_CLK_LCD
+LVDDR18D
+AVDD
LVDSLC-
LVDSL2-
LVDSL1-
LVDSLC+
EDID_DAT_LCD
+AVDDQ
+LPVDD
NB_LDTSTOP#
VGA_CRT_G
NB_STRAP_DATA
EDID_CLK_LCD
LVDSL0-LVDSL0+
VGA_CRT_B
VGA_CRT_G
LVDSL2+
CLK_SBLINKCLK
+NB_PLLVDD18
ENABLT_NBENVDD_NB
LVDSL1+
VGA_DDC_CLK
CLK_HTREFCLKP
ENVDD
NB_RST#
VGA_CRT_RVGA_CRT_R
+LVDDR33A
VGA_CRT_B
VGA_DDC_CLK_NB
EDID_CLK_LCD_NB
EDID_DAT_LCD
VGA_DDC_DATA
NB_PWRGD
NB_PWRGD5V#
ENABLT_NB
ENVDD_NB
ENABLT
ENVDD
+AVDDDI
NB_STRAP_DATA
CLK_HTREFCLKN
NB_REFCLK_N
NB_REFCLK_N
NB_ALLOW_LDTSTOP
NB_PWRGD
SB_PWRGD#
SB_PWRGD
+NB_PLLVDD
+NB_PLLVDD+NB_PLLVDD18
+NB_PCIEPLL
+NB_PCIEPLL
+NB_HTPLL
+NB_HTPLL
SB_SUS_STAT#
VGA_CRT_HSYNC
NB_LDTSTOP#LDT_STOP#
NB_ALLOW_LDTSTOPCPU_LDT_REQ#
CLK_NB_GFX_CLKPCLK_NB_GFX_CLKN
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_CRT_VSYNC
CLK_NB_REFCLK
ENABLT
NB_PWRGD
CLK_NB_REFCLK
LVDSU1-
LVDSU0-LVDSU1+
LVDSU0+
LVDSU2+LVDSU2-
LVDSUC-LVDSUC+VGA_DDC_CLK<15>
LVDSL1- <15>
CLK_HTREFCLKP<14>
VGA_DDC_DATA<15>
LVDSLC- <15>
EDID_DAT_LCD<15>
LVDSL1+ <15>
LVDSL2- <15>
ENABLT <15,28>
LVDSL0- <15>
EDID_CLK_LCD<15>
LVDSL2+ <15>
ENVDD <15>
LVDSL0+ <15>
NB_RST#<17,23,24,25,28>
LVDSLC+ <15>
VGA_CRT_R<15>
VGA_CRT_G<15>
VGA_CRT_B<15>
VGA_CRT_HSYNC<15>
CLK_HTREFCLKN<14>
CLK_NB_REFCLK<14>
SB_PWRGD<6,18,28>
CLK_NB_GFX_CLKP<14>
VGA_CRT_VSYNC<15>
CPU_LDT_REQ#<6,17>
NB_STRAP_DATA<38>
NB_PWRGD_SB <18>
SB_NB_THRMDC <19>SB_NB_THRMDA <19>
LDT_STOP#<6,17>
HPD <16>
CLK_NB_GFX_CLKN<14>
CLK_SBLINKCLK#<14>CLK_SBLINKCLK<14>
HDMIDAT_UMA<16>HDMICLK_UMA<16>
LVDSU0- <15>LVDSU0+ <15>
LVDSU1+ <15>
LVDSU2- <15>
LVDSU1- <15>
LVDSUC+ <15>
LVDSU2+ <15>
LVDSUC- <15>
SUS_STAT# <18>
+1.8VS
+3VS
+3VS
+3VS
+1.8VS
+1.8VS
+1.8VS
+5VS
+3VS
+3VS
+1.8VS
+1.1VS
+3VS
+1.8VS
+1.8VS
+5VS
+1.1VS
+1.8VS
+1.8VS
+3VS +3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
RS780MC VIDEO_IF/CLOCK GEN
Custom
11 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
15mil
15mil
15mil
15mil
15mil
15mil
15mil
15mil
15mil
0.08A
0.22A
Pull-up: DisableSide Port MemoryPull-up: Disable
Debug Port
R1172K_0402_5%@
12
C5762.2U_0603_10V6K
1
2
R1424.7K_0402_5%@
12
R1434.7K_0402_5%
@
12
C2692.2U_0603_10V6K
1
2
L16
FCM2012C-800_08051 2
R11610K_0402_5%
12
R41533_0402_5%
@
12
G
DS
Q18
BSS138_NL_SOT23-3
@
2
13
G
D
SQ14
SSM3K7002FU_SC70-3@
2
13
R362 0_0402_5%12
G
DS
Q19 BSS138_NL_SOT23-3
@
2
13
PART 3 OF 6
PM
CLO
CK
sPL
L PW
R
MIS.
CR
T/TV
OU
TLV
TM
U780MC
RS780M_FCBGA528
VDDA18HTPLLH17
SYSRESETbD8POWERGOODA10LDTSTOPbC10ALLOW_LDTSTOPC12
REFCLK_P/OSCIN(OSCIN)E11
PLLVDD(NC)A12
HPD(NC) D10DDC_DATA0/AUX0N(NC)A8 DDC_CLK0/AUX0P(NC)B8
THERMALDIODE_P AE8THERMALDIODE_N AD8
I2C_CLKB9
STRP_DATAB10
GFX_REFCLKPT2GFX_REFCLKNT1
GPP_REFCLKPU1GPP_REFCLKNU2
PLLVDD18(NC)D14PLLVSS(NC)B12
TXOUT_L0P(NC) A22TXOUT_L0N(NC) B22TXOUT_L1P(NC) A21TXOUT_L1N(NC) B21TXOUT_L2P(NC) B20
TXOUT_L2N(DBG_GPIO0) A20TXOUT_L3P(NC) A19
TXOUT_U0P(NC) B18
TXOUT_L3N(DBG_GPIO2) B19
TXOUT_U0N(NC) A18TXOUT_U1P(PCIE_RESET_GPIO3) A17TXOUT_U1N(PCIE_RESET_GPIO2) B17
TXOUT_U2P(NC) D20TXOUT_U2N(NC) D21
TXOUT_U3P(PCIE_RESET_GPIO5) D18TXOUT_U3N(NC) D19
TXCLK_LP(DBG_GPIO1) B16TXCLK_LN(DBG_GPIO3) A16
TXCLK_UP(PCIE_RESET_GPIO4) D16TXCLK_UN(PCIE_RESET_GPIO1) D17
VDDLTP18(NC) A13VSSLTP18(NC) B13
C_Pr(DFT_GPIO5)E17Y(DFT_GPIO2)F17COMP_Pb(DFT_GPIO4)F15
RED(DFT_GPIO0)G18
TMDS_HPD(NC) D9I2C_DATAA9
TESTMODE D13
HT_REFCLKNC24 HT_REFCLKPC25
SUS_STAT#(PWM_GPIO5) D12
GREEN(DFT_GPIO1)E18
BLUE(DFT_GPIO3)E19
DAC_VSYNC(PWM_GPIO6)B11 DAC_HSYNC(PWM_GPIO4)A11
DAC_RSET(PWM_GPIO1)G14
AVDD1(NC)F12AVDD2(NC)E12
REDb(NC)G17
GREENb(NC)F18
AVDDDI(NC)F14AVSSDI(NC)G15AVDDQ(NC)H15AVSSQ(NC)H14
VDDLT18_2(NC) B15VDDLT33_1(NC) A14VDDLT33_2(NC) B14
VSSLT1(VSS) C14VSSLT2(VSS) D15
VDDLT18_1(NC) A15
VSSLT3(VSS) C16VSSLT4(VSS) C18VSSLT5(VSS) C20
LVDS_DIGON(PCE_TCALRP) E9LVDS_BLON(PCE_RCALRP) F7
LVDS_ENA_BL(PWM_GPIO2) G12
VSSLT6(VSS) E20
VDDA18PCIEPLL1D7VDDA18PCIEPLL2E7
BLUEb(NC)F19
AUX_CAL(NC)C8
GPPSB_REFCLKP(SB_REFCLKP)V4GPPSB_REFCLKN(SB_REFCLKN)V3
DDC_DATA1/AUX1N(NC)A7 DDC_CLK1/AUX1P(NC)B7
DAC_SCL(PCE_RCALRN)F8DAC_SDA(PCE_TCALRN)E8
REFCLK_N(PWM_GPIO3)F11
VSSLT7(VSS) C22
RSVDG11
L19
FCM2012C-800_08051 2
R3781K_0402_1%
12
C2634.7U_0805_6.3V6K~N
1
2
R110 150_0402_1%
1 2
R15
41K
_040
2_5%
12
L14
FCM2012C-800_08051 2
R1564.7K_0402_5%
@
12
R413 0_0402_5%1 2
R414 4.7K_0402_5%
12
L12
FCM2012C-800_08051 2
R1083K_0402_5%
12
R410300_0402_5%
12
R15510K_0402_5%
12
C5652.2U_0603_10V6K
1
2
G
DS
Q21AP2301GN 1P SOT23
@
2
13
R13
910
K_04
02_5
%
@
12
R144 0_0402_5%12
C2570.1U_0402_16V7K~N
1
2
C2622.2U_0603_10V6K
1
2
R439 0_0402_5%@12
R111 150_0402_1%
1 2
R101 150_0402_1%
1 2
L54
FCM2012C-800_08051 2
L11
FCM2012C-800_0805@
1 2
R14010K_0402_5%
12
G
D
S
Q22SSM3K7002FU_SC70-3
2
13
L10
FCM2012C-800_08051 2
R1071.27K_0402_1%
12
C57722P_0402_50V8J
@1
2
R141 0_0402_5%12
R100 715_0402_1%
1 2
R12
21K
_040
2_5%
@
12
C2682.2U_0603_10V6K
1
2
R407
0_0603_5%1 2
R971.27K_0402_1%
12
R106 0_0402_5%12
R99 0_0402_5%1 2
G
D
SQ13SSM3K7002FU_SC70-3
@
2
13
R363 0_0402_5%12
R3771K_0402_1%
12
R4090_0402_5%12
R412 4.7K_0402_5%
12
R4313K_0402_5%
12
C2672.2U_0603_10V6K
1
2
R4084.7K_0402_5%@
12
C2612.2U_0603_10V6K
1
2
L13
FCM2012C-800_08051 2
C2552.2U_0603_10V6K
1
2
R4113K_0402_5%
12
G
DS
Q12AP2301GN 1P SOT23
@
2
13
L53
FCM2012C-800_08051 2
R98 0_0402_5%12
C2332.2U_0603_10V6K
1
2
R1091.8K_0402_5%
12
R104 150_0402_1%@ 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VDDHT
+VDDHTRX
+VDDA18PCIE
+VDD18_MEM
+VDD18
+VDD33
+VDDPCIE
+VDDHTTX
+1.1VS
+1.1VS
+1.8VS
+1.8VS
+3VS
+1.1VS
+NB_CORE
+1.2V_HT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
RS780MC Power/GND
Custom
12 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
VDDG33
+1.8V
+1.1V
NC
IOPLLVDD18
+1.8V
NC+1.8V +1.8V
+3.3V
NC+1.8V +1.8V
PIN NAME
IOPLLVDD
+1.8V
+1.8V
+3.3V NC
PIN NAME
NC
+3.3VAVDDNC
NC
+1.2V
AVDDDI
RS740
NC
RS740 RX780 RS780NC
AVDDQ
+1.1V
NC
+1.1V
PLLVDD
RX780
+1.8V +1.8VNC
PLLVDD18
+1.1V
+3.3V
VDDA18HTPLL
+1.1V
RS780
NC
VDDHT
+1.1V
+1.8V
NC
RS740/RX780/RS780 POWER DIFFERENCE TABLE
+1.2V
+1.8V
+1.8V/1.5V
+1.2V
+1.8V
+1.2V +1.1V +1.1V
NC
+1.8V
NC
VDDHTRX
+1.8V
+1.8V
+1.8V
VDDHTTX
+1.8V
+1.2VVDDA18PCIEPLL
NC
VDDA18PCIE
+1.8V/1.5V
NC
+1.8VVDDG18
+1.2V
+1.8V
VDDLTP18
+1.8V
VDD18_MEM
+1.1V
+1.8V
VDDPCIE
+1.1V
+1.2V
+1.2V
VDDLT18
VDDC
+3.3V
VDDLT33
VDD_MEM
+1.8V NC
1.0V-1.1V 7A
300mil
0.5A
0.45A
0.6A
0.7A
0.25A
0.005A
0.005A
0.03A
For A11, ThisVTTHTTX power planeshould connect to+1.35VS.
C246
0.1U
_040
2_16
V7K~
N
1
2
C5744.
7U_0
805_
6.3V
6K~N
1
2
C205
1U_0
402_
6.3V
6K
1
2
C560
22U
_080
5_6.
3VAM
1
2
C258
0.1U
_040
2_16
V7K~
N
1
2
C206
1U_0
402_
6.3V
6K
1
2
C250
0.1U
_040
2_16
V7K~
N
1
2
+C203
330U
_X_2
VM_R
6M1
2
R3820_0603_5%1 2
L15
FBMA-L11-322513-201LMA40T_1210
1 2
L18
FBMA-L11-322513-201LMA40T_1210
1 2
C531
4.7U
_080
5_6.
3V6K
~N
1
2
PART 5/6
PO
WE
R
U780ME
RS780M_FCBGA528
VDDHT_1J17VDDHT_2K16VDDHT_3L16VDDHT_4M16VDDHT_5P16VDDHT_6R16VDDHT_7T16
VDDHTTX_1AE25VDDHTTX_2AD24VDDHTTX_3AC23VDDHTTX_4AB22VDDHTTX_5AA21VDDHTTX_6Y20VDDHTTX_7W19VDDHTTX_8V18
VDDHTRX_1H18VDDHTRX_2G19VDDHTRX_3F20VDDHTRX_4E21VDDHTRX_5D22
VDD18_1F9VDD18_2G9VDD18_MEM1(NC)AE11VDD18_MEM2(NC)AD11
VDDA18PCIE_1J10VDDA18PCIE_2P10VDDA18PCIE_3K10
VDDA18PCIE_10Y9VDDA18PCIE_11AA9VDDA18PCIE_12AB9VDDA18PCIE_13AD9VDDA18PCIE_14AE9
VDDA18PCIE_6W9VDDA18PCIE_7H9
VDDPCIE_1 A6VDDPCIE_2 B6VDDPCIE_3 C6VDDPCIE_4 D6VDDPCIE_5 E6VDDPCIE_6 F6VDDPCIE_7 G7VDDPCIE_8 H8VDDPCIE_9 J9
VDDA18PCIE_4M10VDDA18PCIE_5L10
VDDC_1 K12VDDC_2 J14VDDC_3 U16
VDDPCIE_11 M9
VDDC_4 J11VDDC_5 K15
VDDPCIE_10 K9
VDDC_6 M12VDDC_7 L14VDDC_8 L11VDDC_9 M13
VDDC_10 M15VDDC_11 N12VDDC_12 N14VDDC_13 P11VDDC_14 P13VDDC_15 P14VDDC_16 R12VDDC_17 R15VDDC_18 T11VDDC_19 T15VDDC_20 U12VDDC_21 T14
VDD33_1(NC) H11VDD33_2(NC) H12
VDD_MEM1(NC) AE10VDD_MEM2(NC) AA11VDD_MEM3(NC) Y11VDD_MEM4(NC) AD10
VDD_MEM6(NC) AC10VDD_MEM5(NC) AB10
VDDA18PCIE_8T10
VDDC_22 J16
VDDPCIE_12 L9
VDDA18PCIE_9R10
VDDPCIE_13 P9VDDPCIE_14 R9VDDPCIE_15 T9VDDPCIE_16 V9VDDPCIE_17 U9
VDDA18PCIE_15U10
VDDHTRX_6B23VDDHTRX_7A23
VDDHTTX_9U17VDDHTTX_10T17VDDHTTX_11R17VDDHTTX_12P17VDDHTTX_13M17
C243
1U_0
402_
6.3V
6K
1
2
L17
FBMA-L11-322513-201LMA40T_1210
1 2
C245
0.1U
_040
2_16
V7K~
N
1
2
R800_0603_5%1 2
C187
0.1U
_040
2_16
V7K~
N
1
2
C212
0.1U
_040
2_16
V7K~
N
1
2
C240
0.1U
_040
2_16
V7K~
N
1
2
C209
0.1U
_040
2_16
V7K~
N
1
2
C210
22U
_080
5_6.
3VAM
1
2
PART 6/6
GR
OU
ND
U780MF
RS780M_FCBGA528
VSSAHT1A25VSSAHT2D23VSSAHT3E22VSSAHT4G22VSSAHT5G24VSSAHT6G25VSSAHT7H19VSSAHT8J22VSSAHT9L17VSSAHT10L22VSSAHT11L24VSSAHT12L25VSSAHT13M20VSSAHT14N22VSSAHT15P20VSSAHT16R19VSSAHT17R22VSSAHT18R24VSSAHT19R25
VSSAHT21U22VSSAHT22V19VSSAHT23W22VSSAHT24W24VSSAHT25W25VSSAHT26Y21VSSAHT27AD25
VSS2 D11VSS3 G8VSS4 E14VSS5 E15
VSS7 J12VSS8 K14VSS9 M11
VSS10 L15
VSS11L12VSS12M14VSS13N13VSS14P12VSS15P15VSS16R11VSS17R14VSS18T12VSS19U14VSS20U11VSS21U15VSS22V12VSS23W11VSS24W15VSS25AC12VSS26AA14VSS27Y18VSS28AB11VSS29AB15VSS30AB17VSS31AB19VSS32AE20
VSSAPCIE1 A2VSSAPCIE2 B1VSSAPCIE3 D3VSSAPCIE4 D5VSSAPCIE5 E4VSSAPCIE6 G1VSSAPCIE7 G2VSSAPCIE8 G4VSSAPCIE9 H7
VSSAPCIE10 J4VSSAPCIE11 R7VSSAPCIE12 L1VSSAPCIE13 L2VSSAPCIE14 L4VSSAPCIE15 L7
VSS34K11
VSSAPCIE16 M6VSSAPCIE17 N4VSSAPCIE18 P6VSSAPCIE19 R1VSSAPCIE20 R2VSSAPCIE21 R4VSSAPCIE22 V7VSSAPCIE23 U4VSSAPCIE24 V8VSSAPCIE25 V6VSSAPCIE26 W1VSSAPCIE27 W2VSSAPCIE28 W4VSSAPCIE29 W7VSSAPCIE30 W8VSSAPCIE31 Y6VSSAPCIE32 AA4VSSAPCIE33 AB5VSSAPCIE34 AB1VSSAPCIE35 AB7VSSAPCIE36 AC3VSSAPCIE37 AC4VSSAPCIE38 AE1VSSAPCIE39 AE4VSSAPCIE40 AB2
VSS1 AE14
VSSAHT20H20
VSS33AB21
VSS6 J15
C242
1U_0
402_
6.3V
6K
1
2
C259
0.1U
_040
2_16
V7K~
N
1
2
C230
0.1U
_040
2_16
V7K~
N
1
2
C164
4.7U
_080
5_6.
3V6K
~N
1
2
C207
0.1U
_040
2_16
V7K~
N
1
2
C232
0.1U
_040
2_16
V7K~
N
1
2
C247
0.1U
_040
2_16
V7K~
N
1
2
C208
0.1U
_040
2_16
V7K~
N
1
2
L49
FBMA-L11-322513-201LMA40T_1210
1 2
C248
0.1U
_040
2_16
V7K~
N
1
2
C575
4.7U
_080
5_6.
3V6K
~N
1
2C266
4.7U
_080
5_6.
3V6K
~N
1
2
C185
0.1U
_040
2_16
V7K~
N
1
2
C241
0.1U
_040
2_16
V7K~
N
1
2
C2561U_0402_6.3V6K
1
2
C231
0.1U
_040
2_16
V7K~
N
1
2
R3810_0603_5%1 2
C244
0.1U
_040
2_16
V7K~
N
1
2
L4
FBMA-L11-322513-201LMA40T_12101 2
C166
0.1U
_040
2_16
V7K~
N
1
2C167
4.7U
_080
5_6.
3V6K
~N
1
2
C211
0.1U
_040
2_16
V7K~
N
1
2
C1651U_0402_6.3V6K@
1
2
C229
10U
_080
5_6.
3V6M
1
2
C186
0.1U
_040
2_16
V7K~
N
1
2
C204
0.1U
_040
2_16
V7K~
N
1
2
C184
0.1U
_040
2_16
V7K~
N
1
2
C249
0.1U
_040
2_16
V7K~
N
1
2
2
2
1
1
B B
A AVDD_MUX_IOPLLVDD+1.8V_IOPLLVDD
+1.8VS
+1.1VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
RS780MC Power/GND
Custom
13 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
SBD_MEM/DVO_I/F
PAR 4 OF 6U780MD
RS780M_FCBGA528
MEM_A0(NC)AB12MEM_A1(NC)AE16MEM_A2(NC)V11MEM_A3(NC)AE15MEM_A4(NC)AA12MEM_A5(NC)AB16MEM_A6(NC)AB14MEM_A7(NC)AD14MEM_A8(NC)AD13MEM_A9(NC)AD15MEM_A10(NC)AC16MEM_A11(NC)AE13MEM_A12(NC)AC14MEM_A13(NC)Y14
MEM_BA0(NC)AD16MEM_BA1(NC)AE17MEM_BA2(NC)AD17
MEM_RASb(NC)W12MEM_CASb(NC)Y12MEM_WEb(NC)AD18MEM_CSb(NC)AB13MEM_CKE(NC)AB18MEM_ODT(NC)V14
MEM_CKP(NC)V15MEM_CKN(NC)W14
MEM_DM0(NC) W17MEM_DM1/DVO_D8(NC) AE19
MEM_DQS0P/DVO_IDCKP(NC) Y17MEM_DQS0N/DVO_IDCKN(NC) W18
MEM_DQS1P(NC) AD20MEM_DQS1N(NC) AE21
MEM_DQ0/DVO_VSYNC(NC) AA18MEM_DQ1/DVO_HSYNC(NC) AA20
MEM_DQ2/DVO_DE(NC) AA19MEM_DQ3/DVO_D0(NC) Y19
MEM_DQ4(NC) V17MEM_DQ5/DVO_D1(NC) AA17MEM_DQ6/DVO_D2(NC) AA15MEM_DQ7/DVO_D4(NC) Y15MEM_DQ8/DVO_D3(NC) AC20MEM_DQ9/DVO_D5(NC) AD19
MEM_DQ10/DVO_D6(NC) AE22MEM_DQ11/DVO_D7(NC) AC18
MEM_DQ12(NC) AB20MEM_DQ13/DVO_D9(NC) AD22
MEM_DQ14/DVO_D10(NC) AC22MEM_DQ15/DVO_D11(NC) AD21
MEM_COMPP(NC)AE12MEM_COMPN(NC)AD12 MEM_VREF(NC) AE18
IOPLLVDD18(NC) AE23
IOPLLVSS(NC) AD23
IOPLLVDD(NC) AE24
C5302.2U_0603_10V6K@
1
2
C5292.2U_0603_10V6K@
1
2C528 0.1U_0402_16V7K~N
1
2
L470_0402_5%
12
L48
0_0402_5%12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
XTALIN_CLKXTALOUT_CLK
CLK_RESET
CLKREQ_LAN#CLKREQ_MINICARD#
CLK_USBCLK_EXT
CLK_NB_REFCLK
CLK_SBSRCCLKCLK_SBSRCCLK#
CLK_NB_GFX_CLKPCLK_NB_GFX_CLKN
CLK_GFX_CLKP
SBSRCCLK_RSBSRCCLK#_R
CLK_GFX_CLKN
SMB_CK_DAT0SMB_CK_CLK0
CLK_USBCLK_EXT
CLK_PCIE_CARDCLK_PCIE_CARD#
CLK_CARDCLK_CARD#
SBLINKCLK#_RCLK_SBLINKCLKCLK_SBLINKCLK#
SBLINKCLK_R
CLK_PCIE_WCARDCLK_PCIE_WCARD#
CLK_WCARDCLK_WCARD#
CPUCLK0H
SEL_27
SEL_SATASEL_27
SEL_HT66
SEL_HT66SEL_SATA
CLKREQ_LAN#CLKREQ_MINICARD#
CLKREQ_54CARD#
CLKREQ_54CARD#
CLK_PCIE_LANCLK_PCIE_LAN#
CLK_LANCLK_LAN#
CPUCLK0L
HTREFCLKPHTREFCLKN
GNDVSSCLK_USBCLK_EXTCLK_USB
CLK_CPUCLK0_H <6>
CLK_CPUCLK0_L <6>
CLK_SBSRCCLK <17>CLK_SBSRCCLK# <17>
CLK_NB_GFX_CLKP <11>CLK_NB_GFX_CLKN <11>
SMB_CK_DAT0<8,9,18>
CLK_SBLINKCLK <11>CLK_SBLINKCLK# <11>
CLK_PCIE_WCARD <24>CLK_PCIE_WCARD# <24>
CLKREQ_LAN#<25>CLKREQ_MINICARD#<24>
CLK_HTREFCLKP <11>CLK_HTREFCLKN <11>
CLK_NB_REFCLK <11>
CLKREQ_54CARD#<24>
SMB_CK_CLK0<8,9,18>
CLK_PCIE_CARD <24>CLK_PCIE_CARD# <24>CLK_PCIE_LAN <25>CLK_PCIE_LAN# <25>
CLK_USBCLK_EXT <18>
+3VS
+3VS_CLK
+3VS_CLK
+3VS_CLK
+3VS+1.1VS_3VS_CLK_VDDIO
+3VS_CLK
+3VS
+1.2V_HT
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Clock Generator
Custom
14 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
+3VS_CLK (40 mils)
SEL_27
SEL_HTT66
SEL_SATA
1
0*
0
0*
1*
1 66 MHz 3.3V single ended HTT clock
100 MHz differential HTT clock
100 MHz non-spreading differential SRC clock
100 MHz spreading differential SRC clock
* default
Pin 4 / 5 configure as SRC_7 output
Pin 4 / 5 configure as 27M and 27M_SS outputs
RS780
1.8V 33R/43RRX780
3.3V 33R serialRS740
1.1V 200R/100R
OSC_14M_NB
100M DIFF
GPPSB_REFCLK 100M DIFF 100M DIFF
100M DIFF(IN/OUT)*
HT_REFCLKP
RS740 RX780 RS780
NB CLOCK INPUT TABLE
NC or 100M DIFF OUTPUT
* RS780 can be used as clock buffer to output two PCIE referecence clocksBy deault, chip will configured as input mode, BIOS can program it to output mode.
66M SE(SINGLE END)
NC
100M DIFF
100M DIFF
100M DIFF
100M DIFF
14M SE (3.3V) 14M SE (1.8V) 14M SE (1.1V)
NB CLOCKS
NC NC vref
HT_REFCLKN
Clock chip has internal serial terminationsfor differencial pairs, external resistors arereserved for debug purpose.
100M DIFF
REFCLK_P
100M DIFF
REFCLK_N
NC
GFX_REFCLK
GPP_REFCLK
100M DIFF
R40/R41 (value may change)
ICS9LPRS476BKLFT
VDDIO voltage range is 1.05V~3.3V
CLK_NB_REFCLK willget 1.1V with R400200ohm and R401 100ohm.
R419 158_0402_1%
1 2
C354
0.1U
_040
2_16
V7K~
N
1
2
R447 0_0402_5%
12
C56727P_0402_50V8J
1 2
C584
0.1U
_040
2_16
V7K~
N
1
2
C597
0.1U
_040
2_16
V7K~
N
1
2
C588
22U
_080
5_6.
3V6M
1
2
Y414.31818MHz_20P_1BX14318BE1A
12
R12
9
8.2K
_040
2_5%
@
12
C296
0.1U
_040
2_16
V7K~
N
1
2
C568 10P_0402_25V8K@ 1 2
C583
2.2U
_060
3_10
V6K
1
2
C27722P_0402_50V8J
@
1
2
C295
0.1U
_040
2_16
V7K~
N
1
2
C294
0.1U
_040
2_16
V7K~
N
1
2
C334
0.1U
_040
2_16
V7K~
N
1
2
R416 33_0402_5%1 2
R39190.9_0402_1%
12
R420 0_0402_5%
12
R13
4
8.2K
_040
2_5%
12
C311
0.1U
_040
2_16
V7K~
N
1
2
R392261_0402_1%@
12
R461 0_0402_5%
12
C56627P_0402_50V8J
1 2
C596
0.1U
_040
2_16
V7K~
N
1
2
C578 10P_0402_25V8K@ 1 2
R14
9
2.2K
_040
2_5%
12
L58
0_0805_5%
1 2
R422 10K_0402_5%1 2
R13
1
8.2K
_040
2_5%
@
12
R454 0_0402_5%
12
R418 33_0402_5% @1 2
R455 0_0402_5%
12
R13
2
8.2K
_040
2_5%
12
R14633_0402_5%@
12
C587
0.1U
_040
2_16
V7K~
N
1
2
C582
22U
_080
5_6.
3V6M
1
2
R463 0_0402_5%
12
R43
3
10K_
0402
_5%
12
C332
0.1U
_040
2_16
V7K~
N
1
2
R45
8
10K_
0402
_5%
12
R445 0_0402_5%
12
U27
SLG8SP626VTR_QFN72_10x10
VDD_CPU54
VDD_CPU_I/O53
VSS_CPU52
CLKREQ_1#51CLKREQ_2#50
VDD_A49
VSS_SRC19
SRC_1# 20SRC_1 21SRC_0# 22SRC_0 23
CLKREQ_0#24
ATIGCLK_2# 25ATIGCLK_2 26
VSS_ATIG27
VDD_ATIG_IO28
VDD_ATIG29 ATIGCLK_1# 30ATIGCLK_1 31ATIGCLK_0# 32
VSS_SB_SRC36
SB_SRC_1 35SB_SRC_1# 34
ATIGCLK_0 33
VSS_A48
VSS_SATA47
SRC_6/SATA 46SRC_6#/SATA# 45
VDD_SATA44
CLKREQ_3#43CLKREQ_4#42
SB_SRC_SLOW#41
SB_SRC_0 40SB_SRC_0# 39
VDD_SB_SRC38
VDD_SB_SRC_IO37
REF_1/SEL_SATA 64REF_2/SEL_27 63
VDD_REF62 VDD_HTT61
HTT_0/66M_0 60HTT_0#/66M_1 59
VSS_HTT58
PD#57
CPU_K8_0 56CPU_K8_0# 55
SCL1SDA2
VDD_DOT3
SRC_7#/27M 4SRC_7/27M_SS 5
VSS_DOT6
SRC_5# 7SRC_5 8SRC_4# 9SRC_4 10
VSS_SRC11
VDD_SRC_IO12
SRC_3# 13SRC_3 14SRC_2# 15SRC_2 16
VDD_SRC17
VDD_SRC_IO18
REF_0/SEL_HTT66 65
VSS_REF66
XTAL_IN67XTAL_OUT68
VDD_4869
48MHz_1 7048MHz_0 71
VSS_4872GND73
R462 0_0402_5%
12
R417 33_0402_5% @1 2
R424 0_0402_5%
12
C312
0.1U
_040
2_16
V7K~
N
1
2
R456 0_0402_5%
12
R13
3
8.2K
_040
2_5%
@
12
C293
0.1U
_040
2_16
V7K~
N
1
2
C333
0.1U
_040
2_16
V7K~
N
1
2
L60
FBM-L11-160808-601LMT_0603
@12
L59
0_0805_5%
1 2
L55
FBM-L11-160808-601LMT_060312
C335
0.1U
_040
2_16
V7K~
N
1
2
R13
0
8.2K
_040
2_5%
@
12
C3100.
1U_0
402_
16V7
K~N
1
2
R15
0
2.2K
_040
2_5%
@
12
R444 0_0402_5%
12
R460 0_0402_5%
12
R457 0_0402_5%
12
R446 0_0402_5%
12
R45
9
2.2K
_040
2_5%
@
12
R421 0_0402_5%
12
C598
22U
_080
5_6.
3V6M
1
2
R43
2
10K_
0402
_5%
@
12
L56
FBM-L11-160808-601LMT_060312
R423 0_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CRT_HSYNC D_CRT_HSYNCVGA_CRT_HSYNC
VGA_CRT_VSYNC CRT_VSYNC D_CRT_VSYNC
VGA_CRT_R
VGA_CRT_B
CRT_R_L
VGA_DDC_DATA_C
VGA_CRT_G CRT_G_L
HSYNC_L
VGA_DDC_CLK_C
VSYNC_L
CRT_B_L
INVT_PWM
EDID_DAT_LCD
DISPOFF#
EDID_CLK_LCD
+LCDVDD_R
LVDSL0+LVDSL0-
LVDSL1+LVDSL1-
LVDSL2+LVDSL2-
LVDSLC+LVDSLC-
INVPWR_B+ INVPWR_B+
VGA_DDC_CLK_C
VGA_DDC_DATA_C
BKOFF# DISPOFF#
DAC_BRIGINVT_PWM
+LCDVDD
ENVDD
LVDSU0+
LVDSU1-LVDSU1+
LVDSU0-
LVDSU2-LVDSU2+
LVDSUC-LVDSUC+
VGA_CRT_HSYNC<11>
VGA_CRT_VSYNC<11>
VGA_CRT_R<11>
VGA_CRT_G<11>
VGA_CRT_B<11>
MSEN#<28>
DAC_BRIG <28>
EDID_CLK_LCD<11>EDID_DAT_LCD<11>
INVT_PWM <28>
LVDSL0+ <11>LVDSL0- <11>
LVDSL1+ <11>LVDSL1- <11>
LVDSL2+ <11>LVDSL2- <11>
LVDSLC+ <11>LVDSLC- <11>
VGA_DDC_DATA <11>
VGA_DDC_CLK <11>
BKOFF#<28>
ENABLT<11,28>
ENVDD<11>
LVDSU0+<11>LVDSU0-<11>
LVDSU1+<11>LVDSU1-<11>
LVDSU2+<11>LVDSU2-<11>
LVDSUC+<11>LVDSUC-<11>
+CRT_VCC+5VS
+CRT_VCC
+CRT_VCC
+3VS +3VS
B+
+3VS+CRT_VCC +3VS+CRT_VCC +3VS
+LCDVDD
+3VS
+3VS +LCDVDD
+5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
CRT Conn.& LCD Conn. & Camera
Custom
15 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
W=40milsW=40mils
LCD POWER CIRCUITW=60milsW=60mils
R32
315
0_04
02_1
%
12
R7 10K_0402_5%12
R5 39_0402_5%1 2
C46
710
0P_0
402_
25V8
K
D17RB751V-40TE17_SOD323-2
21
C4681U_0603_10V6K@
1
2
R33
315
0_04
02_1
%
12
JCRT
SUYIN_070546FR015S2307R~D
611
17
1228
1339
144
1015
5
1617
C104.7U_0805_6.3V6K~N
1
2
D16
DAN217_SC59-3
231
D3
DAN217_SC59-3
231
R4 0_0603_5%1 2
C47
38P
_040
2_50
V8K
1
2
F3
1.1A_6VDC_FUSE
21
G
D S
Q1BSS138_NL_SOT23-3
2
1 3
R9
0_04
02_5
%1
2
R11
6.8K
_040
2_5%
12
L37
FCM2012C-800_08051 2
C47
28P
_040
2_50
V8K 1
2
R10
4.7K
_040
2_5%
12
C168P_0402_50V8K
1
2
C47
50.1U_0603_50V4Z
1
2
C5 0.1U_0402_16V7K~N1 2
L38
FCM2012C-800_08051 2
C4870.1U_0402_16V7K~N@
1
2
C7
68P_
0402
_50V
8K
1
2
R3
6.8K
_040
2_5%
12
C47
4
0.1U_0603_50V4Z
1
2
G
D S
Q2BSS138_NL_SOT23-3
2
1 3
D18RB751V-40TE17_SOD323-2@ 21
R6 0_0603_5%1 2
C46
98P
_040
2_50
V8K 1
2
C48
910
0P_0
402_
25V8
K
F2
3A_32V
21
R2
4.7K
_040
2_5%
12
C410P_0402_50V8J
1
2
U174AHCT1G125GW_SOT353-5
A2 Y 4OE#
1G
3P
5
JLCD1
ACES_87242-400111 33 55 77 99 1111 1313 1515 1717 1919 2121 2323 2525 2727 2929 3131 3333 3535 3737 3939
2 24 46 68 810 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 40GND41 GND 42
C47
08P
_040
2_50
V8K
1
2
C6 0.1U_0402_16V7K~N1 2
R335
1K_0402_5%
12
R1210K_0402_5%
12
D2
DAN217_SC59-3
231
D15
DAN217_SC59-3
231
C47
10.
1U_0
402_
16V4
Z
@1
2
U3
AOZ1320CI-04_SOT23-6
GND 2
EN3 NC 4
IN6 OUT 1
GND5
L39
FCM2012C-800_08051 2
C3
10P_
0402
_50V
8J
1
2
R33
415
0_04
02_1
%
12
D14
1N4148_SOT23@
12
D13
DAN217_SC59-3
231
U274AHCT1G125GW_SOT353-5
A2 Y 4OE#
1G
3P
5
D19
RB491D_SOT23
2 1
C48
18P
_040
2_50
V8K
1
2
C80.1U_0402_16V7K~N
1
2
C48
08P
_040
2_50
V8K 1
2
C490
0.1U
_040
2_16
V7K~
N
1
2
R13 0_1206_5%1 2
C90.1U_0402_16V7K~N
1
2
R8 39_0402_5%1 2
C48
20.
1U_0
402_
16V4
Z
@1
2
C48
30.
1U_0
402_
16V4
Z
@ 1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
HDMI_CLK+HDMI_CLK-
HDMI_TX0+HDMI_TX0-
HDMI_TX1+HDMI_TX1-
HDMI_TX2+HDMI_TX2-
HDMI_HPD
HDMI_SDATA
HDMI_SCLK
HDMI_R_D0+
HDMI_R_CK-
HDMI_R_CK+HDMI_CLK+
HDMI_CLK-
HDMI_TX0-
HDMI_TX0+
HDMI_R_D0-
HDMI_TX1+
HDMI_R_D2+
HDMI_R_D2-HDMI_TX2-
HDMI_TX2+
HDMI_R_D1-
HDMI_R_D1+
HDMI_TX1-
HDMI_R_CK-
HDMI_R_CK+
HDMI_R_D2-
HDMI_R_D2+
HDMI_R_CK-
HDMI_R_D1+
HDMI_R_D1-
HDMI_R_D2-
HDMI_R_CK+
HDMI_R_D2+
HDMI_R_D0+
HDMI_R_D0-
HDMI_HPD
HDMI_SCLKHDMI_SDATA
HDMI_R_D0-
HDMI_R_D0+
HDMI_R_D1-
HDMI_R_D1+
TMDS_B_CLK<10>TMDS_B_CLK#<10>
TMDS_B_DATA2<10>TMDS_B_DATA2#<10>
TMDS_B_DATA1<10>
TMDS_B_DATA0<10>TMDS_B_DATA0#<10>
TMDS_B_DATA1#<10>
HDMICLK_UMA<11>
HDMIDAT_UMA<11>HPD <11>
+5VS +HDMI_5V_OUT
+HDMI_5V_OUT
+3VS
+HDMI_5V_OUT+3VS
+5VS
+5VS
+5VS
+5VS
+HDMI_5V_OUT
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
HDMICustom
16 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
MP:Update D10 to meet HDMI.
SI:Add Q136 & Q137 for AMD request
HDMI Connector
SI:Add R6161~R624 for EMI requset
FOR U1H
C238 0.1U_0402_16V7K1 2
R121100K_0402_5%
U1H@
12
R88 0_0402_5%@1 2
G
D S
Q47
SSM3K7002FU_SC70-3U1H@
2
1 3
R93 0_0402_5%@1 2
R1384.7K_0402_5%
12
G
D S
Q44
SSM3K7002FU_SC70-3U1H@
2
1 3
R368 750_0402_1%1 2
R380 750_0402_1%1 2
R369 750_0402_1%1 2
C227 0.1U_0402_16V7K1 2
C226 0.1U_0402_16V7K1 2
C2730.1U_0402_16V4ZU1H@
1
2
R87 0_0402_5%@1 2
R94 0_0402_5%@1 2
R96 0_0402_5%@1 2
G
DS
Q17BSH111_SOT23
U1H@
2
13
R92 0_0402_5%@1 2
U8SN74AHCT1G125GW_SOT353-5U1H@
A2 Y 4OE#
1G
3P
5
D7
RB491D_SOT23U1H@
2 1
R89 0_0402_5%@1 2
R379 750_0402_1%1 2
R1646.8K_0402_5%
R370 750_0402_1%1 2
C228 0.1U_0402_16V7K1 2
G
D S
Q46
SSM3K7002FU_SC70-3U1H@
2
1 3
R95 0_0402_5%@1 2
G
D S
Q45
SSM3K7002FU_SC70-3U1H@
2
1 3C202 0.1U_0402_16V7K1 2
L9
WCM-2012-900T_080511 2 2
3 344
R1362.2K_0402_5%
U1H@12
C239 0.1U_0402_16V7K1 2
C200 0.1U_0402_16V7K1 2
R1376.8K_0402_5%
R372 750_0402_1%1 2
C2750.1U_0402_16V4Z
U1H@
1
2 R1804.7K_0402_5%
12
R373 750_0402_1%1 2
L5
WCM-2012-900T_080511 2 2
3 344
R374 750_0402_1%1 2
G
DS
Q24BSH111_SOT23
U1H@
2
13
C201 0.1U_0402_16V7K1 2
C274
0.1U_0402_16V4ZU1H@
1
2
L6
WCM-2012-900T_080511 2 2
3 344
L7
WCM-2012-900T_080511 2 2
3 344
JHDMI
FOX_QJ1119L-NT02-7FD2+1 D2_shield2 D2-3 D1+4 D1_shield5 D1-6 D0+7 D0_shield8 D0-9 CK+10 CK_shield11 CK-12 CEC13 Reserved14 SCL15 SDA16 DDC/CEC_GND17 +5V18 HP_DET19
GND 20GND 21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SB_RX0PSB_RX0NSB_RX1PSB_RX1N
PCI_AD[0..31]
PCI_RST#
CLK_PCI_MINI
CLK_PCI_CB
CLK_PCI_ECCLK_PCI_TPM
RTC_BAT_PWR
SB_RX2PSB_RX2NSB_RX3PSB_RX3N
RTC_CLK
PCI_AD17PCI_AD16
PCI_AD13
PCI_PERR#
PCI_TRDY#
PCI_CBE#0
PCICLK1_R
SB_32KH0
PCI_PIRQH#
PCI_AD22
LPC_AD3
PCICLK0_R
SB_TX0N
PCI_AD18
PCI_AD3
PCI_STOP#PCI_PAR
PCI_DEVSEL#
SB_TX2P
SB_TX1P
LOCK#
PCI_AD21
PCI_AD19
PCI_AD10
SB_RX3N_C
PCI_AD7
PCI_CBE#2
SB_TX3N
SB_TX1N
PCI_PIRQE#
PCI_AD27
SIRQ
LPC_AD2
PCI_REQ#0
A_RST#
PCI_AD20
PCI_AD8
PCI_AD1
PCI_CBE#3
SB_TX2N
SB_TX0P
PCI_AD29
PCI_AD9
PCI_FRAME#
SB_32KHI
SB_RX1P_C
+PCIE_PVDD
PCI_AD30
PCI_AD4
LDRQ0#
PCI_GNT#0
LDT_RST#
PCI_PIRQF#
LDRQ1#
PCI_AD25
PCI_AD23
PCI_AD14
LPC_FRAME#
SB_RX2N_C
PCI_AD31
SB_RX3P_C
PCI_AD11
PCI_AD26
PM_CLKRUN#
PCI_CBE#1
SB_RX0N_C
PCI_AD0
PCI_PIRQG#
PCI_AD15
SB_TX3P
SB_RX2P_C
PCIRST#
PCI_AD28
LPC_AD1LPC_AD0
PCI_AD24
PCI_AD6
PCI_SERR#
SB_RX1N_C
SB_RX0P_C
PCI_AD12
PCI_AD5
PCI_AD2
PCI_IRDY#
CLK_SBSRCCLK#CLK_SBSRCCLK
CPU_LDT_REQ#
NB_RST#
CLK_PCI_TPMPCICLK5_RPCICLK4_R
PCICLK5_RPCICLK4_R
PCICLK2_RPCICLK3_R
A_RST#NB_RST#
PCI_TRDY# <22>
PCI_STOP# <22>
PCI_FRAME# <22>PCI_DEVSEL# <22>PCI_IRDY# <22>
PCI_SERR# <22>PCI_PERR# <22>
PCI_REQ#0 <22>
PCI_GNT#0 <22>
PCI_CBE#0 <22>
PM_CLKRUN# <22,28>
PCI_CBE#3 <22>
PCI_PAR <22>
PCI_CBE#1 <22>PCI_CBE#2 <22>
LPC_FRAME# <24,28>
LPC_AD1 <24,28>LPC_AD2 <24,28>
LPC_AD0 <24,28>
LPC_AD3 <24,28>
SIRQ <22,28>
SB_RX0P<10>SB_RX0N<10>SB_RX1P<10>SB_RX1N<10>
CLK_PCI_MINI <24>
PCI_RST# <22,24>
PCI_AD[0..31] <21,22>
LDT_RST#<6>
PCI_PIRQF# <22>PCI_PIRQE# <22>
SB_TX1P<10>SB_TX1N<10>
SB_TX0P<10>SB_TX0N<10>
CLK_PCI_CB <22>
CLK_PCI_EC <28>
CPU_PWRGD<6>LDT_STOP#<6,11>
SB_RX2P<10>SB_RX2N<10>SB_RX3P<10>SB_RX3N<10>
SB_TX3P<10>SB_TX3N<10>
SB_TX2P<10>SB_TX2N<10>
CLR_CMOS <29>
CLK_SBSRCCLK<14>CLK_SBSRCCLK#<14>
CPU_LDT_REQ#<6,11>
LPC_CLK0 <21>LPC_CLK1 <21>
RTC_CLK <21>
NB_RST#<11,23,24,25,28>
CPU_PROCHOT#<6>
PCICLK2_R <21>PCICLK3_R <21>
+SB_VBAT
CHGRTC
+1.2V_HT
+SB_VBAT
+1.8VS
+PCIE_VDDR+3VS +3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SB700-PCI_EXP/PCI/LPC/RTC
Custom
17 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
+
0.1A
W=20mils
Reserved
C595 0.1U_0402_16V7K
L25
BLM21A601SPT_0805
1 2
C343 0.1U_0402_16V7K
R42520M_0603_5% 12
R44933_0402_5%1 2
Y5
32.768KHZ_12.5PF_1TJS125BJ4A421P
OUT4
IN1
NC 3
NC 2
C579
18P_0402_50V8J~N
1 2
R18410K_0402_5%@
12
C580
18P_0402_50V8J~N
1 2
R16810K_0402_5%@
12
R427 22_0402_5%1 2
C581
0.1U_0402_16V7K~N
1
2
C344 0.1U_0402_16V7K
TP35
C599 0.1U_0402_16V7K
TP38
PCI E
XPR
ESS
INTE
RFA
CE
Part 1 of 5SB700
PCI I
NTE
RFA
CE
LPC
RTCC
PU
RTC
XTA
L
PCI C
LKS
CLO
CK
GEN
ERAT
OR
USB700A
218S7EALA11FG_BGA528_SB700~D
A_RST#N2
PCIE_RX2PR20PCIE_RX2NR21PCIE_RX3PR18
PCIE_TX3NT22 PCIE_TX3PT23 PCIE_TX2NU24 PCIE_TX2PU25
PCIE_RX1PU19PCIE_RX1NV19
PCIE_RX0PU22PCIE_RX0NU21
PCIE_TX1NV25 PCIE_TX1PV24 PCIE_TX0NV22 PCIE_TX0PV23
PCIE_RCLKP/NB_LNK_CLKPN25PCIE_RCLKN/NB_LNK_CLKNN24
PCIE_CALRPT25PCIE_CALRNT24
PCIE_PVDDP24
GPP_CLK1NL19
X1A3
X2B3
VBAT B2
GPP_CLK0NJ18
GPP_CLK2PM19
ALLOW_LDTSTPF23
CPU_HT_CLKNM18
GPP_CLK2NM20
SLT_GFX_CLKPM23
CPU_HT_CLKPP17
LDT_RST#G24
PCICLK0 P4PCICLK1 P3PCICLK2 P1PCICLK3 P2
PCIRST# N1
CBE0# W2CBE1# U7CBE2# AA7CBE3# Y1
FRAME# AA6DEVSEL# W5
IRDY# AA5TRDY# Y5
PAR U6STOP# W6PERR# W4
REQ0# AC3REQ1# AD4REQ2# AB7
REQ3#/GPIO70 AE6
GNT0# AD2GNT1# AE4GNT2# AD5
GNT3#/GPIO72 AC6
SERR# V7
CLKRUN# AD6
LAD0 H24LAD1 H23LAD2 J25LAD3 J24
LFRAME# H25LDRQ0# H22
SERIRQ V15
PCICLK4 T4
LPCCLK0 G22LPCCLK1 E22
AD0 U2AD1 P7AD2 V4AD3 T1AD4 V3AD5 U1AD6 V1AD7 V2AD8 T2AD9 W1
AD10 T9
AD12 R7AD13 R5AD14 U8AD15 U5AD16 Y7AD17 W8AD18 V9AD19 Y8AD20 AA8AD21 Y4AD22 Y3AD23 Y2AD24 AA2AD25 AB4AD26 AA1AD27 AB3AD28 AB2AD29 AC1AD30 AC2AD31 AD1
AD11 R6
REQ4#/GPIO71 AB6
GNT4#/GPIO73 AE5
LDRQ1#/GNT5#/GPIO68 AB8
GPP_CLK1PL20
RTCCLK C3
PCIE_RX3NR17
INTE#/GPIO33 AD3INTF#/GPIO34 AC4INTG#/GPIO35 AE2INTH#/GPIO36 AE3
LOCK# V5
PCIE_PVSSP25
PCICLK5/GPIO41 T3
BMREQ#/REQ5#/GPIO65 AD7
NB_HT_CLKPM24
LDT_PGF22LDT_STP#G25
GPP_CLK3NP22
INTRUDER_ALERT# C2
NB_DISP_CLKPK23
25M_48M_66M_OSCL18
GPP_CLK0PJ19
NB_HT_CLKNM25
SLT_GFX_CLKNM22
GPP_CLK3PN22
25M_X1J21
25M_X2J20
NB_DISP_CLKNK22
PROCHOT#F24
C331 10P_0402_25V8K@ 1 2
R18510K_0402_5%@
12
D4BAS40-04_SOT23-3
1
23
R464 33_0402_5%U1L@
12
R403 22_0402_5%1 2
C600 0.1U_0402_16V7K
C592 10P_0402_25V8K@ 1 2
R16910K_0402_5%@
12
C591
0.1U_0402_16V7K~N
1 2
U28
NC7SZ08P5X_NL_SC70-5U1H@
B 2
A 1Y4
P5
G3
R426
20M_0603_5%@
12
C5851U_0603_10V6K
1
2
C34
122
U_0
805_
6.3V
6M
1
2
C594 10P_0402_25V8K@ 1 2
C345 0.1U_0402_16V7K
R166 2.05K_0402_1% 12
R448 22_0402_5%1 2
TP39
C363 0.1U_0402_16V7K
TP48
R428 10K_0402_5%@1 2
R450 22_0402_5%1 2
C601 0.1U_0402_16V7K
R452 562_0402_1% 12
R78510_0603_5%
1 2
R790_0603_5%
@1 2
C34
21U
_060
3_10
V6K
1
2
R451 22_0402_5%1 2
R167 22_0402_5%1 2
TP49 JBATT1
ACES_20385-0001CONN@
+ 1-2
C593 10P_0402_25V8K@ 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SMB_CK_CLK0
SMB_CK_DAT0
EC_SWI#EC_SCI#
SLP_S3#SLP_S5#PWRBTN_OUT#SB_PWRGD
EC_RSMRST#
SB_TEST1SB_TEST0EC_GA20KB_RST#
PCIE_WAKE#
H_THERMTRIP#
SB_SPKRSMB_CK_CLK0SMB_CK_DAT0
CLK_USBCLK_EXT
SB_HD_SYNC
SB_HD_BITCLKSB_HD_SDOUT
OVCUR#1
EC_LID_OUT#
OVCUR#0
OVCUR#3
EC_SMI#NC_PWR_EN#
SB_TEST2
SB_HD_RST#
HD_SDIN3
HD_SDIN0
SB_SPKR
SMB_CK_CLK1SMB_CK_DAT1
SMB_CK_CLK1
SMB_CK_DAT1
NB_PWRGD_SB
SUS_STAT#
SUS_STAT#
EC_RSMRST#
SB_TEST2
SB_TEST1
SB_TEST0
SLP_S3#<28>SLP_S5#<28>
PWRBTN_OUT#<28>SB_PWRGD<6,11,28>
EC_SWI#<28>EC_SCI#<28>
EC_RSMRST#<28>
KB_RST#<28>EC_GA20<28>
PCIE_WAKE#<22,24,25,28>
H_THERMTRIP#<6>
SB_SPKR<27>
SMB_CK_DAT0<8,9,14>SMB_CK_CLK0<8,9,14>
USB20P1- <30>
USB20P0- <30>
USB20P1+ <30>
USB20P0+ <30>
USB20P2- <30>USB20P2+ <30>
CLK_USBCLK_EXT <14>
HD_SYNC<27>
OVCUR#0<30>
EC_LID_OUT#<28>
OVCUR#1<30>
EC_SMI#<28>
HD_BITCLK<27>HD_SDOUT<27>
HD_SDIN3<27>
NC_PWR_EN#<24>
HD_RST#<21,27>
GP16 <21>GP17 <21>
CPU_SID_SBCPU_SIC_SB
IDE_RST#<23>
SMB_ALERT#<6>
USB20P7-USB20P7+
USB20P6- <24>USB20P6+ <24>
USB20P8+USB20P8-
USB20P9+ <24>USB20P9- <24>
NB_PWRGD_SB<11>
SUS_STAT#<11>
USB20P3+ <30>USB20P3- <30>
USB20P4+ <29>USB20P4- <29>
USB20P5-USB20P5+
USB20P10-USB20P10+
USB20P11+USB20P11-
OVCUR#3<30>
SMB_CK_CLK1<24>SMB_CK_DAT1<24>
+3VS_VDD33_18
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SB700 USB/ACPI/AC97/GPIO
Custom
18 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
DDR/CLK
R440 10K_0402_5%1 2
R43610K_0402_5%
12
R147 100K_0402_5%1 2
R159 2.2K_0402_5%@1 2
TP33
TP34
R429 0_0402_5%
12
R161 2.2K_0402_5%1 2
R492 10K_0402_5%1 2
R170 2.2K_0402_5%1 2
R17133_0402_5% 1 2
R490 2.2K_0402_5%1 2
R192 10K_0402_5%1 2
R43733_0402_5% 1 2
USB
2.0
Part 4 of 5SB700
ACPI
/ W
AKE
UP
EVEN
TS
GPI
O
HD
AU
DIO
USB
OC
USB
1.1
USB
MIS
C
INTE
GR
ATED
uC
INTE
GR
ATED
uC
USB700D
218S7EALA11FG_BGA528_SB700~D
USBCLK/14M_25M_48M_OSC C8
USB_RCOMP G8
USB_OC6#/IR_TX1/GEVENT6#B9
USB_HSD5P C12USB_HSD5N D12
USB_HSD4P B12USB_HSD4N A12
USB_HSD3P G12USB_HSD3N G14
USB_HSD2P H14USB_HSD2N H15
USB_HSD1P A13USB_HSD1N B13
USB_HSD0P B14USB_HSD0N A14
USB_OC4#/IR_RX0/GPM4#A8USB_OC3#/IR_RX1/GPM3#A9
USB_OC1#/GPM1#F8 USB_OC2#/GPM2#E5
USB_HSD7P G11USB_HSD7N H12
USB_HSD6P E12USB_HSD6N E14
USB_OC0#/GPM0#E4
DDR3_RST#/GEVENT7#G5
SATA_IS0#/GPIO10AE18
AZ_SDIN3/GPIO46M3
PCI_PME#/GEVENT4#E1RI#/EXTEVNT0#E2
SLP_S3#F5SLP_S5#G1PWR_BTN#H2PWR_GOODH1SUS_STAT#K3
TEST1H4TEST0H3GA20IN/GEVENT0#Y15KBRST#/GEVENT1#W15
SMBALERT#/THRMTRIP#/GEVENT2#J6
LPC_PME#/GEVENT3#K4LPC_SMI#/EXTEVNT1#K24S3_STATE/GEVENT5#F1SYS_RESET#/GPM7#J2WAKE#/GEVENT8#H6
RSMRST#D3
CLK_REQ3#/SATA_IS1#/GPIO6AD18
NB_PWRGDW14
SMATVOLT1/SATA_IS2#/GPIO4AA19
SMARTVOLT2/SHUTDOWN#/GPIO5Y19
SPKR/GPIO2W21SCL0/GPOC0#AA18SDA0/GPOC1#W18
DDC1_SCL/GPIO9AA20DDC1_SDA/GPIO8Y18
AZ_BITCLKM1AZ_SDOUTM2
AZ_SYNCL6AZ_RST#M4
USB_HSD9P A11USB_HSD9N B11
USB_HSD8P C10USB_HSD8N D10
LLB#/GPIO66C1
AZ_DOCK_RST#/GPM8#L5
SLP_S2/GPM9#H7
USB_OC5#/IR_TX0/GPM5#B8
BLINK/GPM6#F2
SCL1/GPOC2#K1SDA1/GPOC3#K2
TEST2H5
CLK_REQ0#/SATA_IS3#/GPIO0W17
AZ_SDIN2/GPIO44L8 AZ_SDIN1/GPIO43J8 AZ_SDIN0/GPIO42J7
CLK_REQ1#/SATA_IS4#/FANOUT3/GPIO39V17CLK_REQ2#/SATA_IS5#/FANIN3/GPIO40W20
USB_FSD13P E6USB_FSD13N E7
USB_FSD12P F7USB_FSD12N E8
USB_HSD11P H11USB_HSD11N J10
USB_HSD10P E11USB_HSD10N F11
IMC_GPIO9 B18IMC_PWM0/IMC_GPIO10 F21
SCL2/IMC_GPIO11 D21SDA2/IMC_GPIO12 F19
SCL3_LV/IMC_GPIO13 E20SDA3_LV/IMC_GPIO14 E21
IMC_PWM1/IMC_GPIO15 E19IMC_PWM2/IMC_GPO16 D19IMC_PWM3/IMC_GPO17 E18
IMC_GPIO18 G20IMC_GPIO19 G21IMC_GPIO20 D25IMC_GPIO21 D24IMC_GPIO22 C25IMC_GPIO23 C24IMC_GPIO24 B25IMC_GPIO25 C23
IMC_GPIO0H19IMC_GPIO1H20SPI_CS2#/IMC_GPIO2H21IDE_RST#/F_RST#/IMC_GPO3F25
IMC_GPIO4D22IMC_GPIO5E24IMC_GPIO6E25IMC_GPIO7D23
IMC_GPIO8 A18
IMC_GPIO26 B24IMC_GPIO27 B23IMC_GPIO28 A23IMC_GPIO29 C22IMC_GPIO30 A22IMC_GPIO31 B22IMC_GPIO32 B21IMC_GPIO33 A21IMC_GPIO34 D20IMC_GPIO35 C20IMC_GPIO36 A20IMC_GPIO37 B20IMC_GPIO38 B19IMC_GPIO39 A19IMC_GPIO40 D18IMC_GPIO41 C18
R182 10K_0402_5% 1 2
R15711.8K_0402_1%
1 2
R438 2.2K_0402_5%@1 2
R44133_0402_5% 1 2
R160 2.2K_0402_5%@1 2
R491 2.2K_0402_5%1 2
R15833_0402_5% 1 2
R162 0_0402_5%@ 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SATA_DTX_IRX_N0
SATA_DTX_IRX_P0 SATA_DTX_C_IRX_P0
SATA_DTX_C_IRX_N0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0 SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_DRX_P1
SATA_DTX_IRX_P1 SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1
SATA_DTX_IRX_N1
SATA_ITX_DRX_N1
SATA_DTX_C_IRX_N1
SATA_DTX_IRX_P1
IDEDA12
IDEDA1IDEDA0
IDEIOR#A
EC_THERM#
SATA_X1
IDEIRQA
SATA_ITX_DRX_N0
SATA_X2
EC_THERM_SB#
IDEDA8
SATA_DTX_IRX_P0
IDEDA15
IDEDA9
IDEDA4
IDEDACK#A
IDECS#A1
IDEDA5
IDESAA2IDESAA1
SATA_LED#
SATA_X1
IDEDA13
IDEDA2
IDEIORDYA
IDESAA0
TEMP_COMM
SATA_ITX_DRX_P1SATA_ITX_DRX_N1
IDEDA7
TEMP_COMM
SATA_DTX_IRX_N0
SATA_CAL
IDEDA3
+PLLVDD_ATA
IDEDA6
IDEDA14
IDEDA11IDEDA10
IDECS#A3
IDEIOW#ASATA_DTX_IRX_N1
+XTLVDD_ATA
SATA_X2
SATA_ITX_DRX_P0
IDEREQA
SB_NB_THRMDA
SATA_DTX_C_IRX_N0 <23>
SATA_DTX_C_IRX_P0 <23>
SATA_ITX_C_DRX_N0 <23>
SATA_ITX_C_DRX_P0 <23>
SATA_ITX_C_DRX_N1 <23>
SATA_ITX_C_DRX_P1 <23>
SATA_DTX_C_IRX_P1 <23>
SATA_DTX_C_IRX_N1 <23>
IDEIRQA <23>
IDEDACK#A <23>
IDECS#A1 <23>
IDEIORDYA <23>
IDEDA[0..15] <23>
IDEIOW#A <23>
EC_THERM# <28>
SATA_LED#<29>
IDEIOR#A <23>
IDESAA1 <23>
SB_NB_THRMDC <11>
IDESAA0 <23>
IDEREQA <23>
IDECS#A3 <23>
SB_NB_THRMDA <11>
+1.2V_HT
+3VS
+5VS
+3VALW
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SB700 IDE/SATA
Custom
19 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
close to connector
close to connector
TEMP_COMM 10mil trace
0.1A
C290
0.1U
_040
2_16
V7K~
N1
2
G
DS
Q50 SSM3K7002FU_SC70-3
2
13
C607 0.01U_0402_16V7K
12
R1831K_0402_1% 12
L30
KC FBM-L11-201209-221LMAT_0805
1 2
C375
1U_0
402_
6.3V
6K
1
2
ATA
66/1
00/1
33
Part 2 of 5SB700
SATA
PW
RSE
RIA
L AT
A
SPI R
OM
HW
MO
NIT
OR
USB700B
218S7EALA11FG_BGA528_SB700~D
IDE_IORDY AA24IDE_IRQ AA25
IDE_A0 Y22IDE_A1 AB23IDE_A2 Y23
IDE_DACK# AB24IDE_DRQ AD25IDE_IOR# AC25
IDE_IOW# AC24IDE_CS1# Y25IDE_CS3# Y24
IDE_D0/GPIO15 AD24IDE_D1/GPIO16 AD23IDE_D2/GPIO17 AE22IDE_D3/GPIO18 AC22IDE_D4/GPIO19 AD21IDE_D5/GPIO20 AE20IDE_D6/GPIO21 AB20IDE_D7/GPIO22 AD19IDE_D8/GPIO23 AE19IDE_D9/GPIO24 AC20
IDE_D10/GPIO25 AD20IDE_D11/GPIO26 AE21IDE_D12/GPIO27 AB22IDE_D13/GPIO28 AD22IDE_D14/GPIO29 AE23IDE_D15/GPIO30 AC23
XTLVDD_SATAW12
PLLVDD_SATAAA11
SATA_TX2PAB12SATA_TX2NAC12
SATA_RX2PAD12 SATA_RX2NAE12
SATA_TX3PAD13SATA_TX3NAE13
SATA_RX3PAC14 SATA_RX3NAB14
SATA_TX0PAD9SATA_TX0NAE9
SATA_RX0NAB10SATA_RX0PAC10
SATA_TX1PAE10SATA_TX1NAD10
SATA_RX1NAD11SATA_RX1PAE11
SATA_CALV12
SATA_X1Y12
SATA_X2AA12
SATA_ACT#/GPIO67W11
SPI_DI/GPIO12 G6SPI_DO/GPIO11 D2
SPI_CLK/GPIO47 D1SPI_HOLD#/GPIO31 F4
SPI_CS1#/GPIO32 F3
FANOUT1/GPIO48 M5FANOUT2/GPIO49 M7
FANIN0/GPIO50 P5FANIN1/GPIO51 P8FANIN2/GPIO52 R8
LAN_RST#/GPIO13 U15ROM_RST#/GPIO14 J1
VIN0/GPIO53 A4VIN1/GPIO54 B4VIN2/GPIO55 C4VIN3/GPIO56 D4VIN4/GPIO57 D5VIN5/GPIO58 D6VIN6/GPIO59 A7VIN7/GPIO60 B7
TEMPIN0/GPIO61 B6TEMPIN1/GPIO62 A6TEMPIN2/GPIO63 A5
TEMPIN3/TALERT#/GPIO64 B5
FANOUT0/GPIO3 M8
AVDD F6
AVSS G7
TEMP_COMM C6
SATA_TX4PAE14SATA_TX4NAD14
SATA_RX4NAD15SATA_RX4PAE15
SATA_TX5PAB16SATA_TX5NAC16
SATA_RX5NAE16SATA_RX5PAD16
R3834.7K_0402_5%
12
R124 0_0402_5%1 2
C387
10P_0402_50V8J
12
C613 0.01U_0402_16V7K
12
C609 0.01U_0402_16V7K
12
C608 0.01U_0402_16V7K
12
R3934.7K_0402_5%
12C369
1U_0
402_
6.3V
6K
1
2
L31
KC FBM-L11-201209-221LMAT_0805
1 2
C237 0.01U_0402_16V7K
12
C236 0.01U_0402_16V7K
12
L50
MBK1608301YZF_0603
1 2
R22210M_0402_5%
12
C351
1U_0
402_
6.3V
6K
1
2
C569
2.2U
_060
3_10
V6K1
2
C614 0.01U_0402_16V7K
12
R39410K_0402_5%
12
C606 0.01U_0402_16V7K
12
TP37
Y225MHZ_12P_X8A025000FC1H-H
12
C278100P_0402_25V8K
C388
10P_0402_50V8J
12
+1.2VALW_SB
+3VALW_SB
+1.2V_USBPHY
+V5_VREF
+V5_VREF
+3VS_VDDQ_SB
+3VS_VDD33_18
+AVDDC
+PCIE_VDDR
+1.2V_AVDD_SATA
+3VS_AVDDTX
+1.2V_CKVDD
+1.2V_VDD_SB
+AVDDC
+AVDDCK_1.2V
+AVDDCK_3.3V
+AVDDCK_1.2V
+AVDDC
+3VS
+5VS
+3VS
+1.2VALW
+3VALW
+1.2V_HT
+3VS
+1.8VS
+3VALW
+1.2V_HT
+1.2V_HT
+3VS
+1.2V_HT
+1.2V_HT
+3VS
+1.2V_HT
+PCIE_VDDR
+3VS_VDD33_18
+1.2VALW
+3VS
+1.2V_HT
+3VS
+3VALW+1.2VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SB700 Power/GND
Custom
20 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
0.6A
0.1A
+1.8VS : FLASH MEMORY MODE(DEFAULT)+3VS : IDE MODE
0.8A
0.2A
0.2A
0.01A
0.22A
0.6A
0.45A
0.2A
0.01A
For A11 version this power should connected to +1.2VALW due to PWRBTN no response issue.
C303
1U_0
402_
6.3V
4Z1
2
C612
22U
_080
5_6.
3VAM
1
2
C366
1U_0
402_
6.3V
4Z1
2
C330
0.1U
_040
2_16
V7K~
N
1
2
C306
2.2U
_060
3_10
V6K1
2
R118 0_0805_5%@12
L52
KC FBM-L11-201209-221LMAT_0805@
1 2
SB700
GR
OU
ND
Part 5 of 5
USB700E
218S7EALA11FG_BGA528_SB700~D
VSS_4 D7
VSS_2 A25
VSS_21 M13
VSS_10 K16VSS_11 L4
VSS_1 A2
VSS_17 L16
VSS_8 K9VSS_9 K11
VSS_46 AB1
VSS_13 L10VSS_14 L11VSS_15 L12VSS_16 L14
VSS_18 M6VSS_19 M10VSS_20 M11
VSS_22 M15VSS_23 N4
VSS_26 P6VSS_27 P9VSS_28 P10VSS_29 P11
VSS_32 R1VSS_33 R2VSS_34 R4
VSS_36 R10VSS_37 R12
VSS_3 B1
VSS_35 R9
VSS_30 P13
AVSS_SATA_15AB13
AVSS_SATA_18AC8
AVSS_SATA_5V11
AVSS_SATA_11Y17
AVSS_SATA_19AD8
VSS_31 P15
VSS_24 N12
AVSS_SATA_14AB11
AVSS_SATA_2U10AVSS_SATA_3U11
AVSS_SATA_1T10
AVSS_SATA_17AB17
AVSS_SATA_4U12
AVSS_SATA_12AA9
AVSS_SATA_6V14
AVSS_SATA_10Y14
AVSS_SATA_7W9AVSS_SATA_8Y9
AVSS_SATA_16AB15
AVSS_SATA_20AE8
AVSS_SATA_13AB9
AVSS_USB_5D9
AVSS_USB_8D14
AVSS_USB_4D8 AVSS_USB_3C14
AVSS_USB_6D11AVSS_USB_7D13
AVSS_USB_2B15
AVSS_USB_21K10
AVSS_USB_10E15
AVSS_USB_20J15
AVSS_USB_22K12
AVSS_USB_11F12AVSS_USB_12F14
AVSS_USB_23K14
AVSS_USB_16J9 AVSS_USB_15H17
AVSS_USB_19J14
AVSS_USB_14H9
AVSS_USB_1A15
AVSS_USB_24K15
VSS_12 L7
AVSS_USB_17J11AVSS_USB_18J12
VSS_7 H8
VSS_25 N14
VSS_6 G19
AVSS_USB_13G9
AVSS_USB_9D15
AVSSCK L17
PCIE_CK_VSS_3J22
PCIE_CK_VSS_14 U20PCIE_CK_VSS_13 U18PCIE_CK_VSS_12 T17
PCIE_CK_VSS_18 W19PCIE_CK_VSS_6M17
PCIE_CK_VSS_11 R19
PCIE_CK_VSS_8P16 PCIE_CK_VSS_7M21
PCIE_CK_VSS_17 V21PCIE_CK_VSS_16 V20PCIE_CK_VSS_15 V18
VSS_50 AE24
PCIE_CK_VSS_21 W25
PCIE_CK_VSS_19 W22PCIE_CK_VSS_20 W24
AVSSCF9
PCIE_CK_VSS_2J17 PCIE_CK_VSS_1H18
PCIE_CK_VSS_4K25
VSS_5 F20
PCIE_CK_VSS_5M16
PCIE_CK_VSS_9 P23PCIE_CK_VSS_10 R16
VSS_49 AE1
VSS_44 V6VSS_45 Y21
VSS_42 U4
VSS_48 AB25VSS_47 AB19
VSS_41 T14
VSS_43 U14
VSS_38 R14VSS_39 T11VSS_40 T12
AVSS_SATA_9Y11
C289
0.1U
_040
2_16
V7K~
N
1
2
C327
1U_0
402_
6.3V
4Z
1
2
C270
2.2U
_060
3_10
V6K1
2
R163 0_0805_5%12
L51
KC FBM-L11-201209-221LMAT_08051 2
C611
1U_0
402_
6.3V
4Z1
2
C353
0.1U
_040
2_16
V7K~
N
1
2
L23
FBM-L11-321611-260-LMT_12061 2
C304
1U_0
402_
6.3V
4Z1
2
C318
0.1U
_040
2_16
V7K~
N
1
2
C287
0.1U
_040
2_16
V7K~
N
1
2
C324
1U_0
402_
6.3V
4Z
1
2
C291
1U_0
402_
6.3V
4Z
1
2
C309
1U_0
402_
6.3V
4Z
1
2
C285
1U_0
402_
6.3V
4Z
1
2C321
1U_0
402_
6.3V
4Z1
2
C590
2.2U
_060
3_10
V6K1
2
C349
1U_0
402_
6.3V
4Z1
2
L24
KC FBM-L11-201209-221LMAT_08051 2
R482 0_0402_5%@ 1 2
L22
FBM-L11-321611-260-LMT_1206
@1 2
C348
1U_0
402_
6.3V
4Z
1
2
C305
2.2U
_060
3_10
V6K1
2C347
1U_0
402_
6.3V
4Z1
2
C286
1U_0
402_
6.3V
4Z1
2
C282
22U
_080
5_6.
3VAM
1
2
C364
1U_0
402_
6.3V
4Z1
2
C302
2.2U
_060
3_10
V6K1
2
R483 0_0402_5%1 2
R4891K_0402_5% 1 2
C325
0.1U
_040
2_16
V7K~
N
1
2
C573
22U
_080
5_6.
3VAM
1
2
C307
1U_0
402_
6.3V
4Z1
2
L21
KC FBM-L11-201209-221LMAT_08051 2
C3191U
_040
2_6.
3V4Z1
2
C586
2.2U
_060
3_10
V6K1
2
C271
22U
_080
5_6.
3VAM
1
2
L27
FBM-L11-321611-260-LMT_12061 2
C3670.
1U_0
402_
16V7
K~N
1
2
C604
22U
_080
5_6.
3VAM
1
2C328
1U_0
402_
6.3V
4Z
1
2
L26
KC FBM-L11-201209-221LMAT_08051 2
C610
22U
_080
5_6.
3VAM
1
2
R119 0_0805_5%12
R3960_0805_5%@
12
C365
1U_0
402_
6.3V
4Z
1
2
C301
10U
_080
5_6.
3V6M
1
2
C329
1U_0
402_
6.3V
4Z
1
2
L61
KC FBM-L11-201209-221LMAT_08051 2
C570
1U_0
402_
6.3V
4Z
1
2
C346
1U_0
402_
6.3V
4Z1
2
C323
0.1U
_040
2_16
V7K~
N
1
2
L20
KC FBM-L11-201209-221LMAT_0805@1 2
C589
2.2U
_060
3_10
V6K1
2
C320
0.1U
_040
2_16
V7K~
N
1
2
C572
1U_0
402_
6.3V
4Z
1
2
C288
1U_0
402_
6.3V
4Z1
2
L62
FBM-L11-321611-260-LMT_12061 2
D28RB751V-40TE17_SOD323-2
2 1
C322
1U_0
402_
6.3V
4Z1
2
C308
0.1U
_040
2_16
V7K~
N
1
2
C370
1U_0
402_
6.3V
4Z
1
2
C350
1U_0
402_
6.3V
4Z
1
2
C283
22U
_080
5_6.
3VAM
1
2
C368
0.1U
_040
2_16
V7K~
N
1
2
Part 3 of 5SB700
POWER
PCI/G
PIO
I/O
CO
RE
S0
3.3V
_S5
I/OC
OR
E S5
A-LI
NK
I/OSA
TA I/
O
USB
I/O PL
LC
LKG
EN I/
O
IDE/
FLSH
I/O
USB700C
218S7EALA11FG_BGA528_SB700~D
VDDQ_2M9
VDDQ_6U17
VDDQ_3T15
VDDQ_11AB5
VDDQ_1L9
VDDQ_4U9VDDQ_5U16
VDDQ_12AB21
VDDQ_10AA4
VDDQ_7V8VDDQ_8W7VDDQ_9Y6
S5_3.3V_1 A17S5_3.3V_2 A24S5_3.3V_3 B17S5_3.3V_4 J4S5_3.3V_5 J5
S5_1.2V_2 G4S5_1.2V_1 G2
USB_PHY_1.2V_1 A10USB_PHY_1.2V_2 B10
V5_VREF AE7
AVDDCK_3.3V J16
AVDDCK_1.2V K17
AVDDC E9
AVDDTX_0A16AVDDTX_1B16AVDDTX_2C16AVDDTX_3D16
AVDDTX_5E17 AVDDTX_4D17
AVDDRX_2F18
AVDDRX_0F15
AVDDRX_5G18 AVDDRX_4G17
PCIE_VDDR_4P21 PCIE_VDDR_3P20
PCIE_VDDR_7R25
PCIE_VDDR_2P19
PCIE_VDDR_5R22
PCIE_VDDR_1P18
PCIE_VDDR_6R24
AVDD_SATA_1AA14AVDD_SATA_4AB18AVDD_SATA_2AA15AVDD_SATA_3AA17AVDD_SATA_5AC18AVDD_SATA_6AD17AVDD_SATA_7AE17
VDD_1 L15VDD_2 M12VDD_3 M14VDD_4 N13VDD_5 P12VDD_6 P14VDD_7 R11
VDD_9 T16VDD_8 R15
AVDDRX_1F17
AVDDRX_3G15
VDD33_18_2AA21
VDD33_18_4AE25 VDD33_18_3AA22
VDD33_18_1Y20CKVDD_1.2V_2 L22CKVDD_1.2V_1 L21
CKVDD_1.2V_4 L25CKVDD_1.2V_3 L24
S5_3.3V_7 L2S5_3.3V_6 L1
C326
1U_0
402_
6.3V
4Z
1
2
C352
1U_0
402_
6.3V
4Z
1
2
C292
1U_0
402_
6.3V
4Z
1
2
L57
KC FBM-L11-201209-221LMAT_08051 2
R3950_0805_5% 12
C284
0.1U
_040
2_16
V7K~
N
1
2
C6051U_0402_6.3V4Z
1
2
R148 0_0805_5%@12
C571
22U
_080
5_6.
3VAM
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI_AD26PCI_AD30 PCI_AD24PCI_AD27 PCI_AD23PCI_AD25
PCI_AD[0..31]
PCI_AD31
PCI_AD28
PCI_AD29
PCICLK3_R<17>
GP17<18>
PCICLK2_R<17>
RTC_CLK<17>HD_RST#<18,27>
LPC_CLK1<17>
GP16<18>
LPC_CLK0<17>
PCI_AD[0..31] <17,22>
+3VALW+3VALW +3VALW +3VS +3VS+3VALW +3VALW+3VALW
+3VS +3VS+3VS+3VS +3VS+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SB700 HW Strap
Custom
21 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
REQUIRED STRAPS
WITH A12 SB700, STRAP PIN FOR MEM BOOT AND EC ENABLE SWAPED. I.E. LPC_CLK0 FOR EC ENABLE, AZ_RST# FOR MEM BOOT ENABLE.
LPC_CLK0
ENABLE PCIMEM BOOT
EXT. RTC (PD on X1,apply32KHz toRTC_CLK)DEFAULT
GP17
DISABLE PCIMEM BOOT
PULLLOW
PULLHIGH
INTERNALRTC
DEFAULT
RTC_CLKLPC_CLK1
CLKGENENABLED
DEFAULT
CLKGENDISABLED
AZ_RST#
ECENABLED
ECDISABLEDDEFAULT
GP16PCI_CLK2
BOOTFAILTIMERENABLED
DEFAULT
BOOTFAILTIMERDISABLED
PCI_CLK3
RESERVED
DEFAULT
IGNOREDEBUGSTRAPS
USEDEBUGSTRAPS
PCI_CLK4 PCI_CLK5
RESERVED
L,H = LPC ROM (Default)
H,H = Reserved
H,L = SPI ROM
L,L = FWH ROM
PCI_AD23
No Stuff No Stuff
No Stuff
USE EEPROMPCIE STRAPS
RESERVED
PCI_AD30 PCI_AD29 PCI_AD26
USE DEFAULTPCIE STRAPS
SB700 HAS 15K INTERNAL PU FOR PCI_AD[28:23]
No Stuff
PCI_AD28
USE IDEPLL
RESERVED
PULLLOW
PCI_AD27
BYPASS IDEPLL
USE LONGRESET
BYPASSACPIBCLK
PCI_AD25
No Stuff
No Stuff
USE SHORTRESET
USE ACPIBCLK
PCI_AD24
DEBUG STRAPS
No Stuff
USE PCIPLL
No Stuff
No StuffNo Stuff
No Stuff
RESERVED RESERVED
PCI_AD31
BYPASSPCI PLL
PULLHIGH
No Stuff
TP36
R4012.2K_0402_5%
12
TP41
TP40
R18710K_0402_5%
12
R17410K_0402_5%
12
R47810K_0402_5%
@
12
R47510K_0402_5%
@
12
R17310K_0402_5%@
12
R4742.2K_0402_5%
@1
2
R3972.2K_0402_5%
@
12
R43410K_0402_5%
12
R47710K_0402_5%
@
12
R4352.2K_0402_5%@
12
R4682.2K_0402_5%
@
12
R47610K_0402_5%
@
12
R40010K_0402_5%@
12
R4722.2K_0402_5%
@
12
R4662.2K_0402_5%
@
12
R18810K_0402_5%@
12
R46710K_0402_5%
@
12
R40410K_0402_5%@
12
R43010K_0402_5%
12
R4712.2K_0402_5%
@
12
R17210K_0402_5%
12
R4732.2K_0402_5%
@
12
R3982.2K_0402_5%
12
R18610K_0402_5%
@
12
R40210K_0402_5%
12
R46510K_0402_5%
@
12
R3992.2K_0402_5%@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TPBIAS0
TPBIAS0
XDCE#
SDCMD_MSBS_XDWE#
XDWP
MSDET#_XDDET1#
SD_ENSDWP#_XDRB#
SDDATA2_MSDATA2_XDDATA2
SDDATA0_MSDATA0_XDDATA0
SDDATA3_MSDATA3_XDDATA3
XDDATA6XDDATA5XDDATA4
XDDATA7XDCLEXDALE
R5C833XOR5C833XI
UDIO5
VCC_ROUT
CBS_GRST#
SDDATA1_MSDATA1_XDDATA1
SDDET#_XDDET0#
SDCLK_MSCLK_XDRE#
UDIO4
VCC_ROUT
R5C833XI
PCI_AD30
PCI_AD28PCI_AD29
PCI_AD26PCI_AD25
PCI_AD27
PCI_AD31
PCI_AD22PCI_AD21
PCI_AD17
PCI_AD24
PCI_AD20
PCI_AD23
PCI_AD18
PCI_AD14PCI_AD15PCI_AD16
PCI_AD19
PCI_AD7
PCI_AD13
PCI_AD11
PCI_AD9PCI_AD10
PCI_AD12
PCI_AD5
PCI_AD1PCI_AD2
PCI_AD8
PCI_AD4
PCI_AD6
PCI_AD3
PCI_AD0
PCI_FRAME#
PCI_STOP#
PCI_PAR
PCI_AD21 PCI_IDSELPCI_DEVSEL#
PCI_IRDY#PCI_TRDY#
PCI_SERR#PCI_PERR#
PCI_RST#
CLK_PCI_CB
CLK
_PC
I_C
B_TE
RM
CBS_GRST#
IEEE1394_TPAP0IEEE1394_TPAN0IEEE1394_TPBP0IEEE1394_TPBN0
IEEE1394_TPAP0IEEE1394_TPAN0
IEEE1394_TPBP0IEEE1394_TPBN0
SDDET#_XDDET0#
SDDATA1_MSDATA1_XDDATA1SD_MS_XDDATA1
SD_MS_XDDATA2SDDET#_XDDET0#
SD_EN
SDDET#_XDDET0#
MSDET#_XDDET1# XDDET0#
SDCLK_MSCLK_XDRE#
XDDET0#
XDCE#SDCMD_MSBS_XDWE#
SDDATA2_MSDATA2_XDDATA2
SDDATA3_MSDATA3_XDDATA3SDCLK_MSCLK_XDRE#
SD_MS_XDDATA1SD_MS_XDDATA2
MSDET#_XDDET1#
SDCMD_MSBS_XDWE#
SDDATA0_MSDATA0_XDDATA0
SDWP#_XDRB#
SDDATA0_MSDATA0_XDDATA0
SDCLK_MSCLK_XDRE#
SDDET#_XDDET0#
SDDATA1_MSDATA1_XDDATA1
SDDATA3_MSDATA3_XDDATA3SDCMD_MSBS_XDWE#
SDDATA2_MSDATA2_XDDATA2
SDWP#_XDRB#
XDCE#
XDWP
XDALEXDCLE
SDCMD_MSBS_XDWE#
SDCLK_MSCLK_XDRE#
SDDATA0_MSDATA0_XDDATA0
SDDATA2_MSDATA2_XDDATA2SDDATA3_MSDATA3_XDDATA3
XDDATA6
SDDATA1_MSDATA1_XDDATA1
XDDATA4XDDATA5
XDDATA7
XDDET0#
R5C833XO
CARD_LED# <29>
SIRQ <17,28>
PCI_AD[0..31]<17,21>
PCI_CBE#0<17>
PCI_CBE#3<17>PCI_CBE#2<17>PCI_CBE#1<17>
PCI_PAR<17>PCI_FRAME#<17>PCI_TRDY#<17>PCI_IRDY#<17>PCI_STOP#<17>PCI_DEVSEL#<17>
PCI_PERR#<17>PCI_SERR#<17>
PCI_GNT#0<17>PCI_REQ#0<17>
PCI_RST#<17,24>CLK_PCI_CB<17>
PM_CLKRUN#<17,28>
PCI_PIRQE#<17>PCI_PIRQF#<17>
PCIE_WAKE#<18,24,25,28>
+3VS_CB
+3VS_CB
+3VS_CB
+3VS_CB
+3VS_CB
+3VS_PHY
+3VS
+3VS_SD
+3VS_XD
+3VS_PHY
+3VS_CB
+3VS_SD
+3VS_CB
+5VS
+5VS
+3VS_SD+3VS
+3VS_CB
+3VS_XD+3VS
+3VS_SD
+3VS
+3VS_XD
+3VS
+3VS_SD
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
R5C833 Media Card/1394
22 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Layout Note: Place close to R5C833 Chip
Layout Note: Place close to R5C833.
MDIO19 XDALE
MSCDAT2MSCDAT1
MSCDAT3SDCDAT3
MMC Card
MTEST
XDPWRXDR/B#
XDLED#
SD,MMC,MS,XD muti-function pin define
XDCDAT1
XDCD0#
XDRE#
MDIO12MDIO11
MMCCD#
MMCPWR
MMCLED#
XDCDAT5XDCDAT4
MDIO10MDIO09MDIO08
XDCDAT3XDCDAT2
MDIO07MDIO06MDIO05MDIO04MDIO03
XDWE#
MDIO02MDIO01
XDCE#
XDWP#
MDIO18MDIO17
MS Card
MSCD#
MDIO16MDIO15MDIO14
MSWR
MMCDAT0
XDCDAT7XDCDAT6
MMCCMDMMCCLK
MDIO13
XDCLE
MDIO00Media I/F XD Card
MSLED#
MSCDAT0
MSBSMSCCLK
XDCDAT0SDCDAT0SDCDAT1SDCDAT2
SDCD#
SDPWR0SDPWR1SDLED#
SDCCMD
SD Card
SDCCLK
XDCD1#
SDWP#
Pull-up Pull-up Pull-up
MSENUDIO4UDIO3 XDEN
Pull-up
FunctionFunction set pin define
EnableSD,XD,MS,MMC Card
Layout Note: Place close to R5C833 and Shield GND.
Place close to JSD1.
MMCDAT1MMCDAT2MMCDAT3MMCDAT4MMCDAT5MMCDAT6MMCDAT7
2007-02-12 Protect Circuit for ALPS conn
R215 100_0402_5%1 2
R22
5
10K_0402_1%
12
R205 100_0402_5%1 2
C460 0.01U_0402_16V7K@
1 2
R211 22_0402_5%1 2
R314 100_0402_5%1 2
R207 100_0402_5%1 2
J139A1
P-TWO_CU8042-A0G1G-PCONN@
TPB-1 TPB+2 TPA-3 TPA+4
GND 5GND 6
R276
56.2_0603_1%
12 R305
2.2K_0402_5%@
12
R278 0_0402_5%1 2
R2360_0805_5%@
12
R206 100_0402_5%1 2
R289 100_0402_5%1 2
D9RB751V_SOD323
2 1
R268
56.2_0603_1%
12
R303 100_0402_5%1 2
C458
15P_0402_50V8J
12
R202 100_0402_5%1 2
C4561U_0603_10V6K
1
2
X1
24.576MHz_16P_3XG-24576-43E1
12
R265
10_0402_5%
@
12
R255100_0402_5%
1 2
C436
0.1U_0402_16V7K~N
1
2
C437
1000P_0402_50V7K~N
1
2
C455
0.01U_0402_16V7K
1
2
C414
0.01U_0402_16V7K
1
2R301100K_0402_5%
12
C429
0.01U_0402_16V7K
1
2
R313 100_0402_5%1 2
R290 100_0402_5%1 2
C413
0.01U_0402_16V7K
1
2
R23533K_0402_5%
12
C428
0.01U_0402_16V7K
1
2
C450
0.47U_0603_16V7K
1
2
C461
10U_0805_6.3V6M
1
2
U12
SN74CBT1G384_SOT23-5GND 3OE4 A 1
VCC 5B2
R291 100_0402_5%1 2
R269
56.2_0603_1%
12
R214 100_0402_5%1 2
R2540_0805_5%
12
C451
0.01U_0402_16V7K
1
2
C39
00.
01U
_040
2_16
V7K
1
2
C423
10U_0805_6.3V6M
1
2
C39
71U
_060
3_10
V6K
1
2
R203 100_0402_5%1 2
C376
0.01U_0402_16V7K
1
2
C422
4.7P_0402_50V8C
@
1
2
C439
0.33U_0603_10V7K
1
2
R311 100_0402_5%1 2
R292 22_0402_5%1 2
R271 10K_0402_5%1 2
R294 100_0402_5%1 2
R304 100_0402_5%1 2
R208 100_0402_5%1 2
G
DS
Q29SI2303BDS-T1-E3_SOT23-3~D
2
13
C416
0.01U_0402_16V7K
1
2
R312 100_0402_5%1 2
R277
56.2_0603_1%
12
R270 0_0402_5%@1 2
R300 10K_0402_5%1 2
R297 100_0402_5%1 2
R279
5.1K_0603_1%
12
C435
0.01U_0402_16V7K
1
2
R212150K_0402_5%
12
R298100K_0402_5%
12
R204 39_0402_5%1 2
D8RB751V_SOD3232 1
R296 100_0402_5%1 2
R295 100K_0402_5%1 2
R5C833
U17
R5C833-TQFP128P_TQFP128_14X14~D
AD31125AD30126AD29127AD281AD272AD263AD255AD246AD239AD2211AD2112AD2014AD1915AD1817AD1718AD1619AD1536AD1437AD1338AD1239AD1140AD1042AD943AD844AD746AD647AD548AD449AD350AD251AD152AD053
VCC_PCI3V 10VCC_PCI3V 20
VCC_RIN 61
VCC_ROUT 16VCC_ROUT 34
VCC_3V 67
VCC_MD3V 86
AVCC_PHY3V 98AVCC_PHY3V 106AVCC_PHY3V 110
TPBIAS0 113
MDIO00 80
MDIO03 77MDIO04 76MDIO05 75MDIO06 74MDIO07 73
MDIO10 82MDIO11 81MDIO12 93MDIO13 90
FIL0 96
VREF 100REXT 101
MDIO08 88MDIO09 84
MDIO01 79MDIO02 78
MDIO14 91MDIO15 89MDIO16 92MDIO17 87MDIO18 85MDIO19 83
C/BE3#7C/BE2#21C/BE1#35C/BE0#45
PAR33FRAME#23TRDY#25IRDY#24STOP#29DEVSEL#26IDSEL8PERR#30SERR#31
RSV97
TEST66 HWSPND#69
INTA#115INTB#116
PCICLK121PCIRST#119GBRST#71CLKRUN#117PME#70
REQ#124GNT#123
AGND111 AGND107 AGND103
GND 4GND 13GND 22GND 28
UDIO0/SRIRQ# 72UDIO1 60UDIO2 56UDIO3 65UDIO4 59UDIO5 57
XI 94XO 95
MSEN 58XDEN 55
AGND102 AGND99
GND 54GND 62GND 63GND 68GND 118GND 122
VCC_PCI3V 32VCC_PCI3V 27
VCC_PCI3V 41
VCC_ROUT 114VCC_ROUT 64
VCC_ROUT 120
VCC_PCI3V 128
AVCC_PHY3V 112
TPAP0 109TPAN0 108
TPBP0 105TPBN0 104
C412
10U_0805_6.3V6M
1
2
C3894.7P_0402_50V8C
@
1
2
R210 100_0402_5%1 2
R316 100_0402_5%1 2
C447
270P_0402_50V7K
1
2
R213 100_0402_5%1 2C
421
0.01U_0402_16V7K
1
2
C415
0.01U_0402_16V7K
1
2
U14
RT9701-CB_SOT23-5
VIN3VIN/CE4 VOUT 1
VOUT 5
GND2
R209 100_0402_5%1 2
R299 0_0402_5%@1 2
C445
0.1U_0402_16V7K~N
1
2
C457
0.01U_0402_16V7K
1
2
R267 10K_0402_5%
1 2
L36
BLM21AG601SN1D_0805~D
1 2
C420
0.47U_0603_16V7K
1
2
C446
0.01U_0402_16V7K
1
2
U13
SN74CBT1G384_SOT23-5GND 3OE4 A 1
VCC 5B2
C378
0.01U_0402_16V7K
1
2
R315 100_0402_5%1 2
R274 100K_0402_5%
1 2
R22310_0402_5%
@
12
C452
10U_0805_6.3V6M
1
2
JSD1
ALPS_SCDE2B0101_46PCONN@
MS-D213MS-D012MS-D111BS10VSS9
VDD19CLK8VSS6D04D13
SCLK16
D225
CMD22
VSS18
MS-D315
CD/D324
VCC17
VSS20
INS14
WP_SW46
CD_SW1COMMDN2
GND 26
GND 27R/-B 29-RE 30-CE 31CLE 32ALE 33-WE 34-WP 35GND 36
D0 37D1 38D2 39D3 40D4 41D5 42D6 43D7 44
VCC 45
CD 28
NC 5NC 7NC 23NC 21
R234 100K_0402_5%1 2
R293 100_0402_5%1 2
C377
0.01U_0402_16V7K
1
2
R302 0_0402_5%1 2
R27510K_0402_5%
12
C459
15P_0402_50V8J
12
R22433K_0402_5%
@12
C438
0.01U_0402_16V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SATA_ITX_C_DRX_N1SATA_ITX_C_DRX_P1
SATA_DTX_C_IRX_P1SATA_DTX_C_IRX_N1
SATA_ITX_C_DRX_N0SATA_ITX_C_DRX_P0
SATA_DTX_C_IRX_P0SATA_DTX_C_IRX_N0
IDEREQA
IDEIRQA
IDECS#A1IDECS#A3
IDEDA12
IDEDA14
IDEDA13
IDEDA9
IDEDA11
IDEDA8
IDEDA10
IDEDACK#A
IDEIOR#A
IDE_FLASH_RST#
IDE_FLASH_RST#
IDESAA1
IDEDA15 IDEDA1
IDEDA3
IDEDA0
IDEDA2
IDEDA5
IDEDA4
IDEDA7
IDEDA6
IDESAA0
IDEIOW#A
IDEDA[0..15]
SATA_ITX_C_DRX_N1<19>SATA_ITX_C_DRX_P1<19>
SATA_DTX_C_IRX_P1<19>SATA_DTX_C_IRX_N1<19>
SATA_ITX_C_DRX_N0<19>SATA_ITX_C_DRX_P0<19>
SATA_DTX_C_IRX_P0<19>SATA_DTX_C_IRX_N0<19>
IDECS#A3<19>
IDEIRQA<19>IDEDACK#A<19>
IDEIOR#A<19>
IDECS#A1 <19>
IDEREQA<19>
IDEDA[0..15]<19>
IDESAA0 <19>
IDESAA1 <19>
IDEIOW#A <19>
IDEIORDYA <19>
IDE_RST#<18>
NB_RST#<11,17,24,25,28>
+5VS
+5VS
+3VS
+5VS
+5VS
+3VS
+1.8VS_FLASH +1.8VS
+1.8VS_FLASH
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
SATA HDD/CDROM
Custom
23 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
SATA HDD CONN
CDROM CONN
Close to ODD Conn
Close to SATA HDD
80mils
26ohm 500mA
Pin2, 20 is NC for Flash module
C404
1000P_0402_50V7K~N@
1
2
+C394
150U_D2_6.3VM1
2
JHF1
MOLEX_78188-0001~DCONN@
PDCS3#1PDA22PIDE_INTR3PDACK#4RSVD5PDIOR#6RSVD7PDREQ8PDD159PDD1410RSVD11PDD1312PDD1213RSVD14PDD1115PDD1016RSVD17PDD918PDD819PDDMA6620
PDCS1# 21PDA0 22RSVD 23PDA1 24
PDIORDY# 25RSVD 26
PDIOW# 27PDD0 28PDD1 29PDD2 30RSVD 31PDD3 32PDD4 33RSVD 34PDD5 35PDD6 36RSVD 37PDD7 38
F_RST# 39RSVD 40
GND 42GND41C374
0.1U_0402_16V7K~N
1
2
C385
0.1U_0402_16V7K~N
1
2
C386
1000P_0402_50V7K~N
1
2
C40
522
U_0
805_
6.3V
6M
1
2
JODD1
SUYIN_127382FR013S52_NR
GND1RX+2RX-3GND4TX-5TX+6GND7
DP85V95V10MD11GND12
GND 14GND 15
GND13
C407
1U_0402_6.3V6K
1
2
C180
1U_0
603_
10V6
K
1
2
L32
BLM31AJ260SN1L_1206~D
12
C406
1U_0402_6.3V6K
1
2
R24620K_0402_1%
12
JSATA1
SUYIN_127043FR022G226ZLCONN@
GNDS1HTX+S2HTX-S3GNDS4HRX-S5HRX+S6GNDS7
VCC3.3P1VCC3.3P2VCC3.3P3GNDP4GNDP5GNDP6VCC5P7VCC5P8VCC5P9GNDP10RESERVEDP11GNDP12VCC12P13VCC12P14VCC12P15
GND 23GND 24GND 25GND 26
NC 27NC 28
C396
0.1U_0402_16V7K~N@
1
2
C181
1000
P_04
02_5
0V7K
~N
1
2
D10 RB751V-40TE17_SOD323-2
21
C395
0.1U_0402_16V7K~N@
1
2
C163
0.1U
_040
2_16
V7K~
N
1
2
C403
10U_0805_10V4Z~N@
1
2
R2278.2K_0402_5%
12
C373
10U
_080
5_10
V4Z~
N
1
2
C162
10U
_080
5_10
V4Z~
N
1
2
D11 RB751V-40TE17_SOD323-2
@
21
PCIE_PERST#
NB_RST#
NC_CPUSB#
NC_CPPE#
PCIE_CARD_C_RX_N2PCIE_CARD_C_RX_P2
PCIE_CARD_C_TX_N2PCIE_CARD_C_TX_P2
SMB_CK_CLK1SMB_CK_DAT1
PCIE_PERST#
USB20P6+_RUSB20P6-_R
NC_PWR_EN#
NC_PWR_EN#
NC_CPUSB#
CLK_PCI_MINIPCI_RST#
LPC_FRAME#
LED_WLAN#
LPC_AD0LPC_AD1
LPC_AD3LPC_AD2
USB20P9+USB20P9-
W_DISABLE#
PCIE_C_RXN1PCIE_C_RXP1
NB_RST#
CLK_PCI_MINI
SMB_CK_DAT1SMB_CK_CLK1
USB20P6+<18>USB20P6-<18>
CLK_PCIE_CARD#<14>CLK_PCIE_CARD<14>
PCIE_CARD_C_TX_N2<10>PCIE_CARD_C_TX_P2<10>
PCIE_CARD_C_RX_N2<10>PCIE_CARD_C_RX_P2<10>
SMB_CK_CLK1<18>SMB_CK_DAT1<18>
NB_RST#<11,17,23,25,28>
CLKREQ_54CARD#<14>
SUSP#<28,32,38,39>
SYSON<28,32,37>
PCIE_WAKE#<18,22,25,28>
NC_PWR_EN#<18>
CLK_PCIE_WCARD<14>CLK_PCIE_WCARD#<14>
NB_RST# <11,17,23,25,28>
PCIE_WLAN_C_TX_N1<10>PCIE_WLAN_C_TX_P1<10>
PCIE_WLAN_C_RX_P1<10>PCIE_WLAN_C_RX_N1<10>
CLKREQ_MINICARD#<14>
USB20P9- <18>USB20P9+ <18>
CLK_PCI_MINI<17>
LPC_AD1 <17,28>LPC_AD2 <17,28>
LPC_AD0 <17,28>
LPC_AD3 <17,28>LPC_FRAME# <17,28>
PCI_RST#<17,22>
LED_WLAN# <29>
W_DISABLE# <28,29>
WLAN_P#<28>
+3V_CARD_AUX
+1.5V_CARD +3V_CARD
+1.5VS+3VS+3VALW
+3VALW
+3V_CARD_AUX
+3V_CARD +1.5V_CARD
+1.5VS
+3VS
+3VALW
+3VS
+1.5VS +3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
KB / TP / Express Card
Custom
24 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
1A 1.5A
0.5A
Placement Closed to JMINI1
Mini-Express Card
New Card
JMINI1
ACES_88911-5204CONN@
1133557799111113131515171719192121232325252727292931313333353537373939414143434545474749495151
GND153
2 24 46 68 8
10 1012 1214 1416 1618 1820 2022 2224 2426 2628 2830 3032 3234 3436 3638 3840 4042 4244 4446 4648 4850 5052 52
GND2 54
R181 100K_0402_5%@ 1 2
C410.1U_0402_16V7K~N
1
2
C330.1U_0402_16V7K~N
1
2
R165 100K_0402_5%@ 1 2
R469 0_0402_5%1 2
R50 0_0402_5%1 2
C31
50.
1U_0
402_
16V7
K~N
1
2
C360.1U_0402_16V7K~N
1
2
C4010U_0805_10V4Z~N
1
2
C30
010
U_0
805_
6.3V
6M
1
2
R420_0402_5%
1 2
C320.1U_0402_16V7K~N
1
2
C36
10.
1U_0
402_
16V7
K~N
1
2
R5310_0402_5%@
12
C350.1U_0402_16V7K~N
1
2
R49 0_0402_5%1 2
R52 0_0402_5%1 2
C31
30.
1U_0
402_
16V7
K~N
1
2
R453 0_0402_5%
12
R484 0_0402_5%1 2
R470 0_0402_5%
12
C31
60.
1U_0
402_
16V7
K~N
1
2
R15310K_0402_5%12
R470_0402_5%
1 2R460_0402_5%
1 2
R44 0_0402_5%1 2
U9
P2231NF_QFN20
3.3Vin23.3Vin4 3.3Vout 3
3.3Vout 5
SYSRST#6
SHDN#20
STBY#1
PERST# 8
OC# 19
RCLKEN18
AUX_IN17 AUX_OUT 15
CPPE#10
CPUSB#9
NC 16
GND 7
1.5Vin121.5Vin14 1.5Vout 11
1.5Vout 13
R442 0_0402_5%
12
C35
90.
1U_0
402_
16V7
K~N
1
2
C4310U_0805_10V4Z~N
1
2
R480_0402_5%
1 2
C34
00.
1U_0
402_
16V7
K~N
1
2
C3410P_0402_25V8K@1
2
C36
00.
1U_0
402_
16V7
K~N
1
2
R443 0_0402_5%
12
C31
40.
1U_0
402_
16V7
K~N
1
2
C36
210
U_0
805_
6.3V
6M
1
2
R43 0_0402_5%1 2
R450_0402_5%1 2
C440.1U_0402_16V7K~N
1
2
R51 0_0402_5%1 2
C31
70.
1U_0
402_
16V7
K~N
1
2
R485 0_0402_5%1 2
JEXP1
FOX_1CH4310C-KL_RB
11223344556677889910101111121213131414151516161717181819192020212122222323242425252626
GND 27
GND 28
GND 29
GND 30
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTALI
XTALO
LAN_WP
LAN_DATALAN_CLK
PCIE_MRX_C_LTX_N0
MDIP0
PCIE_MRX_C_LTX_P0
LAN_DATACS#
MDIN2
SI
XTALIXTALO
MDIP3
LAN_CLK
LOW_PWRCBE#1
CTL12
MDIN0
MDIP1MDIN1
MDIN3
MDIP2
CLKREQ#
EN_WOL
CTL12
GPIO2
SUPER_IDDQ
LAN_WP
LAN_LOW_PWR
LAN_LOW_PWR
CLK_PCIE_LAN#<14>
PCIE_LAN_C_RX_P0<10>
CLK_PCIE_LAN<14>
PCIE_LAN_C_TX_P0<10>PCIE_LAN_C_RX_N0<10>
PCIE_LAN_C_TX_N0<10>PCIE_WAKE#<18,22,24,28>
NB_RST#<11,17,23,24,28>
CLKREQ_LAN#<14>
MDIP3 <26>
MDIN1 <26>
MDIP2 <26>
MDIP1 <26>
MDIN0 <26>
MDIN3 <26>
MDIN2 <26>
MDIP0 <26>
EN_WOL#<28>
LAN_LOW_PWR <28>
CABLE_DET <28>
+3VS+3VLAN
+3VLAN
+1.2VLAN
+AVDDL
+PCIE_PLLVDDL
+PCIE_VDDL
+GPHY_PLLVDDL
+1.2VLAN
+3VLAN
+AVDDL
+3VLAN+3VLAN
+1.2VLAN_IO
+1.2VLAN_IO
+1.2VLAN
+GPHY_PLLVDDL
+PCIE_PLLVDDL
+PCIE_VDDL
+3VLAN
+BIASVDDH
+AVDDH
+XTALVDDH
+3VLAN
+BIASVDDH
+XTALVDDH
+AVDDH
+3VALW
B+_BIAS
+3VLAN
+1.2VLAN
+3VLAN
+3VLAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
BroadCom LAN bcm5784M
Custom
25 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Layout Notice : Filter place as closechip as possible.
Layout Notice : 3.3V filter. Place as closechip as possible.
Layout Notice : 1.2V filter. Place as closechip as possible.
C50
60.
1U_0
402_
16V4
Z
1
2
L40 FBM-L11-160808-601LMT_060312
L43 FBM-L11-160808-601LMT_060312
C24
22U
_080
5_6.
3VAM
@
1
2
Y1
25MHZ_16P_XSL025000FK1H
1 2
C50
80.
1U_0
402_
16V4
Z
1
2C
497
0.1U
_040
2_16
V4Z
1
2
C180.1U_0402_16V4Z 1
2
C51110U_0805_10V4Z~N
1
2
C29
0.1U
_040
2_10
V7K~
N
1
2
C504 0.1U_0402_16V4Z1 2
R370_0402_5%@1 2
C25
22U
_080
5_6.
3VAM
1
2
C231U_0603_10V6K
1
2
C512
0.1U_0402_16V4Z
1
2
C50
30.
1U_0
402_
16V4
Z
1
2
C224.7U_0805_6.3V6K 1
2
C5000.1U_0402_16V4Z
1
2
C124.7U_0805_6.3V6K
1
2
R360_0402_5%@ 1 2
R26 47K_0402_1%12
C170.1U_0402_16V4Z 1
2
R32470K_0402_5%
12
C30 0.1U_0402_16V4Z 1 2
C50
90.
1U_0
402_
16V4
Z
1
2
C20
4.7U
_080
5_10
V4Z~
N
1
2
C50
50.
1U_0
402_
16V4
Z
1
2
R311.5M_0402_5%@
12
U21
AT24C02N-10SU-2.7_SO8
A0 1A1 2NC 3
GND 4
VCC8WP7SCL6SDA5
R25 47K_0402_1%12
C21 0.1U_0402_16V7K~N
12C4990.1U_0402_16V4Z 1
2
S
GD
Q5
SI3456BDV-T1-E3_TSOP6
3
6
245
1
G
D
S
Q6SSM3K7002FU_SC70-3
2
13
R39 0_0402_5%1 2
R350_0402_5%@ 1 2
R33
84.
7K_0
402_
5%
@
12R340 4.7K_0402_5%1 2
C4950.1U_0402_16V4Z 1
2
L42 FBM-L11-160808-601LMT_060312
C50
70.
1U_0
402_
16V4
Z
1
2
C160.1U_0402_16V4Z 1
2
R23 1.24k_0402_1%1 2
R34
14.
7K_0
402_
5%1
2
C49
80.
1U_0
402_
16V4
Z
1
2
L3FBMA-L11-322513-201LMA40T_1210
1 2
C27
27P_
0402
_50V
8J
1
2
R34 0_0402_5%@12
R30200_0603_1%
12
C26 0.1U_0402_16V7K~N
12
C50
10.
1U_0
402_
16V4
Z
1
2
R40 0_0402_5%@12
R41 0_0402_5%1 2
U5
BCM5784MA0KMLG_QFN68_10x10
TRD3_N 49TRD3_P 50
TRD2_N 47TRD2_P 46
TRD1_N 43TRD1_P 44
TRD0_N 41TRD0_P 40
RDAC37
LINKLED# 2SPD100LED# 1
SPD1000LED# 67TRAFFICLED# 66
XTALI21 XTALO22
VDDC34 VDDC20 VDDC13 VDDC_IO55 VDDC_IO5
VAUX_PRSNT54
TEST158TEST257
VDD
IO6
VDD
IO56
VDD
IO61
CS# 62SO_EEDATA 64SI 63SCLK_EECLK 65
XTALVDDH 23
DC
38
AVDDL51
AVDDL39
BIASVDDH 36
GPHY_PLLVDDL35
DC
68
PCIE_TXD_P26PCIE_TXD_N25PCIE_RXD_P31PCIE_RXD_N32
PCIE_REFCLK_P29PCIE_REFCLK_N28
VMAIN_PRSNT53
PERST#10
PCIE_PLLVDDL30PCIE_PLLVDDL27
WAKE#12
LOW_PWR3
ENERGY_DET 59
REGOUT12_IO 18
VDDC60
VDD
IO15
PCIE_VDDL33
AVDDL45
DC
52
CLK_REQ#11
SUPER_IDDQ 16
PCIE_VDDL24
UART_MODE 9GPIO1_SERIALDI 7
GPIO0_SERIALDO 4
GPIO2 8
REGCTL12 14
VDDC_IO 17
VDD
IO19
AVDDH 42AVDDH 48
GND69
R29 4.7K_0402_5%1 2
C51
04.
7U_0
805_
6.3V
6K
1
2
C49
60.
1U_0
402_
16V4
Z
1
2
L44 FBM-L11-160808-601LMT_060312
C134.7U_0805_6.3V6K
1
2
L41 FBM-L11-160808-601LMT_060312
R380_0402_5%@ 1 2
R22 1K_0402_5% 1 2
L46 FBM-L11-160808-601LMT_060312
C50
20.
1U_0
402_
16V4
Z
1
2
R270_0402_5%@ 12
L45 FBM-L11-160808-601LMT_060312
Q40
MMJT9435T1G_SOT223-4~D
1
23
4
R33 1.5_1206_5%1 2
C28
27P_
0402
_50V
8J
1
2
C140.1U_0402_16V4Z 1
2
C49
40.
1U_0
402_
16V4
Z
1
2
C31 4.7U_0805_10V4Z~N
1 2
R28 4.7K_0402_5%1 2
C194.7U_0805_6.3V6K
1
2
R24 1K_0402_5%
1 2
C150.1U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
MDIN3MDIP3
V_DAC
V_DAC
V_DACMDIN0MDIP0
MDIN2MDIP2
RJ45_TX0+RJ45_TX0-
RJ45_RX1+RJ45_RX1-
RJ45_TX3-RJ45_TX3+
RJ45_TX2-RJ45_TX2+
V_DAC
V_DAC
MDIN1MDIP1
RJ45_TX3+
RJ45_RX1+
RJ45_TX3-
RJ45_RX1-
RJ45_TX0+
RJ45_TX0-
RJ45_TX2+
RJ45_TX2-
MDIP0<25>
MDIN1<25>
MDIN2<25>
MDIN0<25>
MDIP2<25>
MDIP1<25>
MDIN3<25>MDIP3<25>
+3VLAN
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
RJ45 / Hyper Flash
Custom
26 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
C479 0.01U_0402_16V7K1 2
R32849.9_0402_1%@
12
R32749.9_0402_1%
@
12
C478 0.01U_0402_16V7K1 2
T1
BOTH_GST5009-LF
TCT11TD1+2TD1-3
TCT24TD2+5TD2-6 MX2- 19MX2+ 20MCT2 21
MX1- 22MX1+ 23MCT1 24
TCT37TD3+8TD3-9
TCT410TD4+11TD4-12
MCT3 18MX3+ 17MX3- 16
MCT4 15MX4+ 14MX4- 13
R321 0_0805_5%@12
R324 FBM-L11-160808-601LMT_0603@12
R32649.9_0402_1%@
12
R33249.9_0402_1%
@ 12
C4840.01U_0402_16V7K
@
1
2
R32549.9_0402_1%
@
12
R320 0_0805_5%@12
C4631000P_1206_2KV7K
12
R1 0_0805_5%@12
C4850.01U_0402_16V7K
@
1
2
C477 0.01U_0402_16V7K1 2
JLAN1
FOXCONN_JM36113-L0R7-7FCONN@
PR1-2
PR1+1
PR2+3
PR3+4
PR3-5
PR2-6
PR4+7
PR4-8
NC9
NC10
NC11
NC12
SHLD1 13
SHLD2 14
SHLD2 16
SHLD1 15
R33049.9_0402_1%
@1
2
RP17
75_1206_8P4R_5%
18273645
C4860.01U_0402_16V7K@
1
2
R32949.9_0402_1%@
12
R33149.9_0402_1%
@ 12
C4880.01U_0402_16V7K@
1
2
C476 0.01U_0402_16V7K1 2
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
HD_SYNC
C_MIC2
C_MIC1
HD_SYNC
SDIN_CODEC
HD_RST#
HP_JD
AC_JDREF
AC97_VREF
SPK_L1
SPK_R1
SPK_L2
SPK_R2
HP_OUTRHP_OUTL
PD#
HP_JD
PLUG_IN
PLUG_IN#
HD_RST#
EC_MUTE#
PD#
SPK_L2
SPK_R2
SPK_R1
SPK_L1SPK_L2
SPK_R2SPK_R1
MIC1
MIC2
SPK_L1
BUZZER
SPK_L1
SPK_R1
SPK_L2
SPK_R2
MIC1
MIC2
MIC-1
MIC-2
HP_OUTR
HP_OUTL
HP_R
HPL
HPR
HP_L
PLUG_IN
HD_SYNC <18>
HD_RST#<18,21>
HD_SDOUT <18>
MIC_JD
HD_SDIN3 <18>
HD_BITCLK <18>
EC_MUTE#<28>
BUZR_OFF<28>BEEP#<28>
SB_SPKR<18>
MIC_JD
+VDDA
+VDDA+5VS
+MIC1_VREFO_R
+5VS
+AVDD_AC97
+3VS
+MIC1_VREFO_L
+MIC2_VREFO
+3VS_DVDD +5VS_PVDD
+3VS
+3VS +3VS
+5VS
+5VS_PVDD
+3VS
+MIC1_VREFO_L+MIC1_VREFO_R
GND_AMP
GND_AMP
GND_AMP
GND_AMP
GND_AMP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
Codec ALC262
27 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
20mil
10mil
40mil
Reserved for TEST
GND AGND
Adjustable Output
For EMI
AGND
10mil 10mil
10mil
EAPD Control for Vista
EC Beep
ICH Beep
Speaker Connector
MICROPHONE IN JACK
HEADPHONE OUT JACK
+VDDA=4.5V
Inductor under survey
C63
10.
01U
_040
2_16
V7K
R50320K_0402_1%1 2
R2723K_0402_5% 12
R251 0_0402_5%@12
C6160.1U_0402_16V7K~N
1
2
R495
1M_0402_5%
1 2
C627 2.2U_0603_10V6K1 2
C417 22P_0402_25V8K@1 2
C432 1U_0603_16V6K~N1 2
L68 CHB2012U170_08051 2
L348.2UH_FRH5D28-8R2NNP_1.6A_30%
1 2
C6262.2U_0603_10V6K1 2
U31
SI9182DH-AD-T1-E3_MSOP8~N
VIN4
SD8
VOUT 5
GND 3
SENSE or ADJ 6
ERROR7 CNOISE 1
DELAY2
R493
0_0603_5%
12
L67 CHB2012U170_08051 2
L338.2UH_FRH5D28-8R2NNP_1.6A_30%
1 2
C41
910
P_04
02_2
5V8K
@ 1
2
D12
RB751V-40TE17_SOD323-2 2
1
R499 0_0402_5%1 2
R506 1K_0402_5% 1 2
G
D
S
Q52SSM3K7002FU_SC70-3
2
13
C625
0.1U
_040
2_16
V4Z
1
2
R253 0_0402_5%
@12
C62
94.
7U_0
805_
10V4
Z~N
1
2
G
D
S
Q31SSM3K7002FU_SC70-3
2
13
R257 0_0805_5%
1 2
C418
0.1U_0402_16V7K~N
1
2
R250 0_0402_5%@12
C61
810
P_04
02_2
5V8K
@ 1
2
C621 4.7U_0805_6.3V6K
12
C61
710
P_04
02_2
5V8K
@ 1
2
R286 0_0805_5%
1 2
C425 1U_0603_16V6K~N1 2
C623
470P_0402_50V7K 1
2
C624
10U
_080
5_10
V4Z~
N
1
2
C628
0.1U
_040
2_16
V7K~
N
C424 0.22U_0603_16V4Z1 2
G
D
S
Q30
SSM3K7002FU_SC70-3
2
13
R498 33_0402_5%1 2
C63
00.
1U_0
402_
16V7
K~N
1
2
D29
RB751V_SOD323
21
R262
56.2_0603_1%
12
UA1
ALC269-GR_LQFP48
AVD
D1
25
AVD
D2
38
AVSS1 26AVSS2 37
DVD
D1
DV
DD
_IO
9
DVSS7
PVD
D1
39
PVD
D2
46
PVSS142 PVSS243 CPVEE 34
JDREF 19
VREF 27
MIC1_VREFO_L 28MIC1_VREFO_R 30
MIC2_VREFO 29
CPVREF31
CBN35
CBP36
SENSE A13
SENSE B18
SPK_OUT_L+ 40SPK_OUT_L- 41
SPK_OUT_R+ 45SPK_OUT_R- 44
HP_OUT_L 32HP_OUT_R 33
PCBEEP12
LINE1_L23LINE1_R24
LINE2_L14LINE2_R15
MIC1_L21MIC1_R22
MIC2_L16MIC2_R17
MONO_OUT 20
RESET#11
GPIO0/DMIC_DATA2
GPIO1/DMIC_CLK3
PD#4
SYNC 10
BCLK 6
SDATA_OUT 5
SDATA_IN 8
EAPD/SPDIFO2 47
SPDIFO 48
AGN
D49
C440 0.22U_0603_16V4Z1 2
R259 0_0402_5%@ 1 2
L35FBM-L11-160808-800LMT_0603
12
R249 0_0805_5%
1 2
R501
100K
_040
2_5%
1
2
C430 0.22U_0603_16V4Z1 2
R260
0_0402_5%
1 2
C620 4.7U_0805_6.3V6K
12
R500
100K
_040
2_5%
1
2
R496 39.2K _0402_1%12 C443
220P_0402_50V7K
1
2
JSPK1
ACES_88266-04001~NCONN@
11223344 G1 5
G2 6
U29
74LVC1G125GW_SOT353-5
I2 O 4
P5
G3
OE#
1
L65 CHB2012U170_08051 2
C622470P_0402_50V7K 1
2
+
-
BUR1
LET9040-03A_2P
45@
12
G
D
S
Q51SSM3K7002FU_SC70-3
2
13
R502 20K_0402_1%12
R505 62_0603_1%1 2
R508 10K_0402_5%1 2
JMIC1
FOX_JA6333L-B3S0-7F~N
CONN@
12
3
4
5
6 78910R497 33_0402_5%
1 2
C444
220P_0402_50V7K
1
2
C433
0.1U_0402_16V7K~N
1
2
L64 CHB2012U170_08051 2
R28727K_0603_1%
12
R507 1K_0402_5% 1 2
R28810K_0603_1%
12
C442
0.1U_0402_16V7K~N
1
2
L638.2UH_FRH5D28-8R2NNP_1.6A_30%
1 2L66
8.2UH_FRH5D28-8R2NNP_1.6A_30%1 2
C427
0.1U_0402_16V7K~N
1
2
R266 0_0805_5%
1 2
C44110U_0805_10V4Z~N
1
2
C61910U_0805_6.3V6M
1
2
R263
56.2_0603_1%
12
C61510U_0805_6.3V6M
1
2
C434
0.1U_0402_16V7K~N
1
2
C410
0.1U_0402_16V7K~N
1
2
C42610U_0805_10V4Z~N
1
2
R504 62_0603_1%1 2
C431 0.22U_0603_16V4Z1 2
R2733K_0402_5% 12
C449
4.7U
_080
5_10
V4Z~
N
R258 0_0805_5%
12
R494
10_0402_5%
1 2JHP1
FOX_JA6333L-B3S0-7F~N
CONN@
12
3
4
5
6 78910
R261
0_0402_5%
1 2
U30
NC7SZ08P5X_NL_SC70-5
B2
A1 Y 4
P5
G3
C411
0.1U_0402_16V7K1
2
R252 0_0402_5%12
G
D
S
Q32AP2301GN 1P SOT23
2
13
R264 0_0805_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
KSI6
KSI1KSI0
KSI5
KSI2
KSI[0..7]
KSI3
KSI7
KSI4
KSO12
KSO14KSO15
KSO6
KSO13
KSO11
KSO[0..15]
KSO4
KSO0
KSO3
KSO8
KSO5
KSO1
KSO9
KSO7
KSO10
KSO2
EC_SMI#
SW_CONFIG1
EC_SMB_CK1EC_SMB_DA1
EC_SMB_DA2EC_SMB_CK2
EC_PME#
CRY2CRY1
EC_MUTE#
AD_BID0
LPC_AD3LPC_AD2LPC_AD1LPC_AD0
ECAGND
FWR#SPI_SIFRD#SPI_SO
LID_SW#
EC_SCI#
SPI_CLK
ENABLT
FAN_SPEED1
BATT_TEMP
ECAGND
EC_RST#
NB_RST#
CRY1
CRY2
CLK_PCI_EC
TP_CLK
EC_GA20
MSEN#
BATT_OVP
EC_SMB_DA2
SW_CONFIG2
+3VALW_ECVCC
EMAIL_BTN
AD_BID0
EC_SMB_CK2
TP_DATA
SB_PWRGD_EC
NB_RST#
VLDT_EN
TP_CLKTP_DATA
ACIN
BATT_CHG_LED#
FSEL#SPICS#
INTERNET_BTN
EC_PME#
SPI_CS#
EC_SO_SPI_SI EC_SI_SPI_SO
SPI_CLK_R
EC_RX_P80CLK
EC_RX_P80CLKEC_TX_P80DATA
EC_TX_P80DATA
EC_SMB_DA1EC_SMB_CK1
SPI_CLK_R
SPI_CS#SPI_CLK_REC_SO_SPI_SIEC_SI_SPI_SO
KB_RST#
SPI_PD
BUZR_OFF
DIMMER_STATUS
EC_THERM#
SB_PWRGD_EC
EC_SMB_DA1
EC_SMB_CK1
BATT_TEMP
BATT_OVP
ACIN
SW_CONFIG1
SW_CONFIG2
SW_RSV1
INTERNET_BTN
SW_RSV2
EMAIL_BTN
LID_SW#
SOFT_BTN
EC_MUTE#
MSEN#
ECO_BTN
KSI[0..7]<29>
SLP_S3#<18>SLP_S5#<18>
FSTCHG <35>
KSO[0..15]<29>
EC_SMI#<18>
EC_SMB_CK1<6,34>
SUSP#<24,32,38,39>
EC_SMB_DA1<6,34>
EC_ON <31>
EC_SMB_CK2<6>EC_SMB_DA2<6>
INVT_PWM <15>BEEP# <27>
SIRQ<17,22>ACOFF <35>LPC_FRAME#<17,24>
DAC_BRIG <15>
NUMLED#<29>
CLK_PCI_EC<17>
IREF <35>
EC_SCI#<18>PM_CLKRUN#<17,22>
ENABLT <11,15>
LPC_AD[0..3]<17,24>
EN_DFAN1 <4>
EC_GA20<18>
BATT_OVP <35>
EC_MUTE# <27>
PWRBTN_OUT#<18>
SW_CONFIG1<29>SW_CONFIG2<29>
SW_RSV1 <29>
MSEN# <15>
EMAIL_BTN <29>
SB_PWRGD <6,11,18>
NB_RST#<11,17,23,24,25>
FAN_SPEED1<4>
ON_OFF<31>
VLDT_EN <32>
TP_DATA <29>TP_CLK <29>
SYSON <24,32,37>VR_ON <40>
EC_RSMRST# <18>EC_LID_OUT# <18>
EC_SWI# <18>
CAPSLED# <29>
BKOFF# <15>
BATT_CHG_LED# <29>
INTERNET_BTN <29>
ACIN <33,35>
PCIE_WAKE#<18,22,24,25>EN_WOL# <25>
KB_RST#<18>
BATT_LOW_LED# <29>
BUZR_OFF <27>
DIMMER_STATUS <29>
EC_THERM# <19>SCRLED#<29>
PWR_BTN_LED# <29>
USBSW_EN#<30>
LID_SW#<29>
CHGVADJ <35>
SW_RSV2 <29>
WLAN_P# <24>
ADP_I <35>
CABLE_DET <25>
GPLED <29>
USB_EN# <30>ECO_GRN_LED# <29>ECO_BLU_LED# <29>
BATT_TEMP <34>
ECO_BTN <29>
SOFT_BTN <29>
LAN_LOW_PWR <25>
W_DISABLE#<24,29>
VFIX_EN <40>
+EC_AVCC+3VALW+3VALW
+3VALW
+3VALW
+3VALW
+5VS
+EC_AVCC
+3VALW
+3VALW
+3VS
+3VALW
+5VALW
+3VALW
+5VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
KB926&BIOS
Custom
28 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Ra
Rb
FOR Board ID
SPI Flash (8Mb*1)
20mils
Reserve for EMI, close to SPI ROM
2007-02-12 MUST PULL DOWN!
2007-05-02 Support KB926 C0
20mil
EC DEBUGC382
1000P_0402_50V7K~N@
1
2
LPC & MISC
Int. K/B Matrix
SM Bus
GPIO
GPIO
AD Input
PWM Output
DA Output
PS2 Interface
SPI Device Interface
SPI Flash ROM
GPO
GPI
U10
KB926QFC0_LQFP128_14X14
GA20/GPIO001KBRST#/GPIO012SERIRQ#3LFRAME#4LAD35
PM_SLP_S3#/GPIO046
LAD27LAD18
VCC
9
LAD010
GN
D11
PCICLK12PCIRST#/GPIO0513
PM_SLP_S5#/GPIO0714EC_SMI#/GPIO0815LID_SW#/GPIO0A16SUSP#/GPIO0B17PBTN_OUT#/GPIO0C18EC_PME#/GPIO0D19
SCI#/GPIO0E20
INVT_PWM/PWM1/GPIO0F 21
VCC
22
BEEP#/PWM2/GPIO10 23
GN
D24
EC_THERM#/GPIO1125
FANPWM1/GPIO12 26ACOFF/FANPWM2/GPIO13 27
FAN_SPEED1/FANFB1/GPIO1428FANFB2/GPIO1529EC_TX/GPIO1630EC_RX/GPIO1731ON_OFF/GPIO1832
VCC
33
PWR_LED#/GPIO1934
GN
D35
NUMLED#/GPIO1A36
ECRST#37
CLKRUN#/GPIO1D38
KSO0/GPIO2039KSO1/GPIO2140KSO2/GPIO2241KSO3/GPIO2342KSO4/GPIO2443KSO5/GPIO2544KSO6/GPIO2645KSO7/GPIO2746KSO8/GPIO2847KSO9/GPIO2948KSO10/GPIO2A49KSO11/GPIO2B50KSO12/GPIO2C51KSO13/GPIO2D52KSO14/GPIO2E53KSO15/GPIO2F54
KSI0/GPIO3055KSI1/GPIO3156KSI2/GPIO3257KSI3/GPIO3358KSI4/GPIO3459KSI5/GPIO3560KSI6/GPIO3661KSI7/GPIO3762
BATT_TEMP/AD0/GPIO38 63BATT_OVP/AD1/GPIO39 64
ADP_I/AD2/GPIO3A 65AD3/GPIO3B 66
AVC
C67
DAC_BRIG/DA0/GPIO3C 68
AGN
D69
EN_DFAN1/DA1/GPIO3D 70IREF/DA2/GPIO3E 71
DA3/GPIO3F 72
CIR_RX/GPIO40 73CIR_RLC_TX/GPIO41 74
AD4/GPIO42 75SELIO2#/AD5/GPIO43 76
SCL1/GPIO4477SDA1/GPIO4578SCL2/GPIO4679SDA2/GPIO4780
KSO16/GPIO4881KSO17/GPIO4982
PSCLK1/GPIO4A 83PSDAT1/GPIO4B 84PSCLK2/GPIO4C 85PSDAT2/GPIO4D 86
TP_CLK/PSCLK3/GPIO4E 87TP_DATA/PSDAT3/GPIO4F 88
FSTCHG/SELIO#/GPIO50 89BATT_CHGI_LED#/GPIO52 90
CAPS_LED#/GPIO53 91BATT_LOW_LED#/GPIO54 92
SUSP_LED#/GPIO55 93
GN
D94
SYSON/GPIO56 95
VCC
96
SDICS#/GPXOA00 97SDICLK/GPXOA01 98SDIDO/GPXOA02 99
EC_RSMRST#/GPXO03 100EC_LID_OUT#/GPXO04 101
EC_ON/GPXO05 102EC_SWI#/GPXO06 103
ICH_PWROK/GPXO06 104BKOFF#/GPXO08 105
WL_OFF#/GPXO09 106GPXO10 107GPXO11 108
SDIDI/GPXID0 109
PM_SLP_S4#/GPXID1 110
VCC
111
ENBKL/GPXID2 112
GN
D11
3
GPXID3 114GPXID4 115GPXID5 116GPXID6 117GPXID7 118
SPIDI/RD# 119SPIDO/WR# 120
VR_ON/XCLK32K/GPIO57 121
XCLK1122XCLK0123 V18R 124
VCC
125
SPICLK/GPIO58 126
AC_IN/GPIO59 127
SPICS# 128
R221
10_0402_5%@
12
C392
1000P_0402_50V7K~N1
2
C39915P_0402_50V8J
1
2
C393
0.1U_0402_10V7K~N
1 2
R487 10K_0402_5%1 2
R199 10K_0402_5%1 2
R247 15_0402_5%
12
R1940_0402_5%@
12
C4080.47U_0603_16V7K@
1
2
C401
100P_0402_25V8K
R231 10K_0402_5%1 2
R218 4.7K_0402_5% 12
R197 4.7K_0402_5% 12
R230 10K_0402_5%1 2
C337
100P_0402_25V8K
R220 100K_0402_5%@1 2
R243 15_0402_5%
12
R196 10K_0402_5%1 2
C6030.1U_0402_10V7K~N
1
2
R2290_0603_5%@
1 2
JECDB1
ACES_85205-0400CONN@
11223344
R198 4.7K_0402_5% 12
R17656K_0402_5%~N
12
R2400_0402_5%1 2
R177
100K_0402_5%
@
12
R191 10K_0402_5%1 2
U15
AT24C16AN-10SU-2-7 SO 8P @
A0 1A1 2
SDA5 SCL6
VCC8
A2 3GND 4
WP7
R239 4.7K_0402_5%1 2
R200 10K_0402_5%1 2
R1950_0402_5%
12
R479 10K_0402_5%1 2
R219 4.7K_0402_5% 12
R488 10K_0402_5%1 2
R201 0_0402_5%1 2
L28
MBK1608800YZF 06031 2
R242 10K_0402_5%1 2
R486 10K_0402_5%1 2
R232
10K_0402_5%
12
C6024.7U_0805_6.3V6K~N
1
2
R244 15_0402_5%
12
C336
100P_0402_25V8K
C3581000P_0402_50V7K~N
1
2C372
1000P_0402_50V7K~N
1
2
C338
0.1U_0402_16V7K~N1
2
C3560.1U_0402_16V7K~N
1
2
C3810.1U_0402_16V7K~N
@1 2
R179
0_0805_5%
1 2
R237
100K_0402_5%
@12
C384
15P_0402_50V8D@
1
2
R23333_0402_5%@
12
Y3
32.768KHZ_12.5PF_1TJS125BJ4A421P
OU
T4
IN1
NC
3
NC
2
R241 10K_0402_5%1 2
C40222P_0402_50V8J
@
1
2
C398
0.1U_0402_16V7K~N
1
2
C383
0.1U_0402_16V7K~N1
2
L29 MBK1608800YZF 06031 2
R228 0_0603_5%@
1 2
R480 10K_0402_5%1 2
C3570.1U_0402_16V7K~N
1
2R178
47K_0402_5%
1 2
R481 10K_0402_5%1 2
R245 15_0402_5%
12
C40015P_0402_50V8J
1
2
U16
SST25VF080B-50-4C-S2AF_SO8
S1
VCC8
Q 2
HOLD7
VSS 4
D5
C6
W3
R238
100K_0402_5%
@12
C339
0.1U_0402_16V7K~N1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
KSO[0..15]
KSI[0..7]
KSI0
KSO15
KSO14
KSO13
KSO12
KSO11
KSO10
KSI1
KSI3
KSO8
KSI2
KSO9
KSI6
KSI7
KSO0
KSO5
KSO7
KSI5
KSO4
KSO6
KSO3
KSO2
KSI4
KSO1
USBP4_R-
LEC
USBP4_R+
Internet_BTNECO_BTN
KSO9
KSO13
KSI4
KSO10
KSI6
KSO4
KSO8
KSI3
KSI1
KSO0
KSO3
KSO7
KSI2
KSI0
KSO2
KSO6
KSI5
KSO15
KSO1
KSO5
KSO12
KSO14
KSI7
KSO11
+5VS_FP_FE
LID_SW#
W_DISABLE#
WLAN_EN
BATT_LOW_LED#
PWR_BTN_LED#
BATT_CHG_LED#
CARD_LED#
SOFT_BTN
NUMLED#
LED_WLAN#
SATA_LED#
PWR_ON-OFF_BTN#
DIMMER_STATUS
SCRLED#
EMail_BTN
CAPSLED#
ECO_GRN_LED#
PWR_BTN_LED#ECO_BLU_LED#
TP_DATATP_CLK
CLR_CMOS<17>
SW_CONFIG1<28>
SW_CONFIG2<28>
SW_RSV1<28>
SW_RSV2<28>
KSO[0..15] <28>
KSI[0..7] <28>
TP_DATA<28>TP_CLK<28>
USB20P4+<18>USB20P4-<18>
PWR_ON-OFF_BTN#<31>EMail_BTN<28>Internet_BTN<28>ECO_BTN<28>SOFT_BTN<28>
SCRLED#<28>NUMLED#<28>
CAPSLED#<28>SATA_LED#<19>CARD_LED#<22>
ECO_GRN_LED#<28>ECO_BLU_LED#<28>
LED_WLAN#<24>
PWR_BTN_LED#<28>
DIMMER_STATUS<28>
GPLED<28>
LID_SW#<28>
BATT_CHG_LED#<28>
BATT_LOW_LED#<28>
PWR_BTN_LED#<28>
W_DISABLE#<24,28>
+5VS_DIMMER
+5VS_DIMMER
+5VS
+5VS
+5VS
+3VALW
+5VS
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
MINICARD/TPM
Custom
29 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
ONOFF
Dip Switch CONN.
INT_KBD CONN.
(Left)
(Right)
TOUCHPAD CONN.
1AFelica CONN.
Function Brd CONN.
R310 680_0402_5%
1 2
C61 100P_0402_25V8K@
C390.1U_0402_16V7K~N
1
2
JFN2
ACES_85201-20051
1234567891011121314151617181920
C5190.01U_0402_16V7K
1
2
C69 100P_0402_25V8K@
LED1
HT-F194BP5 0603 WHITE
21
C60 100P_0402_25V8K@
C71 100P_0402_25V8K@
C53 100P_0402_25V8K@
R55100K_0402_5%
12
ON
SW1
FHDS-06-T-V-T/R_12P
1
2
3
4
5
6 7
8
9
10
11
12
C55 100P_0402_25V8K@
R307 680_0402_5%
1 2
C59 100P_0402_25V8K@
C40910U_0805_10V4Z~N
1
2
R248 0_0402_5%1 2
S
G
D
Q7AOS3401_SOT23
2
13
R309 390_0603_5%
1 2
G
D
SQ36SSM3K7002FU_SC70-3
2
13
D25
PACDN042Y3R_SOT23-3
@
231
C57 100P_0402_25V8K@
TP42
C73 100P_0402_25V8K@
C74 100P_0402_25V8K@
LED2
HT-F191UY 0603 AMBER
21
JTP1
ACES_85201-08051
GND9GND10
1122334455667788
R54 1M_0402_5%1 2
C52 100P_0402_25V8K@
R56100K_0402_5%@
12
C68 100P_0402_25V8K@
C67 100P_0402_25V8K@
C62 100P_0402_25V8K@
D24
PACDN042Y3R_SOT23-3
@
231
C54 100P_0402_25V8K@
C72 100P_0402_25V8K@C64 100P_0402_25V8K@
D23
PACDN042Y3R_SOT23-3
@
231
C63 100P_0402_25V8K@
C58 100P_0402_25V8K@
JKB1
ACES_85202-24051~NCONN@
112233445566778899101011111212131314141515161617171818191920202121222223232424G125G226
C38
0.1U_0402_16V7K~N1
2
C51
7
100P
_040
2_25
V8K
@1
2
D21
PACDN042Y3R_SOT23-3
@
231
LED3
HT-F191UY 0603 AMBER
21
D22
PJSOT24C_SOT23-3
@
231
C56 100P_0402_25V8K@
F1 1.1A_6VDC_FUSE
21JFE1
ACES_87151-06051~NCONN@
11 22 33 44 55 66 G1 7G2 8
C66 100P_0402_25V8K@
G
D
SQ8
SSM3K7002FU_SC70-3
2
13
LED4
HT-F194BP5 0603 WHITE
21
C51
810
0P_0
402_
25V8
K
@1
2
C371000P_0402_50V7K~N
@
1
2
C65 100P_0402_25V8K@
C421U_0603_10V6K
1 2
R256 0_0402_5%1 2
R308 390_0603_5%
1 2
C70 100P_0402_25V8K@
C51 100P_0402_25V8K@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB_EN#
USB20P1_R+
CON-USBP0-CON-USBP0+
USB_EN#
SUSP
SUSP
USB20P0+
USB20P0- USBP0-_SW
USBP0+_SW
USB20P1_R-
SUSP
USB20P2+
USB20P3-
USB20P0-
USB20P0+
USBP0-_SW
USBP0+_SW
USB20P2-
USB20P3+
OVCUR#0 <18>
OVCUR#3 <18>
USB20P0+<18>
USB20P0-<18>
USBSW_EN#<28>
SUSP<32>
USB_EN#<28>
USB20P1+<18>
USB20P1-<18>
OVCUR#1 <18>
SUSP<32>
SUSP<32>
USB20P3+<18>USB20P3-<18>
USB20P2+<18>USB20P2-<18>
+5VALW
+USB_AS
+USB_AS
+USB_AS
+5VS+USB_CS
+5VS+3VS
+3VALW
+USB_CS
+5VS+USB_BS
+USB_BS+USB_BS
+USB_CS
+USB_AS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
USB Port X3 + Felica
30 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
W=40mils
iPOD Charger when system shutdown
AC/DC
ON
OFF
ON
ON
ON
OFF
ON
OFF
ON
OFF
S0BIOSMENU S3 S4 S5
USB_EN Hi=Enable, Low=Disable IPOD USB power
W=40mils
20mil
W=40mils
板下
沉板
USB Brd CONN.
U22
G548A2P8U_MSOP8
GND1IN2
OC# 5OUT 6
OUT 8
IN3EN#4
OUT 7
J2
OPEN PADS@
1 2
D20CM1293A-04SO_SOT23-6
<Part Type>
CH
36
Vp5
CH
44
CH
23
Vn2
CH
11
+C515
150U_D2_6.3VM
1
2
G
D
S
Q39SSM3K7002FU_SC70-3
2
13
R317470_0805_5%
1
2
L2
WCM-2012-670T_4P
1 122
33 4 4
R1775K_0402_1%U1H@
12
R20 0_0402_5%
U1L@1 2
R342470_0805_5%
12
R319100K_0402_5%@
12
R339470_0805_5%
12
R3180_0402_5%
1 2
U4
FSUSB31K8X_US8U1H@
NC 1
HSD-2 D- 3
GND 4
D+ 5HSD+6
OE#7
VCC8
C492
470P_0402_50V7K1
2
C514
470P_0402_50V7K
1
2
C464
470P_0402_50V7K
1
2
R21 0_0402_5%
U1L@1 2
U19
G548B2P8U_MSOP8
GND1IN2
OC# 5OUT 6
OUT 8
IN3EN#4
OUT 7
C465
470P_0402_50V7K1
2
R140_0603_5%
@
1 2
R337 0_0402_5%U1H@1 2
C513
470P_0402_50V7K1
2
G
D
S
Q38SSM3K7002FU_SC70-3
2
13
L1
WCM-2012-670T_4P
1 122
33 4 4
R343100K_0402_5%@
12
+C2
150U_D2_6.3VM
1
2
+C11
150U_D2_6.3VM
1
2
JUSB3
ACES_87213-0800G
1122334455667788
GND 9
GND 10
G
D
S
Q41SSM3K7002FU_SC70-3
2
13
R322
100K_0402_5%
1 2
R1951K_0402_1%U1H@
12
C493
470P_0402_50V7K
1
2
C516
0.1U_0402_16V7K~N
1
2
C491
0.1U_0402_16V7K~N
1
2
J3OPEN PADS@1
2
C466
0.1U_0402_16V7K~N
1
2
U20
G548B2P8U_MSOP8
GND1IN2
OC# 5OUT 6
OUT 8
IN3EN#4
OUT 7
G
D
SQ3
SSM3K7002FU_SC70-3U1H@
2
13
JUSB2
SUYIN_020167MR004S511ZR
VBUS1D-2D+3GND4
GND7GND8
GND5GND6
R1643K_0402_1%
U1H@
12
R3440_0402_5%
1 2
R336 0_0402_5%@1 2
JUSB1
TYCO 0-1775501-1 4P CONN@
VCC1USB_N2USB_P3GND4GND5GND6GND7GND8
G
DS
Q4AP2301GN 1P SOT23
U1H@
2
13
R1851K_0402_1%U1H@
12
D1CM1293A-04SO_SOT23-6
<Part Type>
CH
36
Vp5
CH
44
CH
23
Vn2
CH
11
R1510K_0603_1%
U1H@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
EC_ON
PWR_ON-OFF_BTN#51ON#
EC_ON<28>
ON_OFF <28>
51ON# <33>PWR_ON-OFF_BTN#<29>
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
PWR_OK/BTN
Custom
31 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
Power Button
H_3P0
H_4P2
Q11DTC124EKAT146_SC59-3
2
13
CF1HOLEA@
1
H10HOLEA@
1
H3HOLEA@
1
H25HOLEA@
1
H8HOLEA@
1
H11HOLEA@
1
H19HOLEA@
1
R113
33K_0402_5%@1 2
R1144.7K_0402_5%
12
CF3HOLEA@
1
H15HOLEA@
1
H32HOLEA@
1
H27HOLEA@
1
H7HOLEA@
1
H5HOLEA@
1
H28HOLEA@
1
H4HOLEA@
1
H23HOLEA@
1
H9HOLEA@
1
H2HOLEA@
1
H31HOLEA@
1
H21HOLEA@
1
D5RLZ20A_LL34
12
H16HOLEA@
1
H17HOLEA@
1
H18HOLEA@
1
H6HOLEA@
1H29HOLEA@
1
R115
100K_0402_5%
12
H33HOLEA@
1
D6
DAN202U_SC70
2
31
CF2HOLEA@
1
H24HOLEA@
1
H26HOLEA@
1
H1HOLEA@
1
H22HOLEA@
1
H13HOLEA@
1
SW2SW TJG-533-V-T/R
3
2
1
4
5 6
CF4HOLEA@
1
SW3SW TJG-533-V-T/R
3
2
1
4
5 6
H34HOLEA@
1
C2651000P_0402_50V7K~N
@
1
2
H14HOLEA@
1
H12HOLEA@
1
H30HOLEA@
1
H20HOLEA@
1
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4SUSPSUSP
DIS
CH
G_3
VS
DIS
CH
G_5
VS
DIS
CH
G_1
.8V
S
SUSP
DIS
CH
G_0
.9V
SYSON#
DIS
CH
G_1
.8V
SYSON#
DIS
CH
G_1
.2V
HT
VLDT_EN#
DIS
CH
G_1
.5V
S
SUSP
SUSP
SUSP
VLDT_EN
VLDT_EN#
RUN_ON
1.2VS_GATE
RUN_ON_1.2
RUN_ON
3VS_GATE RUN_ON
SYSON#
SYSON
1.8VS_GATE
SUSP#<24,28,38,39>
VLDT_EN<28>
SYSON<24,28,37>
SYSON#<6,39>SUSP<30>
+5VS+3VS+1.8VS+1.2V_HT+0.9V +1.8V +1.5VS
+1.2V_HT
+3VALW
+1.2VALW
+5VALW
+5VALW
+1.8V
B+_BIAS
+3VS
+5VS
+5VALW
+5VS
+1.8VS
+5VALW
B+_BIAS
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
DC Interface
Custom
32 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
+1.2VALW TO +1.2V_HT+5VALW TO +5VS
+3VALW TO +3VS
+1.8V TO +1.8VS
G
D
S
Q48
SSM3K7002FU_SC70-3
2
13
G
D
S
Q20
SSM3K7002FU_SC70-3
2
13
C5621U_0603_10V6K
1
2
G
D
S
Q28
SSM3K7002FU_SC70-3
2
13
U11
AO4468_SO8
S 1S 2S 3G 4
D8D7D6D5
G
D
S
Q37
SSM3K7002FU_SC70-3
2
13
R3750_0402_5%1 2 R283
10K_0402_5%
12
R28110K_0402_5%
12
C26410U_0805_10V4Z~N
1
2
C4544.7U_0805_10V4Z~N
1
2
R127100K_0603_5% 1 2
G
D
S
Q35SSM3K7002FU_SC70-3
2
13
C3791U_0603_10V6K
1
2
U7
AO4468_SO8
S 1S 2S 3G 4
D8D7D6D5
R125470_0805_5%
12
R2840_0402_5%
1 2
R28010K_0402_5%
12
U26
AO4468_SO8
S 1S 2S 3G 4
D8D7D6D5
G
D
S
Q23
SSM3K7002FU_SC70-3
2
13
R28210K_0402_5%
12
G
D
S
Q26
SSM3K7002FU_SC70-3
2
13
R126
10K_0402_5%
1 2
C37110U_0805_10V4Z~N
1
2
C5634.7U_0805_6.3V6K~N
1
2C56410U_0805_10V4Z~N
1
2
R151470_0805_5%
12
R12010K_0402_5%
12
R285100K_0603_5% 1 2
C2801U_0603_10V6K
1
2
C5610.22U_0603_10V7K
@
1
2
C4531U_0603_10V6K
1
2
G
D
SQ15
SSM3K7002FU_SC70-3
2
13
G
D
S
Q34SSM3K7002FU_SC70-3
2
13
G
D
S
Q33SSM3K7002FU_SC70-3
2
13
R37610K_0402_5%@
1 2
R175470_0805_5%
12
G
D
S
Q16SSM3K7002FU_SC70-3
2
13
C2794.7U_0805_10V4Z~N
1
2
R226470_0805_5%
12
R384470_0805_5%
12
C3914.7U_0805_10V4Z~N
1
2
R12810K_0402_5%
12
C3800.22U_0603_10V7K
1
2
R306470_0805_5%
12
R2160_0402_5%
1 2
U18
AO4468_SO8
S 1S 2S 3G 4
D8D7D6D5
C2720.1U_0603_25V7K~N
1
2
C46210U_0805_10V4Z~N
1
2
G
D
S
Q49
SSM3K7002FU_SC70-3
2
13
R385470_0805_5%
12
C4480.22U_0603_10V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CHGRTCP
ACIN <28,35>
51ON#<31>
VINADPIN
RTCVREF
VIN
VS
VS
VIN
VS
CHGRTC
BATT+
RTCVREF
+0.9V+0.9VP
+1.1VS+1.1VSP
+VDDNBP +VDDNB
+1.2VALW+1.2VALWP
+1.5VS+1.5VSP
+NB_CORE+NB_COREP
+3VALWP +3VALW
+5VALWP +5VALW +1.8VP +1.8V
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4381P 0.0
Custom
33 41Wednesday, January 16, 2008
2007/12/12 2008/12/12
DCIN / Precharge
3.3V
(2.0A,80mils ,Via NO.=4)
(2A,80mils ,Via NO.= 4)
(3A,120mils ,Via NO.= 6)
(7A,280mils ,Via NO.=14)
(5.0A,200mils ,Via NO.=10)
(3.0A,120mils ,Via NO.=6)
(5A,200mils ,Via NO.= 10)
(5A,200mils ,Via NO.= 10) (8A,320mils ,Via NO.= 16)
Vin Detector
High 14.57 14.01 13.46Low 14.06 13.51 12.98
PC6
0.1U
_040
2_16
V7K~
N
32.3
12
PR261.9K_0402_1%~N
12
PR13
560_0603_5%
1 2
PC2
1000
P_04
02_5
0V7K
~N
12
PR1122K_0402_5%
1 2
PC7
0.1U
_040
2_16
V7K~
N
32.3
12
PC1432200P_0402_50V7K~N@
1 2
PR710K_0402_5%~N
12
PJP5
JUMP_43X118@1 122
PC10
4.7U
_080
5_6.
3V6K
~N12
PJP11
JUMP_43X118@1 122
PR35.6K_0402_5%
12
PR12200_0805_5%
12
PR5
15.4K_0402_1%
1 2
PF110A_65VDC_451010
21
PD3
RLS4148_LLDS2
12
PR8
10K_0402_5%~N
12
PC4
1000
P_04
02_5
0V7K
~N1
2PC3
100P
_040
2_50
V8J~
N 12
PR6
20K_0402_1%~N
12
PR10100K_0402_5%
12
PL1FBMA-L18-453215-900LMA90T_1812
1 2
PJP2
JUMP_43X118@1 122
PJP3
JUMP_43X118@1 122
PC8
0.22
U_1
206_
25V7
K
12
PR11M_0402_1%~N
1 2
PR9
33_1206_5%
12
PC5
0.01
U_0
402_
25V7
K~N
12
PR20356K_0402_5%~N@
1 2
PU1A
LM393DR_SO8~N
+3
-2 0 1
P8
G4
PC9
0.1U_0603_25V7K~N
12
PJP8
JUMP_43X118@1 122
PJP26
JUMP_43X118@1 122
1
2
3
4
PCN1
SINGA_2WA-8291T041
1
2
4
3
PR14
560_0603_5%
1 2
PQ1TP0610K-T1-E3_SOT23-3
32.8
2
13
PJP12
JUMP_43X118@1 122
PJP6
JUMP_43X118@1 122
PU3G920AT24U_SOT89
IN 2
GND
1
OUT3
PC111U_0805_25V4Z
12
PC1
100P
_040
2_50
V8J~
N12
PD2
RLS4148_LLDS2
12
PJP25
JUMP_43X118@1 122
PR410K_0402_1%~N
1 2
PU1B
LM393DR_SO8~N
+ 5
- 607
P8
G4
PD1
RLZ
4.3B
_LL3
4
12
PJP10
JUMP_43X118@1 122
PJP1JUMP_43X118@
11 2 2
PJP4
JUMP_43X118@1 122
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BATT_TEMP
BATT
+
BATT++
BATT_TEMP <28>
EC_SMB_DA1 <6,28>
EC_SMB_CK1 <6,28>
MAINPWON <36>
+3VALWP
BATT++BATT+
+3VALWP
B+_BIAS
+5VALW
B+
VL
VL VS
VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4381P 0.0Custom
34 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
CPU
Recovery at 50 +-3 degree C
PH1 under CPU botten side :CPU thermal protection at 90 +-3 degree C
Battery Connect/OTP
BATTERY CONN
Place clsoe to EC pin
SMARTBattery:
1.BAT+2.BAT+3.ID4.B/I5.TS6.SMD7.SMC8.GND9.GND
PJPB1 battery connector
CPU
PC181U_0603_6.3V6M~N
12
PR2461.9K_0402_1%~N1 2
PR27
470K
_040
2_5%
12
PR28150K_0402_1%~N
12
PR19100_0402_5%
1 2
PC140.1U_0402_16V7K~N
@
12
PR25
100_0805_5%~N
1 2
PC19
0.1U
_060
3_25
V7K~
N 1
2
PR22442K_0402_1%~N1 2
PC150.1U_0603_25V7K~N1
2
PR29
220K
_040
2_5%
12
PR23150K_0402_1%~N
12
PU4A
LM358ADT_SO8~N
+3
-2 0 1
P8
G4
PH1
100K_0603_1%_TH11-4H104FT
12
PC131000P_0402_50V7K~N
12
PD4
1SS355_SOD323-2
1 2
PC171000P_0402_50V7K~N
12
G
D
S
PQ3
RHU002N06_SOT3232
13
PR186.49K_0402_1%
1 2
PR161K_0402_5%
1 2
PR30
220K
_040
2_5%
12
PF215A_65VDC_451015
21
PR2110.7K_0402_1%~N
12
PQ2TP0610K-T1-E3_SOT23-3
32.6
2
13
PL2FBMA-L18-453215-900LMA90T_1812
1 2
PD5
1SS3
55_S
OD
323-
2
32.6
12
PC120.01U_0402_25V7K~N
12
PR20100_0402_5%
1 2
PR26150K_0402_1%~N
1 2
PC16
0.1U
_080
5_25
V7M
~N
12
PJP13
SUYIN_200275MR009G154ZL_RV
BATT+ 1
ID 3B/I 4TS 5
SMD 6
GND- 9GND10GND11
BATT+ 2
SMC 7GND- 8
PR1547K_0402_5%~N
12
PR17
1K_0402_5%12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DL_CHG
24751_SRP
24751_SRN
ACSET
P3
P2
BST_CHGA
RE
GN
/BATDRV
24751_ACN24751_ACP
ACDET
DH_CHG
24751_SRSET
ACGOOD#
24751_BAT
OVPSET
24751_ACDRV
/BATDRV
LX_CHG
CELLS
VADJ
24751_ACOP
CHG_B+
CHGEN#
VADJ
REGN
CHG
ACSET
CHGEN#
ACGOOD#
BST_CHG
IREF <28>
ACOFF <28>
FSTCHG<28>
ACIN <28,33>
BATT_OVP<28>
CHGVADJ<28>
ADP_I<28>
BATT+
VIN
VREF
VREF
B+
VREF
VREF
BATT+
VS
RTCVREF
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
0.0
Charger
B
35 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
JAL70
75W adapter
Input UVP : 17.26V
Fsw : 300KHz
Input OVP : 22.3V
CP setting
ICHG setting
BATT-OVP=0.111*BATT+LI-3S :13.5V----BATT-OVP=1.5V
IREF Current
3.3V 1.65A
CHGVADJ
3.3V
0V
4V+0.105*CHGVADJ
Pre Cell
4.35V
4V
0.4V 0.2A
PQ7FDS4435BZ_SO8
S1
S2
S3
G4
D8
D7
D6
D5
G
D
S
PQ11SSM3K7002F_SC59-3@
2
13
PC260.1U_0402_16V7K~N
1 2
PD6
RLS4148_LLDS2
12
PR310.015_2512_1%
1
3
4
2
PQ6AO4466_SO8
365 7 8
2
4
1
PR35
1_12
10_5
%12
PR34
100K
_040
2_1%1
2 PR380_0603_5%1 2
PC310.1U_0603_25V7K~N
1 2
PC430.01U_0402_25V7K~N
@
12
PQ5FDS4435BZ_SO8
S1S2S3G4
D 8D 7D 6D 5
PC22
4.7U
_120
6_25
V6K~
N
12
PC380.1U_0603_25V7K~N
12
PR5410K_0402_1%~N
12
PR4354.9K_0402_1%
12
PC24
4.7U
_120
6_25
V6K~
N
12
PR50133K_0402_1%
12
PR46100K_0402_1%
@
12
PC32
10U
_120
6_25
V6M
~N
12
PR41100K_0402_1%
12
PU5
BQ24751ARHDR_QFN28_5X5
ACN2ACP3
CHGEN1
ACSET6
IADAPT 15
VADJ12
PGND 22
ACDET5
ACOP7
BAT 17
BATDRV14
CELLS 20
SRN 18
SRP 19
LODRV 23
ACDRV4
VREF10
LEARN 21
SRSET 16
AGND9
VDAC11
OVPSET8
ACGOOD13
PVCC 28
HIDRV 26
PH 25
BTST 27
REGN 24
TP 29
PC23
4.7U
_120
6_25
V6K~
N
12
PR39340K_0402_1%
12
PC210.01U_0603_50V7K~N1
2
PQ8AO4466_SO8
365 7 8
2
4
1
PR33
1_12
10_5
%12
PR4910_0603_5%
1 2
PL310UH_SIL1045RA-100PF_4.5A_30%
1 2
PC44100P_0402_50V8J~N
12
PQ4FDS4435BZ_SO8
S 1S 2S 3G 4
D8D7D6D5
PC351U_0603_10V6K~N
12
PC25
0.01
U_0
402_
25V7
K~N
12
PR534.32K_0402_1%
1 2
PC292.2U_0805_25V6K1
2
PR44100K_0402_1%
1 2
G
D
S
PQ12SSM3K7002F_SC59-3
2
13
PC401U_0603_10V6K~N
12
PC270.1U_0805_25V7M~N1 2
PC45
0.01
U_0
402_
25V7
K~N
12
PR55499K_0402_1%
12
PU4B
LM358ADT_SO8~N
+ 5
- 607
P8
G4
PR360.02_2512_1%
1
3
4
2
PR48100K_0402_1%
@
12
PC340.01U_0402_25V7K~N
12
PC200.01U_0402_25V7K~N1
2
PC410.1U_0603_25V7K~N
12
PR52453K_0402_1%
12
PR32100K_0402_1%
12
PR510_0402_5%@
12
PQ9SI2301BDS-T1-E3_SOT23-3
2
13
PJP14
JUMP_43X118@1 122
PR56100K_0402_1%
12
PR47
270K_0402_1%12
PR42340K_0402_1%
12
PC300.1U_0603_25V7K~N
12
PR5786.6K_0402_1%
12
PC370.1U_0402_16V7K~N
1 2
PR3754.9K_0402_1%
12
PC420.1U_0603_25V7K~N
12
PC280.1U_0603_25V7K~N@
12
PR4080.6K_0402_1%
1 2
PR197
0_0402_5%
12
PC390.1U_0603_25V7K~N@
12
PC360.47U_0603_16V7K~N
1 2
PC33
10U
_120
6_25
V6M
~N
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ILIM2
BST3A BST5A
LX5
DL5
FB3
2VR
EF_
ISL6
237
2VR
EF_
ISL6
237
DH5DH3
EN_LDO
LX3
FB5
ILM1EN1
DL3
3-5V_B23-5V_B1
MAINPWON<34>
POK <39>
VL
VL
ISL6237_B+
VS
+3VALWP
+5VALWP
B+
VL
2VREF_ISL6237
ISL6237_B+
VL
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4381P 0.0Custom
36 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
+3VALWP, +5VALWP
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
3.3VALWPImax=5A
Iocp=9A
5VALWPImax=5A
Iocp=9A
PQ36TP0610K-T1-E3_SOT23-3
2
1 3
PL6
4.7UH_SIL104R-4R7PF_5.7A_30%12
PC
6068
0P_0
603_
50V
7K
@
12
PQ15AO4712_SO8
36 578
2
4
1
+ PC61330U_D3L_6.3VM_R25M
1
2
PC142
1U_0
603_
10V
6K~N
12
PR76
0_0402_5%
@
12
PC
504.
7U_1
206_
25V
6K~N
12
PC
4822
00P
_040
2_50
V7K
~N1
2
PR69100K_0402_1%
1 2
PQ16AO4712_SO8
365 7 8
2
4
1
PR67 0_0402_5%@12
PR
614.
7_12
06_5
%@
12
PQ13AO4466_SO8
36 578
2
4
1
PC520.1U_0603_25V7K~N
12 PQ14
AO4466_SO8
365 7 8
2
4
1
PR59
0_0603_5%12
PC
474.
7U_1
206_
25V
6K~N
12
PR
7020
0K_0
402_
5%1
2
PC571U_0603_10V6K~N1 2
PF3
7A_24VDC_429007.WRML
2 1
PL4HCB4532KF-800T90_1812
1 2
PD8
1SS355TE-17_SOD323-2
1 2
PC
54
4.7U
_080
5_6.
3V6K
~N12
PR71
255K_0402_1%12
PC
650.
047U
_040
2_16
V7K
~N
@
12
PR6461.9K_0402_1%~N
12
PR78
47K_0402_5%~N@
1 2
PC62 0.22U_0603_10V7K~N
1 2
PL5
4.7UH_SIL104R-4R7PF_5.7A_30%1 2
PC58
0.1U_0603_25V7K~N 12
PR580_0805_5%1 2
PR
75
806K
_060
3_1%
12
PR60
0_0603_5%
12
PC
5968
0P_0
603_
50V
7K
@
12
PC630.22U_0603_25V7-K
12
PR730_0402_5%@
12
PR
634.
7_12
06_5
%@
12
PR
620_
0402
_5%
12
PR72
255K_0402_1%
12
PR6610K_0402_1%~N
12
PC
53
1U_0
603_
10V
6K~N
12
PU6
ISL6237IRZ-T_QFN32_5X5
UGATE226
BOOT224
PHASE225
LGATE223
OUT230
REFIN232
TON
2
LDOREFIN8
NC20
EN_LDO4
EN227
EN114
POK1 13
POK2 28
PVCC 19VC
C3
SKIP 29
LDO
7
ILIM2 31
BYP 9
OUT1 10
GN
D21
PGND 22
LGATE1 18
PHASE1 16
BOOT1 17
UGATE1 15
VIN
6N
C5
REF1
FB1 11
ILIM1 12
TP33
PR6510K_0402_1%~N@
12
PC
5122
00P
_040
2_50
V7K
~N1
2
PC560.1U_0603_25V7K~N1
2
PC640.047U_0603_16V7K~N
12
PC
464.
7U_1
206_
25V
6K~N
12
PR
740_
0402
_5%
12
PR77
0_0402_5%
12
PC
494.
7U_1
206_
25V
6K~N
12
+PC55
330U_D3L_6.3VM_R25M
1
2
PR68 0_0402_5%1 2
PD7RLZ5.1B_LL34
1 2
A
A
B
B
C
C
D
D
1 1
2 2
3 3
4 4
LX_1.2V
5VFILT
UG_1.8V
BST_1.2V
+1.2VALWP
+1.2VALWP
VFB2
TON
SE
L
LG_1.2V
B+++
UG_1.2V
BST_1.2VA
LG_1.8V
VFB1
BST_1.8VAUG_1.2V_1
+1.8VP_EN +1.2VALWP_EN
+1.8VP
BST_1.8V
LX_1.8VUG_1.8V_1
+1.8VP
B++++
SYSON<24,28,32>
CPU_VDDIO_FB_L <6>CPU_VDDIO_FB_H <6>
B+++
+1.2VALWP
B+
+1.8VP
+5VALW
B+++
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4381P 0.0Custom
37 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
1.8VPImax=8A
Iocp=12.6A
1.2VALWPImax=7A
Iocp=11A
1.8VP/1.2VALWP
PR8914K_0402_1%
1 2
PC790.1U_0402_16V7K~N
@
12
PR1130_0402_5%
@
12
PR8275K_0402_1%
12
PR830_0402_5%
12
PU7
TPS51124RGER_QFN24_4x4
GN
D3
TON
SE
L4
VO
11
VFB
12
VFB
25
VO
26
EN28
DR VL1 19
TRIP
117
V5F
ILT
15
VBST1 22
V5I
N16
TRIP
214
DR VL212
LL211
PGOOD27
DR VH210 DR VH1 21
EN1 23
LL1 20
PG
ND
118
VBST29
PGOOD1 24
PG
ND
213
P PAD25
PC710.1U_0402_16V7K~N
1 2
PR913.3_0402_5%
1 2
PC700.1U_0402_16V7K~N
12
PR8814K_0402_1%
12
PL81.8UH_SIL104R-1R8PF_9.5A_30%
1 2
PR900_0402_5%
12
PL71.8UH_SIL104R-1R8PF_9.5A_30%
1 2
PQ19FDS6690AS_NL_SO8
36 578
2
4
1
PR870_0603_1%
12
PR1960_0402_5%
@
12
PR79105K_0402_1%
1 2
PR850_0603_1%
12
PR8075K_0402_1%
1 2
PL14HCB4532KF-800T90_1812
1 2PF4
7A_24VDC_429007.WRML
2 1
PR840_0603_1%
12
PC
6610
U_1
206_
25V
6M~N
12
PC138680P_0603_50V7K@
12
PC734.7U_0805_6.3V6K~N
12
PR81127K_0402_1%
12
PQ17FDS8884_SO8
36 578
2
4
1
PC744.7U_0805_6.3V6K~N 1
2
PC
6722
00P
_040
2_50
V7K
~N
12
PR920_0402_5%
1 2
+PC72220U_D2_4VM
1
2
PQ18FDS8884_SO8
365 7 8
2
4
1
PC771U_0603_10V6K~N
12
PR860_0603_1%
12
PQ20FDS6690AS_NL_SO8
365 7 8
2
4
1
PC760.1U_0402_16V7K~N
@
12
PR1664.7_1206_5%@
12 + PC75
220U_D2_4VM
1
2
PC
6922
00P
_040
2_50
V7K
~N
12P
C68
10U
_120
6_25
V6M
~N1
2
PC784.7U_0805_25V6M~N
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
NB_B+
EN_PSVBST_NBCORE
BST_NBCORE-1
DL_NBCORE
NB_VFB
NB_TON
NB_VFBA
LX_NBCORE
NB_V5FILT
DH_NBCORE
51117_B+
SUSP#<24,28,32,39>
NB_STRAP_DATA <11>
+5VALW
B+
+NB_COREP
+5VALW
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
U1 LA-4381P 0.0
NB_CORE
38 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
NB_STRAP_DATA
1.05VSPImax=5A
Iocp=9A
HIGH
LOW
1.05V
1.12V
+1.12V/+1.05V
NB_CORE
AO4712 Rds(on)=15mohm~18mohm
PQ22AO4712_SO8
365 7 8
2
4
1
PR940_0402_5%1 2
PC871U_0603_10V6K~N
12
PR96300_0603_1%1 2
PC82
0.1U_0603_25V7K~N
1 2
PF5
7A_24VDC_429007.WRML
2 1
PC830.1U_0402_16V7K~N@
12
G
D
S
PQ24SSM3K7002F_SC59-3
2
13PC88
0.1U_0402_16V7K~N
12
PC8547P_0402_50V8J~N
1 2
PC
814.
7U_1
206_
25V
6K~N
12
PR1020_0402_5%1 2
PQ21AO4466_SO8
365 7 8
2
4
1
PL15HCB4532KF-800T90_1812
1 2
PR10110K_0402_1%~N
12
PR10084.5K_0402_1%
12
PR9920K_0402_1%~N
12
PR9715.4K_0402_1%
12
PC890.01U_0402_25V7K~N
12
PR1030_0402_5%
1 2
PR1474.7_1206_5%@
12
PR950_0603_1%1 2
PR988.06K_0402_1%
1 2
PR114100K_0402_5%~N
12
PC864.7U_0805_25V6M~N
12
G
D
S PQ23SSM3K7002F_SC59-3
2
13
PC
804.
7U_1
206_
25V
6K~N
12
PL91.8UH_SIL104R-1R8PF_9.5A_30%
1 2
+ PC84220U_D2_4VM
1
2
PU8
TPS51117RGYR_QFN14_3.5x3.5
VOUT3
V5FILT4
EN
_PS
V1
TON2
VFB5
PGOOD6 DRVL 9
DRVH 13
LL 12G
ND
7
PG
ND
8TRIP 11
V5DRV 10V
BS
T14
TP15
PC137680P_0603_50V7K@
12
PR93200K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SUSP#
SYSON#
POK<36>
SYSON#<6,32>
SUSP#<24,28,32,38>
+3VALW
+0.9VP
+1.8V
+3VALW
+1.5VSP
+1.8V
+1.2VALW
+5VALW
+3VALW
+1.1VSP
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
LA-4381P 0.0Custom
39 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
0.9VP/1.5VSP/1.1/VSP
0.8V
PR1081.15K_0402_1%
32.8
12
PC9110U_1206_25V6M~N
12
PC980.1U_0402_16V7K~N
@
12
PC9522U_1206_6.3V6M~N
32.8
12
PC931U_0603_6.3V6M~N
12
PC9710U_1206_25V6M~N
12
PR10410K_0402_1%~N
12
PR1121K_0402_1%
12
PC9210U_1206_6.3V6M~N
32.8
12
PJP19JUMP_43X118@
11
22
PJP18JUMP_43X118@
11
22
G
D
S
PQ262N7002-7-F_SOT23-3
2
13
PR1090_0402_5%1 2
PR107
0_0402_5%
32.8
1 2
PC1011U_0603_6.3V6M~N
12
PR110
1K_0402_1%
12
PR105
0_0402_5%32.8
1 2
PJP17JUMP_43X118@
11
22
PC96
0.1U_0402_16V7K~N
12
PR1113K_0402_1%
32.8
12
PC10410U_1206_25V6M~N
12
G
D
S
PQ252N7002-7-F_SOT23-3
2
13
PR1150_0402_5%1 2
PR1061K_0402_1%
12
PC94
0.01U_0402_25V7K~N
32.8
12
PC103
0.1U_0402_16V7K~N
12
PC901U_0603_6.3V6M~N
12
PU9
G2992F1U_SO8
VOUT4
NC 5GND2
VREF3
VIN1 VCNTL 6
NC 7
NC 8
TP 9
PR116
4.99
K_04
02_1
%12PC105
0.1U_0402_16V7K~N@
12
PU10
APL5912-KAC-TRL_SO8~N32.8
GN
D1
VOUT 3POK7
EN8VC
NTL
6
VIN 5
VOUT 4
FB 2
VIN 9
PU11
G2992F1U_SO8
VOUT4
NC 5GND2
VREF3
VIN1 VCNTL 6
NC 7
NC 8
TP 9
PC9910U_1206_25V6M~N
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
BOOT0
RTN1
FB_0
PHASE_NB
UGATE_NB
PHASE_NB
BOOT1
BOOT_NB
+VCC_CORE1
+VDDNBP
ISN
0
LGATE_NB
DIFF_1
UGATE_NB
BOOT_NB
LGATE0
ISP
1
UGATE0
VGATE
UGATE1
VSEN1
VSEN0
BOOT1
RTN0
PHASE0
LGATE1
PHASE1
PHASE1
PHASE0
UGATE0
BOOT0
ISN
1
LGATE_NB
PHASE_NB
ISP
0
LGATE0
LGATE1
ISN
1
ISP
1
+VCC_CORE0
VW0
COMP0
VW1
COMP1FB_1
DIFF_0
ISL6265_PWROK
UGATE1
ISL6265_P
WR
OK
ISN0ISP0
CPU_VDDNB_RUN_FB_H <6>
CPU_VDDNB_RUN_FB_L <6>
CPU_VDD0_RUN_FB_H<6>
CPU_VDD0_RUN_FB_L<6>
CPU_VDD1_RUN_FB_H<6>
CPU_PWRGD_SVID_REG<6>
CPU_SVD<6>
CPU_SVC<6>
VR_ON<28>
VFIX_EN<28>
CPU_VDD1_RUN_FB_L<6> +VCC_CORE1
CPU_B+
+VCC_CORE0
CPU_B+
+VDDNBP
CPU_B+
CPU_B+
+5VS +3VS
B+
+5VS
+5VS
+VCC_CORE1+VCC_CORE0
Title
Size Document Number Rev
Date: Sheet of
Security Classification Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIALAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&DDEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSMAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date Deciphered Date
0.0
+CPU_CORE
Custom
40 41Wednesday, January 16, 2008
2007/12/12 2008/12/12Compal Electronics, Inc.
JAL70
+VCC_CORE1Design Current: 12.6AMax current: 18A OCP_min:24A
+VDDNBPDesign Current: 2.1AMax current: 3A OCP_min:5A
+VCC_CORE0Design Current: 12.6AMax current: 18A OCP_min:24A
PR1350_0603_5%1 2
PR155
0_0402_5%
12
PR1450_0402_5%
12
PC1121000P_0402_50V7K~N
12
PR12222K_0402_1%
12
PQ33SI4856DY-T1-E3_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC1091000P_0402_50V7K~N
12
PR1234.7_1206_5%@
12
PQ29SI7686DP-T1-E3_SO8
35
2
4
1
PR1280_0402_5%
12
PR157
10_0402_5%
12
PR12711.3K_0402_1%
12
PC1294700P_0402_25V7K~N
12
PR154
4.02K_0402_1%1 2
PU13
ISL6265HRTZ-T_QFN48_6X6~D
PWROK3
SVD4
OFS/VFIXEN1
PGOOD2
SVC5
ENABLE6
OCSET8V
DIF
F119
RTN
117
VS
EN
015
VW
122
RTN
016
ISN
014
VW012
COMP011
RBIAS7
FB010C
OM
P1
21
ISP
123
FB1
20
VS
EN
118
VDIFF09
ISN
124
ISP
013
BOOT1 25
UGATE1 26
PHASE1 27
PGND1 28
LGATE1 29
PVCC 30
LGATE0 31
PGND0 32
PHASE0 33
UGATE0 34
BOOT0 35
BOOT_NB 36
UG
ATE
_NB
37
PH
AS
E_N
B38
LGA
TE_N
B39
PG
ND
_NB
40
OC
SE
T_N
B41
RTN
_NB
42
VS
EN
_NB
43
FSE
T_N
B44
CO
MP
_NB
45
FB_N
B46
VC
C47
VIN
48
TP49
PR12510_0603_5%
1 2
PC1260.22U_0603_10V7K~N
1 2
PR1384.7_1206_5%@
12
PC
147
1000
P_0
402_
50V
7K~N
@
12
PR
150
100_
0402
_5%
12
PR129105K_0402_1%@
12
PR12410_0402_5%1 2
PJP27
PAD-OPEN 4x4m@
1 2
PC1200.22U_0603_10V7K~N
1 2
PR139
4.02K_0402_1%1 2
PC
110
10U
_120
6_25
V6M
~N1
2
PC
119
10U
_120
6_25
V6M
~N1
2
PR142100K_0402_1%
12
PC1324700P_0402_25V7K~N
12
PC10833P_0402_50V8J~N
12
PR1631K_0402_5%
12
PC1441000P_0402_50V7K~N@
12
PQ30SI4856DY-T1-E3_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PR164
54.9K_0402_1%
12
PC
125
10U
_120
6_25
V6M
~N1
2
PC128
0.1U_0603_16V7K~N
12
PR1260_0402_5%
12
PR12110_0603_5%1 2
PR131105K_0402_1%
12
PC135
1000P_0402_50V7K~N
12
PR1601K_0402_5%
12PR161
54.9K_0402_1%
12
PR13616.2K_0402_1%
12
PR134105K_0402_1%@
12
PR1534.7_1206_5%@
12
PR1300_0402_5%
12
PR158255_0402_1%
12
PC
124
10U
_120
6_25
V6M
~N1
2
PJP23
PAD-OPEN 4x4m@
1 2
PR1626.81K_0402_1%
12
PQ28AO4712_SO8
365 7 8
2
4
1
PC1231U_0603_10V6K~N<BOM Structure>
12
PC136
1000P_0402_50V7K~N
12
PH2
10K_0603_5%_TSM1A103J4302RE
12
PL120.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
PL130.36UH_PCMC104T-R36MN1R17_30A_20%
1 2
PC121680P_0603_50V7K@
12
PC1130.1U_0603_16V7K~N
12
PQ32SI7686DP-T1-E3_SO8
35
2
4
1
PC116680P_0603_50V7K@
12
PR199100K_0402_5%~N
12
PR201
0_0603_5%
12
G
D
S
PQ37SSM3K7002F_SC59-3
2
13
PJP22
PAD-OPEN 4x4m@
1 2
PR14117.8K_0402_1%
12
PC122
0.1U_0603_16V7K~N
12
PQ34SI4856DY-T1-E3_SO8
S1
S2
S3
G4
D8
D7
D6
D5
+ PC115220U_D2_4VM
1
2
PQ27AO4466_SO8
365 7 8
2
4
1
PR13310_0402_5%
12
PR156
10_0402_5%
12
PR12044.2K_0402_1%
12
PR15116.2K_0402_1%
12
+
PC
111
100U
_25V
_M 1
2
PC133180P_0402_50V8J~N
12
PC1140.22U_0603_10V7K~N
1 2
PC127680P_0603_50V7K@
12
PH3
10K_0603_5%_TSM1A103J4302RE
12
PR1400_0402_5%
12
PL10HCB4532KF-800T90_1812
1 2
PR144
0_0402_5%
12PR202
0_0603_5%
12
PR14610_0402_5%
12
PC1341000P_0402_50V7K~N
@
12
PR159255_0402_1%
12
PR1980_0402_5%
@
12
PC130180P_0402_50V8J~N
12
PR143
10_0402_5%
12
PR1480_0603_5%1 2
PR149
0_0402_5%
12
PC
146
1000
P_0
402_
50V
7K~N
@
12
PC1311000P_0402_50V7K~N
@
12
PR13210K_0402_1%~N@
12
PR1656.81K_0402_1%
12
PR
152
100_
0402
_5%
12
PQ31SI4856DY-T1-E3_SO8
S1
S2
S3
G4
D8
D7
D6
D5
PC
118
10U
_120
6_25
V6M
~N1
2
PL114.7UH_MPL73-4R7_5.5A_20%
1 2
PC1170.1U_0603_16V7K~N
12
PR200
0_0603_5%
12
PC1451000P_0402_50V7K~N@
12
PR1370_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet ofU1 LA-4381P 0.0
EE-PIR
Compal Electronics, Inc.
Wednesday, January 16, 2008 4141MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINSAND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Page 1Solution Description Rev.Page# Title
Version Change List ( P. I. R. List )Item Issue DescriptionDate
Next: PR238, PC202, PQ56, PD42, PJP21
P37
P37
P38
P41
P41 +CPU_CORE 08'01/08
+CPU_CORE
ADD PR201 PR202Modify improve EMI
08'01/02 Add PR200 for BOOT_NB.
0.1
Intersil FAE request.
7 P36 +3VALWP,+5VALWP 08'01/08 Compal adjust +3VALWP,+5VALWP ocp setChange PR71 from 330K to 255K
Change PR72 from 330K to 255K
8 P35 Charger 08'01/08 Compal adjust Charger pre cell set Change PR53 from 15K to 4.32K
Change PQ19 PQ20 from AO4712 to FDS6690AS
9 P38 NB_CORE 08'01/08 Compal Change PR96 from 0ohm to 300ohmTI FAE request.TI FAE request.
0.1
0.1
0.1
1.8VP/1.2VALWP 08'01/08 modify current limit
Change PQ17 PQ18 from AO4466 to FDS8884
1.8VP/1.2VALWP 08'01/08 adjust 1.8VP/1.2VALWP OCP set
Change PR88 from 16.5K to 14K
NB_CORE 08'01/08 Change PR114 from @0 to 100KModify NB_CORE turn off avoised cause force PWM mode
+CPU_CORE 08'01/08Change PR199 from 0ohm to 100K
Change PR89 from 20.5K to 14K
Modify while S3 mode avoised cause voltage drop
ADD PQ37
RequestOwner
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CompalP41 0.1
Compal
Compal
Compal
0.1
0.1
0.1
Compal
Compal
0.1