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The ARM Architecture
Ali Saidi
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Agenda ! Introduction to ARM Ltd
ARM Architecture/Programmers Model Data Path and Pipelines System Design Development Tools
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ARM Ltd
! Founded in November 1990 ! Spun out of Acorn Computers
! Designs the ARM range of RISC processor cores ! Licenses ARM core designs to semiconductor
partners who fabricate and sell to their customers. ! ARM does not fabricate silicon itself
! Also develop technologies to assist with the design-in of the ARM architecture ! Software tools, boards, debug hardware,
application software, graphics, bus architectures, peripherals, cell libraries
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The Architecture for the Digital World ARM designs technology that lies at the heart
of advanced digital products
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ARM’s Activities
memory
SoC
Processors System Level IP: Data Engines Fabric 3D Graphics
Physical IP
Software IP
Development Tools
Connected Community
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Product Areas
! Cortex-M0 to Cortex-A9
! Compilers & OS profiling
! 180nm to 28nm
! GPU to HD video
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ARM Business Today ! Processor Shipped Last Year : ~4 Billion ! Processor Shipped In Total : >24 Billion ! Processor Licenses : 500+ ! Semiconductor Partners : 200+ ! Process Technology : 28 – 250 nm ! Connected Community Members : 700+
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ARM Business Model Drivers ! Deliver more functionality to the end-user sooner
and more cost-effectively
! Integration ! Economics ! Focus ! Ecosystem ! Choice ! Power efficiency
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Global Company
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700+
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Nokia N95 Multimedia Computer
Symbian OS™ v9.2 Operating System supporting ARM processor-based mobile devices,
developed using ARM® RealView® Compilation Tools
OMAP™ 2420 Applications Processor
ARM1136™ processor-based SoC, developed using Magma ® Blast® family and winner of 2005
INSIGHT Award for ‘Most Innovative SoC’
Connect. Collaborate. Create.
Mobiclip™ Video Codec Software video codec for ARM
processor-based mobile devices
ST WLAN Solution Ultra-low power 802.11b/g WLAN
chip with ARM9™ processor-based MAC
S60™ 3rd Edition S60 Platform supporting ARM
processor-based mobile devices
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ARM Processor Applications
Tele-parking
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World’s Smallest ARM Computer?
A C B
Wirelessly networked into large scale sensor arrays
University of Michigan
Sensors, timers
Cortex-M0 +16KB RAM 65nm UWB Radio antenna
10 kB Storage memory ~3fW/bit
12!Ah Li-ion Battery
Wireless Sensor Network
Cortex-M0; 65¢
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World’s Largest ARM Computer?
4200 ARM powered Neutrino Detectors
Work supported by the National Science Foundation and University of Wisconsin-Madison
2.5km
70 bore holes 2.5km deep
60 detectors per string starting 1.5km down
1km3 of active telescope
1km
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From 1mm3 to 1km3
The Architecture for the Digital World
1mm3 1km3
2mm
0.7mm 1.2mm
10¢ $1000
Mobile Embedded Consumer
Mobile Computing Server Enterprise PC
Home HPC
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Agenda Introduction to ARM Ltd ! ARM Architecture/Programmers Model
Data Path and Pipelines System Design Development Tools
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ARMv4
Architecture Versions
x1-4
ARMv5
ARMv6
ARMv7-Cortex
ARM966E-S™
SC200™ ARM7EJ-S™
ARM922T™
SC100™
ARM920T™
ARM7TDMI(S)™
ARM1176JZ(F)-S™
ARM1156T2(F)-S™
ARM1136J(F)-S™
ARM1026EJ-S™
ARM968E-S™
ARM926EJ-S™
ARM946E-S™
x1-4
Cortex-A9
SC300™
Cortex-M1/M0 (v6-M)
Cortex™-M3
Cortex-R4
Cortex-R4F
Cortex-A8
ARM11™ MPCore™
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Relative Performance*
*Represents attainable speeds in 130, 90 or 65nm processes
Cor
tex A
8
AR
M11
76JZ
-S
AR
M92
6EJ-
S
AR
M92
0T
AR
M7T
DM
I
AR
M11
36J-
S
AR
M10
26E
J-S
0.43
0.36
0.568
0.335
0.235
0.25 0.35
mW/MHz
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ARM Cortex Advanced Processors Architectural innovation, compatibility across diverse application spectrum
! ARM Cortex-A family: ! Applications processors for feature-
rich OS and 3rd party applications
! ARM Cortex-R family: ! Embedded processors for real-time
signal processing, control applications
! ARM Cortex-M family: ! Microcontroller-oriented processors
for MCU, ASSP, and SoC applications
Cortex-R4(F)
Cortex-A8
SC300™
Cortex-M1 Cortex™-M3
...2GHz
x1-4
Cortex-A9
x1-4
Cortex-A5
12k gates... Cortex-M0 U
npar
alle
led
App
licab
ility
Cortex-M4
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Data Sizes and Instruction Sets ! The ARM is a 32-bit architecture.
! When used in relation to the ARM: ! Byte means 8 bits ! Halfword means 16 bits (two bytes) ! Word means 32 bits (four bytes)
! Most ARM’s implement two instruction sets ! 32-bit ARM Instruction Set ! 16-bit/32bit Thumb Instruction Set
! Jazelle cores can also execute Java bytecode
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ARM and Thumb Performance
Memory width (zero wait state)
Dhrystone 2.1/sec @ 20MHz
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Thumb-2 Instruction Set
! Second generation of the Thumb architecture ! Blended 16-bit and 32-bit instruction set ! 25% faster than Thumb ! 30% smaller than ARM
! Increases performance but maintains code density
! Maximizes cache and tightly coupled memory usage
EEMBC Analysis - Performance
EEMBC Analysis – Code Size
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Processor Modes – A Class ! The ARM has seven basic operating modes:
! User : unprivileged mode under which most tasks run
! FIQ : entered when a high priority (fast) interrupt is raised
! IRQ : entered when a low priority (normal) interrupt is raised
! Supervisor : entered on reset and when a Software Interrupt instruction is executed
! Abort : used to handle memory access violations
! Undef : used to handle undefined instructions
! System : privileged mode using the same registers as user mode
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r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r13 (sp) r14 (lr) r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
FIQ IRQ SVC Undef Abort
User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r13 (sp) r14 (lr) r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
FIQ IRQ SVC Undef Abort
r0 r1 r2 r3 r4 r5 r6 r7
r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User IRQ SVC Undef Abort
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
FIQ Mode IRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User FIQ SVC Undef Abort
r13 (sp) r14 (lr)
Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User FIQ IRQ SVC Abort
r13 (sp) r14 (lr)
SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User FIQ IRQ Undef Abort
r13 (sp) r14 (lr)
Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12
r15 (pc)
cpsr
r13 (sp)"r14 (lr)"
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r13 (sp) r14 (lr)
spsr
r8 r9 r10 r11 r12
r13 (sp) r14 (lr)
spsr
Current Visible Registers
Banked out Registers
User FIQ IRQ SVC Undef
r13 (sp) r14 (lr)
The ARM Register Set
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Vector Table
Exception Handling
! When an exception occurs, the ARM: ! Copies CPSR into SPSR_<mode> ! Sets appropriate CPSR bits
! Change to ARM or Thumb state ! Change to exception mode ! Disable interrupts (if appropriate)
! Stores the return address in LR_<mode> ! Sets PC to vector address
! To return, exception handler needs to: ! Restore CPSR from SPSR_<mode> ! Restore PC from LR_<mode> Vector table can be at
0xFFFF0000 on ARM720T and on ARM9/10 family devices
FIQ IRQ
(Reserved) Data Abort
Prefetch Abort Software Interrupt
Undefined Instruction
Reset
0x1C 0x18 0x14 0x10
0x0C 0x08
0x04
0x00
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Program Status Registers
! Condition code flags ! N = Negative result from ALU ! Z = Zero result from ALU ! C = ALU operation Carried out ! V = ALU operation oVerflowed
! Sticky Overflow flag - Q flag ! Architecture v5+ only ! Indicates if saturation has occurred
! J bit ! Architecture v5+ only ! J = 1: Processor in Jazelle state
! Interrupt Disable bits. ! I = 1: Disables the IRQ. ! F = 1: Disables the FIQ.
! T Bit ! Architecture v5+ only ! T = 0: Processor in ARM state ! T = 1: Processor in Thumb state
! Mode bits ! Specify the processor mode
27 31
N Z C V Q 28 6 7
I F T mode 16 23 8 15 5 4 0 24
f s x c
U n d e f i n e d J
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! ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field. ! This improves code density and performance by reducing the number of
forward branch instructions. CMP r3,#0 CMP r3,#0
BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip
! Why was this developed? ! When would you want to use it? Always? Any downsides?
Conditional Execution and Flags
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Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model ! Data Path and Pipelines
System Design Development Tools
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Multiplier
The ARM7TDM Core
Instruction Decoder
Address Incrementer
nRESET
nMREQ SEQ
ABORT
nIRQ nFIQ
nRW MAS[1:0]
LOCK
nCPI CPA CPB
nWAIT MCLK
nOPC
BIGEND
ISYNC
nTRANS
nM[4:0]
D[31:0]
Barrel Shifter
32 Bit ALU
DBE
Write Data Register
Read Data Register
Address Register
Register Bank
A[31:0] ABE
and
Control Logic
PC Update
Decode Stage Instruction
Decompression
Incrementer
P C
A
B
u
s
B
B
u
s
A
L
U
B
u
s
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Pipeline changes for ARM9TDMI
Instruction Fetch Shift + ALU Memory
Access Reg
Write Reg Read
Reg Decode
FETCH DECODE EXECUTE MEMORY WRITE
ARM9TDMI ARM or Thumb
Inst Decode
Reg Select
Reg Read Shift ALU Reg
Write Thumb!ARM decompress
ARM decode Instruction Fetch
FETCH DECODE EXECUTE
ARM7TDMI
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ARM10 vs. ARM11 Pipelines
ARM11
Fetch 1
Fetch 2 Decode Issue
Shift ALU Saturate
Write back
MAC 1
MAC 2
MAC 3
Address Data
Cache 1
Data Cache
2
Shift + ALU Memory Access Reg
Write
FETCH DECODE EXECUTE MEMORY WRITE
Reg Read
Multiply
Branch Prediction
Instruction Fetch
ISSUE
ARM or Thumb
Instruction Decode Multiply
Add
ARM10
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Full Cortex-A8 Pipeline Diagram 13-Stage Integer Pipeline 10-Stage NEON Pipeline
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Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines ! System Design
Development Tools
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Typical SoC w/GPU
ARM1176JZF
L230
Mali 200 Mali GP2
CLCD PL111
PL301 High-performance matrix
SDRAMC PL340
APB Peripheral Sub-System
D I
APB M S
Sys Ctrl
nRst
M
PL390 GIC
Int
DDR PHY
! Designed and optimised for AMBA: provides easier integration with ARM cores and fabric IP ! Unified Memory Architecture
Local AXI Interconnect Mali MMU
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Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines System Design ! Development Tools
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ARM Debug Architecture
ARM core
ETM
TAP controller
Trace Port JTAG port
Ethernet
Debugger (+ optional trace tools)
! EmbeddedICE Logic ! Provides breakpoints and processor/system
access ! JTAG interface (ICE)
! Converts debugger commands to JTAG signals
! Embedded trace Macrocell (ETM) ! Compresses real-time instruction and data
access trace ! Contains ICE features (trigger & filter logic)
! Trace port analyzer (TPA) ! Captures trace in a deep buffer
EmbeddedICE Logic
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Keil Development Tools for ARM
! Includes ARM macro assembler, compilers (ARM RealView C/C++ Compiler, Keil CARM Compiler, or GNU compiler), ARM linker, Keil uVision Debugger and Keil uVision IDE
! Keil uVision Debugger accurately simulates on-chip peripherals (I2C, CAN, UART, SPI, Interrupts, I/O Ports, A/D and D/A converters, PWM, etc.)
! Evaluation Limitations ! 16K byte object code + 16K data limitation ! Some linker restrictions such as base addresses for code/constants ! GNU tools provided are not restricted in any way
! http://www.keil.com/demo/
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Keil Development Tools for ARM
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Fin