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SWITCHING REGULATOR WITH DYNAMICALLY ADJUSTABLESUPPLY VOLTAGE FOR LOW POWER VLSI
Sandeep Dhar and Dragan Maksimović
Colorado Power Electronics Center
Department of Electrical and Computer Engineering
University of Colorado, Boulder, CO 80309-0425,
dhar,maksimov @colorado.edu
Abstract – The paper describes a switching regulator system
for adaptive voltage scaling (AVS) where the supply volt-
age to a digital VLSI chip is dynamically adjusted to the
minimum value required for the desired system speed. The
control loop includes a variable-frequency Watkins-Johnson
switching DC-DC converter and a model of the critical path
delay of the application. Simple bang-bang control of the
critical path delay allows fast transient response to step
changes in speed, and stable operation over a very wide
range of system clock frequencies. A chip including the AVS
controller and a small digital application has been fabricated
in a standard CMOS process. Experimental results demon-
strate operation over the application clock frequency rangefrom 10 kHz to 20 MHz, and a 12 s transient response for a
step change in speed from standby to maximum throughput
operation.
1. Introduction
The strong demand for low-power computing has been driven
by a growing class of portable, battery-operated applications
that demand ever increasing functionalities with low-power con-
sumption. The power consumption is also a limiting factor in
integrating more transistors in VLSI chips for portable appli-
cations. The resulting heat dissipation also limits the feasible
packaging and performance of the VLSI chip and system. Be-
cause of the quadratic dependence of power consumption on thesupply voltage [11], reducing the supply voltage level is an ef-
fective way to reduce power consumption. However lower sup-
ply voltage, for a given technology leads to increased gate delay
and as a result the application has to be operated at a reduced
clock rate.
More recently, adaptive (or dynamic) voltage scaling (AVS)
has been proposed as an effective power management technique
where the system supply voltage and the clock frequency of a
digital VLSI application are dynamically adjusted to meet the
application throughput requirements [1]-[8]. By reducing the
supply voltage and application clock frequency, adaptive voltage
scaling offers, in principle, superior power savings compared to
simple on/off power management. Successful applications have
included digital signal processing systems [1]-[5], I/O interface
[6], and general-purpose microprocessor [7, 8].
At the system level, AVS requires a voltage/frequency sched-
uler that can intelligently vary the speed depending on the ap-
plication requirements [7, 8]. At the hardware implementation
level, the key AVS component is a controller that can automat-
ically generate the minimum voltage required for the desired
speed. Desirable features of an AVS controller include [8]-[10]:
high efficiency of the power converter used to generate the vari-
able supply voltage; ability to make voltage adjustments over
Figure 1: Supply voltage and critical path delay waveforms illustratingsteady state operation of the “bang-bang” delay controller.
a very wide range of clock frequencies to accommodate pro-
cessing speeds from stand-by to maximum throughput; stable
and fast transient response to minimize latency and losses when
switching between different speed levels.
Voltage regulation systems for adaptive voltage scaling include
frequency locked loop (FLL) based scheme [8], phase locked
loop (PLL) based scheme [2, 9], and a delay-line based speed
detector [3, 5]. In these approaches, the control loop design
requires a careful compromise between the loop stability and
dynamic response times [2, 8, 9] or multiple test clock cy-
cles needed [3, 5]. In addition, the capture range of PLL or
FLL based schemes may limit the achievable range of operat-ing system clock frequencies. Also, since the system clock in
a PLL/FLL scheme is generated by a VCO operating from the
supply voltage [2, 8, 9], the system clock suffers from variable
clock jitter due to supply voltage noise.
The contribution of this paper is to introduce the theory and
concept of a simple digital control scheme for AVS based on
the “bang-bang” control method. The controlled variable is the
critical path delay of the application. This variable is forced
to be between the limits that correspond to the supply voltage
value being close to the minimum required for the desired sys-
tem clock frequency. The bang-bang delay control method ef-
fectively removes the stability concerns, and allows fast tran-
sient response and operation over a very wide range of clock frequencies. Furthermore, since the system clock and supply
voltage are generated independently, system clock jitter can be
effectively reduced.
This paper is organized as follows. The proposed AVS con-
troller is described in Section 2. Design of the power converter
embedded in the control loop is given in Section 3. Simula-
tion results of the proposed scheme and experimental results ob-
tained from a fabricated chip that combines the AVS controller
and a simple test application are presented in Section 4 followed
by conclusions in Section 5.
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Figure 5: Implementation of the control logic to generate . Alldevices are assumed to be operating at supply voltage
tions, i.e., at the maximum supply voltage, and at the maximum
clock frequency
. The delay-cell is then designed
using the model parameters for that process corner. Next, the
delay-line length is selected such that the test clock at
the maximum system clock frequency is just able to propagate
through this length when the supply voltage to the delay-line
has the maximum value. The length can be altered by
choice of the device sizes in the delay-cell design. This choice
also affects the output voltage ripple
as explained in Sec.
3.2.Since the test takes one half of the test clock period (i.e. when
is at logic 1), the critical path model effectively captures
half of the application worst-case critical path delay. With the
delay-line fabricated on the same chip as the application, the
delay-line characteristics scale with the application for voltage,
process or temperature variations.
It should be noted that for proper testing of the
value, the
clock must have a 50% duty cycle. Instead of placing
this responsibility on the external clock, in our scheme the test
clock and the system clock are obtained by dividing an external
clock (at
) by 2.
2.3 Control LogicFig. 5 shows the implementation of the control logic that takes
as inputs the level-shifted delay-line taps DATA2, DATA1, and
DATAH and outputs the control signals for the power converter
switches. As explained in Sec. 2.1, a logic 1 on the input DATAi
implies that the test clock could not propagate to DATAi within
the test clock period. For the outputs, a logic 1 value turns on a
power converter switch. These signals are explained below with
Figure 6: State diagram showing state of the converter power switchescontrolled by (a) CONT IN and (b) CONT DIS. The arcs are labeled
with valid input combinations
Figure 7: modified Watkins Johnson (WJ) converter used in the
AVS scheme
reference to the modified Watkins-Johnson converter shown in
Fig. 7;
CONT IN : controls the input side switch . When turned on,
the switch connects to the converter network.
CONT OUT : controls the output side switch . When turned
on, the switch allows the charging or discharging of the output
capacitor through the converter.
CONT DIS : controls the output discharge switch . When
turned on in conjunction with it allows the capacitor to dis-
charge through the inductor.
Fig. 6 shows the state diagram for the control outputs CONT IN
and CONT DIS. Control output CONT OUT is the logic sum
of these control signals. For example in steady state the inputs
(DATA2, DATA1, DATAH) are at logic values (0,1,1) which
implies that is sufficient for the test clock to propagate
through the critical path model consisting of
cells, but not
enough to propagate through the additional delay ripple of
cells. Depending on the previous state of the converter switch
and the supply voltage limit ( or ) reached the
power converter switches are turned on or off.3. Variable-Frequency Switching Converter
While any step-down switch-mode power converter should suf-
fice, a desirable property of the power converter is that in steady
state operation the output voltage should start increasing when
the control signal CONT OUT is logic 1, and start decreasing
when CONT OUT is logic 0. This allows for a simple, stable
bang-bang control of the delay and therefore of the output volt-
age ripple.
The switching converter we selected for the AVS controller
(Fig. 7) is a modification of the Watkins-Johnson (WJ) converter
[12]. The WJ converter has the desirable property that the out-
put voltage will always decrease when the converter switchesare turned off as compared to a standard step-down (buck) con-
verter.
The WJ converter is operated in the discontinuous conduction
mode (DCM) in steady state. In this mode of operation the con-
verter switches
and
turn on for short durations of time.
The inductor current is discontinuous and is zero at the end of
the converter switching period.
3.1 Dynamic response to step changes in clock frequency.
3.1.1 Step change from low
to high
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Figure 8: LC networks used to model the transient response of
the converter to step changes in frequency, (a) for a step change
from low to high
and (b) a step change from high to low
To minimize latency and/or additional losses, it is desirable to
have fast transient response to step changes in clock frequency.
The converter and the controller transient response to a step
change from low to high is determined by a simple open-
loop model shown in Fig. 8(a). We assume that the converter
operates in DCM so that initially the inductor current is zero.
During this voltage transient the supply voltage is too low
for the application and the the system clock is disabled.
During this time, the application consumes almost no current
(
0) . As a result,
=
during the transient. The
capacitor voltage
is at some initial value .
At
, the switches and are closed and voltage
is applied across the terminals of the network. We are inter-
ested in the time taken for the capacitor voltage to reach a value
. This can be found by solving the differential
equations for the network, resulting in
(1)
3.1.2 Step change from high to low
Similarly the converter transient response to a step change from
high to low
is determined by the simple open-loop
model shown in Fig. 8(b). The inductor current is initially zero.The capacitor is at some initial voltage
and is discharging
with load current
.
At
, the switches
and
close and the capacitor ad-
ditionally discharges through the inductor. Once again we are
interested in the time take for the capacitor voltage to reach a
value . For simplicity we can ignore the load
current giving us the solution,
(2)
The actual transient time is less than (2) since it includes the ca-
pacitor discharge through the load. Equations (1) and (2) show
that the transient responses are of the order of
.
3.2 Converter Switching Frequency
In steady-state (DCM) operation, the converter switches turn
on for a short time interval
charging the capacitor to
, followed by a longer period
over which dis-
charges to
. Under this assumption the capacitor charg-
ing time period can be ignored and the switching period of the
converter
equals
.
(3)
Consequently the converter switching frequency can be
given as,
(4)
where
is the power consumption of the application. However
depends on the delay-line parameters ( and ) and
. This dependence can be found as follows:
At its valley voltage value
the delay through the criti-
cal path model is given as,
(5)
where
is the delay through a delay-cell and is a function of
, i.e.
.
At its peak voltage value
the delay through the delay-
line is
(6)
Since these delays represent the test portion of , they are
equal. Equating the two sides and simplifying by keeping only
the linear terms in the Taylor expansion gives us
(7)
Furthermore, the relation between
and was obtained
by a curve-fit to be approximated as,
(8)
Taking the derivative and substituting in (7) we have,
(9)
As
increases so does
. The delay-line parameters
and
can thus be set to limit the output voltage ripple at
the maximum supply voltage. The output voltage ripple is not
determined by the converter parameters, which is an advantage
of the scheme since it allows for straightforward design of the
WJ converter.
To a first order the power consumption
of the application is,
(10)
where
is a constant. Substituting for
and
in (4)
yields
(11)
Since the test period is also one-half of the system clock period,
can be related to using (8),
(12)
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Figure 9: Block diagram of fabricated chip with external WJ converterproviding AVS of a 6x6 multiplier with registered outputs.
Substituting in (11) gives us,
(13)
This relation implies that the converter switching frequency in-
creases with (and ). This is desirable, because it
implies that the converter switching frequency scales with the
system clock frequency. As a result, switching losses in the
converter also scale with application load power, and the con-
verter can maintain relatively high efficiency over a wide range
of operating conditions.
3.3 Selection of Converter Components
and
As described by (1), (2) and (13), is inversely proportional
to and the transient responses are of the order of
. Hence
can be selected to set the switching frequency. It is desirable
to have a small so that the transient response is faster and
the losses in transient are smaller. However a higher switching
frequency also results in higher switching losses [12] which re-
duces the steady-state power efficiency of the converter. Using
(10), can be inferred from power consumption of the ap-plication for the measured
and . and have
already been selected to limit the output voltage ripple. Hence
can be selected to set the maximum switching frequency at
the maximum supply voltage. Once has been selected,
is
selected to adjust the transient response time. How short the
transient response can be is constrained only by the ability of
power switches to conduct increased peak inductor current and
the conduction losses in the converter switches.
4. Simulation and Experimental Results
The entire scheme except for external
and was designed in
a standard CMOS process and extensive Spice simulations were
performed.
A chip implementing the AVS controller was designed in a 1.5
standard CMOS process available through MOSIS (Fig. 10).
The area taken by the AVS controller including pads is 0.88
. The chip also contains a 6x6 array multiplier which was
used as a test application for the controller. The outputs of the
multiplier are registered and are updated at the rising edge of
the system clock. A model extracted from layout of the mul-
tiplier was simulated at the typical process corner to determine
that under worst-case input data, and at an operating frequency
of 20MHz, the multiplier requires a supply voltage of 2.8 . The
Figure 10: Die photo of chip implementing AVS controller for the testapplication
Figure 11: Plot of
as a function of
for a test where
was adaptively scaled to its minimum value for operation at the given
system clock frequency.
is varied from 20KHz to 40MHz.
parameters used in the typical process corner model were then
used to design the critical path model of the delay-line, with
appropriate sizing of the devices in the delay-cell such that for
delay line length
a test clock pulse at
20MHz and = 2.8 V is just able to propagate to the level-shifted tap DATA2. With these parameters the maximum
is about 150 at 2.8 (cf. equation 7).
A test circuit for AVS of the multiplier was designed with a WJ
converter closing the loop externally as shown in the block di-
agram representation (Fig. 9). The delay-line for the fabricated
Figure 12: Comparison of measured power consumption for differentschemes. From top to bottom, (a)
= 3 V, constant, (b) AVS with
power consumption on-chip only and (c) including the power consump-
tion in the WJ-converter.
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Figure 13: Measured power efficiency of WJ-converter as a functionof
when used in the closed loop AVS scheme.
chip does not include the delay-cells to detect high
and
during a step change from high to low the capacitor is
simply allowed to discharge to the lower supply voltage value.
From power consumption measurements of the multiplier,
was estimated to be about 4 pF. It was desired to have a converter
switching frequency about 50 kHz at the maximum supply volt-
age. = 47 nF was selected by substituting for values in (13).
Also, it was desired to have a worst case transient response
15
s for a step change from the lowest system clock frequency(10 kHz,
= 0.8 V) to the highest system clock frequency
(20 MHz,
= 2.8 V). Using (1),
was selected to be 750
H.
A plot of
as a function of
is shown in Fig. 11. It
is observed that the control loop provides the over a very
wide range of
, which is an advantage of the proposed
controller. It is possible to realize very low power stand-by op-
eration at very low clock frequency, and the supply voltage close
to the threshold voltage of the devices. Fig. 12 shows the mea-
sured power consumption as a function of
, of the AVS
application compared to fixed operation. For illustration,
both the power consumption excluding the converter and includ-
ing the converter losses are shown. The power levels in Fig. 12are low due to the small complexity of the multiplier application.
The power efficiency, of the WJ converter over this range of
frequencies is given in Fig. 13. Due to low output power levels
of the converter, the converter losses become significant only at
very low frequencies, resulting in low .
A second test was designed to demonstrate the fast transient
response of the control loop from the lowest operating supply
voltage to the maximum supply voltage. Two external clock
frequencies
= 20 kHz and
= 40MHz were applied
to a switch that alternated between the two frequencies. Details
of this transient response around the vicinity of the step change
in frequency are seen in Fig. 14. The transient from
= 0.8
V to = 2.8 V takes about 12 , which compares favorablyto the results reported in earlier publications [3, 5, 7, 8, 10].
5. Conclusions
Adaptive voltage scaling (AVS) of a supply voltage is emerging
as an effective power management technique for digital VLSI
applications. The paper describes a delay-line based regulation
scheme which is simple to implement and allows fast transient
response to step changes in speed, and stable operation over a
very wide range of system clock frequencies. The delay is mea-
sured at the system clock rate, which minimizes the system la-
Figure 14: Plot of supply voltage
, control signal CONT IN, and
inductor current for the transient time period for a step change in
from 20 kHz to 40 MHz.
tency. The Watkins-Johnson converter is shown to be well suited
for closed loop delay-line regulation. The design criteria for the
selection of the converter components is straightforward and is
described. A chip including the AVS controller and a small test
application has been fabricated in a standard CMOS process.
Experimental results demonstrate operation over the clock fre-quency range from 10KHz to 20MHz, and a 12 s transient re-
sponse for a step change in system clock frequency from 10 kHz
to 20 Mhz.
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