supported by GSI, BMBF (06FY9099I), EU (FP7-WP26)
A Prototype Readout System for the MVD of the CBM ExperimentChristoph Schrader for the CBM-MVD Collaboration
2011 2013R/O V 1 R/O V 2
The LVDS signals will be replaced by optical transmission for R/O V2
station @5cm @10cm
# sensors (MIMOSIS) 40 120
data rate [Gbit/s] 40 120
compressed data rate [Gbit/s] for Au-Au @ 10AGeV
12 8
compressed data rate [Gbit/s] for p-Au @ 30GeV
14 20
conservative approach (based on LVDS signals) to test the FEE full readout concept based on an available
sensor MIMOSA-26 (IPHC Strasbourg) full bandwidth and scalability
optical readout dedicated CBM sensor
(MIMOSIS)
The read-out system for the Microvertexdetector (MVD) has to be configured accordingto the demanding requirements of the CBM Experiment. For the first application at SIS-100 a prototype based on Monolithic Active Pixel Sensors (MAPS) is set-up. The read-out concept is intended to provide a flexible software and hardware solution. The development comprises two versions V1 and V2.
Front-end Board (FEB) one FPC is plugged in one FEB FEB’s are arranged in a queue passive board for radiation
tolerance (up to 10 MRad) passive power filters
R/O V1
flex-print cable (FPC) connects 2 MIMOSA-26 sensors cooper based
material budget 0.095 % X0
MIMOSA-26 pixels: 1152 x 576 readout time:115.2 µs features: CDS, discrimination, zero-suppression limitation: 570 hit/matrix data rate: 160 Mbit/s
Converter Board (CVB) houses one FEB via LVDS signals (max. 2 m) monitors (6 channel ADC)
o sensor temperature o sensor powering
sensor powering with latch-up protection:
o < 1 µs detection and reaction o switch to disconnect the sensors
sensor
MUX...
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1Gbit/s
fibers
10b/8bde-
coding
8b/10ben-
coding
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FEB Converter Board Readout Controller Board
~ 2m >>
FP
GA
Readout Controller Board (ROC) data reduction time stamping sensor control system
PCI Express cardPC interface for slow control 4 x 3 Gbit/s optical links usable with TrbNet
slow control protocol (TrbNet) used in running experiments (HADES) data acquisition and slow control in one optical link error detection
station @5cm @10cm
# of input channels 40 120# number of ROCs 8 15max. output data rate [Gbit/s] 48 90
readout capacity load [%] (Au-Au @ 10AGeV) 32 11
readout capacity load [%] (p-Au @ 30GeV) 36 28
~ factor 3for safety
revision for R/O V2 based on CBMNet for data transfer and TrbNet (HADES) for slow control one FPGA 8x optical input links (1 Gbit/s) 2x optical output links (3 Gbit/s), CBMNet 1x optical slow control link, TrbNet
R/O V2
one FPC connects up to 10 MIMOSIS sensors aluminium based
material budget 0.032 % X0
MIMOSISreadout time: 30 µssame features as MIMOSA-26with no hit limitationdata rate: max. 800 Mbit/s
mean 300 Mbit/sR/O V2The FEB will be replaced by an FPC based on aluminum to reduce the material budget (~0.032 % X0)
DPG Münster, 2011HK 39.49
Status: The boards were submitted for production, are assembled and currently under test. In parallel to the hardware developments, readout and slow control algorithms for the FPGA firmware were successfully developed.
sensor sensor
FEB
Contact: [email protected]
