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SP605 GTP IBERT Design Creation
January 2010
© Copyright 2009, 2010 Xilinx XTP066
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SP605 IBERT Overview
Xilinx SP605 BoardSoftware RequirementsSetup for the SP605 IBERT Designs– Running the SP605 IBERT Design
SP605 IBERT Design Creation – Create IBERT CORE Generator Project– Create IBERT Design– Create IBERT ACE File
References
Note: This Presentation applies to the SP605
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SP605 IBERT Overview
Description– The LogiCORE Integrated Bit Error Ratio (IBERT) core is used to create a
pattern generation and verification design to exercise the Spartan-6 GTP transceivers. A graphical user interface is provided through the IBERT console window of the ChipScope Pro Analyzer
Reference Design IP– LogiCORE IBERT Example Designs
• PCIe (1), SMA (1), SFP (1), FMC_LPC (1)• ChipScope Pro Analyzer• ChipScope Pro 11.4 Software and Cores User Guide (UG029)
Note: Presentation applies to the SP605
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Xilinx SP605 Board
Note: Presentation applies to the SP605
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Software Requirements
Xilinx ISE 11.4 software
Note: Presentation applies to the SP605
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Software Requirements
Spartan-6 GTP ACE Files – ACE files for Spartan-6 GTP Designs requires an environment variable set– Set XIL_CONFIG_USE_ISC_DISABLE=true – See AR 33575
Note: Presentation applies to the SP605
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ChipScope Pro Software Requirement
Xilinx ChipScope Pro 11.4 software
Note: Presentation applies to the SP605
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Setup for the SP605 IBERT Designs
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Setup for the SP605 IBERT Designs
Unzip the rdf0036.zip file to your C:\ drive– https://secure.xilinx.com/webreg/clickthrough.do?cid=140337
Note: Presentation applies to the SP605
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Setup for the SP605 IBERT Designs
Connect a USB Type-A to Mini-B cable to the USB JTAG connector on the SP605 board– Connect this cable
to your PC
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Setup for the SP605 IBERT Designs
SMA Cable– www.flrst.com– P/N: ASPI-024-ASPI-S402
Note: Presentation applies to the SP605
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Setup for the SP605 IBERT Designs
Using the SMA cables:– Connect J32 to J34
Note: Presentation applies to the SP605
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Setup for the SP605 IBERT Designs
Using the SMA cables:– Connect J33 to J35
Note: Presentation applies to the SP605
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Setup for the SP605 IBERT Designs
Connect Optical Loopback Adapter – www.molex.com– SFP Loopback Adapter,
3.5 db Attenuation – Part # 74720-0501– Alternatively, use an
SFP transceiver with a fiber optic cable
Insert into the SFP Connector on the SP605 boardConnect the SP605 Power and turn the SP605 on
Note: Presentation applies to the SP605
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Running the SP605 IBERT Design
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Running the SP605 IBERT Design
Open ChipScope Pro and click on the Open Cable Button (1) Click OK (2)
Note: Presentation applies to the SP605
1
2
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Running the SP605 IBERT Design
Select Device → DEV:1 MyDevice1 (XC6SLX45T) → Configure…Select <Design Path>\sp605_ibert.bit
Note: Presentation applies to the SP605
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Running the SP605 IBERT Design
Select File → Open Project…Select <Design Path>\sp605_ibert.cpj
Note: Presentation applies to the SP605
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Running the SP605 IBERT Design
Click Yes on this Dialog
Note: Presentation applies to the SP605
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The line rate is 2.5 Gbps for all four GTPs (1)Near-End PMA is selected for the PCIe and FMC GTPs (2)
Running the SP605 IBERT Design
1
22
Note: Left to right: PCIe, SMA, SFP, FMC_LPC
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Running the SP605 IBERT Design
TX Diff Output Swing = 695 mV (0100)TX Pre-emphasis = 1.7 dB (010)
Note: Presentation applies to the SP605
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Running the SP605 IBERT Design
TX/RX Data Patterns are set to PRBS 7-bit (1)Click BERT Reset buttons (2)
Note: Presentation applies to the SP605
1
2
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Running the SP605 IBERT Design
View the RX Bit Error Count (1)
Note: Presentation applies to the SP605
1
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SP605 IBERT Design Creation
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Create IBERT CORE Generator Project
Open the CORE GeneratorStart → All Programs → Xilinx ISE Design Suite 11 →ISE → Accessories → CORE Generator
Create a new project; select File → New Project
Note: Presentation applies to the SP605
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Create IBERT CORE Generator Project
Create a project directory: sp605_ibertName the project: sp605_ibert.cgpThe Project options will appearSet the Part (as seen here):– Family: Spartan6– Device: xc6slx45t– Package: fgg484– Speed Grade: -3
Note: Presentation applies to the SP605
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Create IBERT CORE Generator Project
Select GenerationSet the Design Entry to VerilogClick OK
Note: Presentation applies to the SP605
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Create IBERT Design
Right click on the IBERT Spartan6 GTP (ChipScope Pro - IBERT, Version 2.00a– Select Customize
Note: Presentation applies to the SP605
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Create IBERT Design
Make the following settings:– Component name:
sp605_ibert– Set the number of
Line Rates: 1– Set the line rate to
Max Rate: 2.5 Gbps– Set the RefClk
frequency to: 125 MHz
Click Next
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Create IBERT Design
Select both GTPs:– GTPA_DUAL_X1_Y0– GTPA_DUAL_X0_Y0
Connect both Refclks to:– REFCLK0 X1Y0– This connects both
GTPs to the 125 MHz SFP Clock
Click Next
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Create IBERT Design
Leave this screen as is– Click Next
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Create IBERT Design
Select the following settings:– Use External Clock
source– Frequency (MHz):
200– Location: K21
Click Next
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Create IBERT Design
Click Generate
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Create IBERT Design
After the IBERT core finishes generating, click Close on the Datasheet window
Note: Presentation applies to the SP605
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Create IBERT ACE File (Optional)
Type these commands in a windows command shell:cd C:\sp605_ibert\ready_for_downloadmake_ace.bat
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References
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References
ChipScope Pro– ChipScope Pro 11.1 ChipScope Pro Software and Cores User Guide
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/chipscope_pro_sw_cores_ug029.pdf
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Documentation
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Documentation
Spartan-6– Spartan-6 FPGA Family
http://www.xilinx.com/products/spartan6/index.htm
SP605 Documentation– Spartan-6 FPGA SP605 Evaluation Kit
http://www.xilinx.com/products/devkits/EK-S6-SP605-G.htm– SP605 Hardware User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug526.pdf– SP605 Reference Design User Guide
http://www.xilinx.com/support/documentation/boards_and_kits/ug527.pdf