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1
Smartphone Market Driving 7nm & 5nm
Node 3-D Devices and Stacked Devices
John Ogawa Borland
J.O.B. Technologies
Aiea, Hawaii
www.job-technologies.com
July 14, 2017
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Outline
• Introduction: Smartphone Market Driver for 3-D
– 2016 Semiconductor Market and Applications• Computation, Mobile, Automotive, Medical and IoT
– Smartphone device technology• Application Processor 2-D planar (A8: 20nm node)3-D FinFET (A9: 14/16nm node)
• Rear facing camera (8Mp12Mp16Mp) 3-D TSV3-D Monolithic (Direct Wafer Bonding)
• Flash memory 2-D 13nm 3-D 40nm with 48-layers
• 3-D Bulk FinFET Transistor Formation
• 3-D FinFET High Mobility Channel Formation
• 3-D Gate-All-Around Nanowire Transistor Formation for sub-5nm node
or Monolithic 3-D stacking
• More-Than-Moore 3-D Stacked Devices
• Summary
2
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3
Total IC Market
2014=$340B
2015=$333B
2016=$343B
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J.O.B. Technologies (Strategic
Marketing, Sales &
Technology)
4Nov 9, 2016
403M std phones
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5
Smartphone as new technology driver– 2011: iPhone 4s A5 and Galaxy S245nm (2007) 4 years old technology
– 2012: iPhone 5 A6 and Galaxy S332nm (2009) 3 years old tech
– 2013: April Galaxy S4 and Sept iPhone 5s/5c A728nm (2010) 3 years old tech
– 2014: April Galaxy S5 and Sept iPhone 6/6+ A820/22nm (2012) 2 years old tech
– 2015: April Galaxy S6 and Sept iPhone 6s/6s+ A914/16nm 3-D FinFET (2014) most
advanced technology node
– 2016: April Galaxy S7 and Sept iPhone 7/7+ A1016nm (2014)
– 2017: April Galaxy S8 and Sept iPhone 7s/7s+ A1110nm (2016) most advanced
technology node
A9 2015 14/16nm
A10 2016 3.3B 16nm FF+
A11 2017 10nm
20162015
iPhone 6s iPhone 7
iPhone 6s+ iPhone 7+
2011
2012
2013
2014
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& msec Flash
SF-stressor
Intel, Sept. 6, 2011
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
45nm 32nm 28nm 20nm 14/16nm 16nm 10nm
Everyone Equal
at 14nm FinFET?
IBM: 1980s1999 (1um180nm)
Intel: 1999Aug-2014 (180nm14nm)
Samsung & TSMC: Oct-2016 (10nm?)
6
6
10nm
10nm
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March 28, 2017: Intel Technology and Manufacturing Day
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Samsung Galaxy S6J.O.B. Technologies (Strategic
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8
Dick James, Chipworks, April 6, 2015
Battery
ePOP
S6 S5
App. Processor Samsung Qualcomn
Rear Camera 16Mp Sony 16Mp Samsung
Front Camera 5Mp Samsung 5Mp Samsung
Flash 64Gb Samsung 64Gb Samsung
DRAM 3Gb Samsung
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Samsung Galaxy S7 SmartphoneMarch 2, 2016
S7 S6
App. Processor Qualcomn Samsung
Rear Camera 12Mp Sony 16Mp Sony
Front Camera 5Mp Samsung 5Mp Samsung
Flash 32Gb Samsung+microSD 64Gb Samsung
DRAM 4Gb Hynix 3Gb Samsung
Water Proof 5feet 30 minutes No
14nm FinFET
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Kagawa et al., Sony, IEDM-2016 paper 8.4
Samsung Galaxy S7
March 2016 Sony
12Mp Rear Camera
3rd-gen Hybrid DBI
wafer to wafer
bonding
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Qualcomm Snapdragon 835
10nm FinFET
Sony 8Mp Front facing Selfie Camera &
Iris scanner
Sony 12Mp Rear facing Camera with
DBI (direct bond interconnect)
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iPhone 6s
2015
12Mp
Thick SOI
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Apple iPhone 6s & 6s+Sept 9, 2015
TSMC 16nmFF+
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Intel Inside!
Intel Mobile Cellular Platform
-Two RF transceivers
-Baseband modem
-(RF) power management IC
Samsung 2Gb LPDDR4 DRAM
Flash Memory options
SK Hynix 128Gb (15nm)
Toshiba 128Gb (15nm)
Toshiba 48-layer 3-D NAND 256Gb
Battery 1960mAh (7.45Wh)
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Toshiba 256Gb-Flash
48-layer 3-D NAND
Sony 2nd-generation
TSV 3-D stack
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Sony’s 3-Layer 20Mp CIS
Dick James, May 2017
Sony’s Future 4-Layer CIS
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Best Buy PNY 256Gb=$49.99
$0.195/Gb
Techinsights Nov 2016
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Outline
• Introduction: Smartphone Market Driver for 3-D
• 3-D Bulk FinFET Transistor Formation
– 22nm14/16nm10nm7nm5nm
• 3-D FinFET High Mobility Channel Formation
• 3-D Gate-All-Around Nanowire Transistor Formation for sub-5nm node
or Monolithic 3-D stacking
• Summary
18
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52 Degree Tilt
pMOS nMOS
52 Degree Tilt
22 atoms~7nm
+7-9 degree=~60 degree tilt!
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Prof. Ogura, Meiji Univ. 3/1/16
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14/16nm
FinFET by
Intel, Samsung
& TSMC
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VLSI-2016 paper 9.1
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IEDM-2016 paper 2.6
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24VLSI-2016 paper 2.1
µh=220
µe=170
10nm FinFET will
stay with bulk Si-
channels and
eS/D-stressors. No
SiGe channel.
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VLSI-2017
30% 35%
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Dick James, Chipworks, Semicon/West 2015 AVS-WCJUG
Meeting
Dual Width
FinFET at
14nm node
2 generations
ahead of
Samsung (7nm)
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From Dick James
March 28, 2017: Intel
Technology and
Manufacturing Day
NMOS only,
No Image of PMOS
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Kennel, Intel, IEEE/RTP 2006
Rosseel et al., IMEC/ASM, ECS Oct 2016
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VLSI Sym June 2016
Paper 7.5: UMC/AMAT ultralow p+ SiGe contact resistivity (5.9E-9Ω-cm2)
Paper 7.1: IMEC/AMAT/Samsung ultralow resistivity contacts (2.1E-9Ω-
cm2)
Paper 7.3: AMAT 7nm node ultralow n+ contact resistivity (<1.0E-9Ω-cm2)
Paper 7.4: GF/IBM canceled: Sub-2x10-9 Ω-cm2 N- and P-Contact
Resistivity with Si:P and Ge:Ga Metastable Alloys for FinFET CMOS
Technology
SiP =2E21/cm3 + Ge-PAI=2.1x10-9 Ω-cm2
70%-SiGeB + Ge-PAI= 2.1x10-9 Ω-cm2Pre-contact PAI
DSA versus nsec laser annealing
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IEDM-2016 paper 17.2
B=2E19/cm3
Group III-Me=1E21/cm3
paper 2.7
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31IEDM-2016 paper 17.2
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IEDM-2016 paper 17.4
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IWJT-2017
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VLSI-2017
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35VLSI-2017
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VLSI-2017
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VLSI-2017
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Ge: Trumbore, Bell Labs, 1959
Ga
Al
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Sept IIT-2016 Ga
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Solid Solubility Limited Dopant
Activation of Group III (B, Ga & In) in
Ge Targeting sub-7nm Node Low p+
Contact Resistance IWJT June 2, 2017
John Borland, J.O.B. Technologies, Aiea, HI
Yao-Jen Lee, NDL, Hsinchu, Taiwan
Shang-Shiun Chuang & Tseung-Yuen Tseng, National Chiao Tung University, Hsinchu,
Taiwan
Chee-Wee Liu, National Taiwan University, Taipei, Taiwan
Karim Huet, LASSE/Screen, France
Gary Goodman & John Marino, EAG Laboratories, East Windsor, NJ
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55OC/10 sec RTA Anneal SIMS
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10%-Si
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308nm Laser Anneal SIMS (1.7J/cm2)
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10%-Si
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Outline
• Introduction: Smartphone Market Driver for 3-D
• 3-D Bulk FinFET Transistor Formation
• 3-D FinFET High Mobility Channel Formation (7nm)
– Strain-Si (tensile or compressive stress)
– Strain-SiGe (tensile or compressive stress)
– Strain-Ge (tensile or compressive stress)
• 3-D Gate-All-Around Nanowire Transistor Formation for sub-5nm node
or Monolithic 3-D stacking
• Summary
44
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GF/IBM/Samsung IEDM-2016 paper 2.7 on 7nm
FinFET with sSi and sSiGe high mobility channels
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IEDM-2016 paper 2.7
Thick 25%-SiGe SRB (strain relaxed
buffer) epilayer on Si with multi-step
4 layer SRB. SiGe TDD (threading
dislocation density) defect level from
E8/cm2 to E4/cm2 and the 1.6GPa
tensile sSi (t-Si) channel electron
mobility boost is 40% up to 100%
while the -1.6GPa compressive 50%-
sSiGe (c-SiGe) channel hole mobility
boost varies from 10% up to 60%.
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IEDM-2016 paper 28.1
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Borland et al., ECS Oct 2004
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0.0J/cm2 1.0J/cm2 2.5J/cm2
0.001
0.01
0.1
1
10
100
1.00E+17
1.00E+18
1.00E+19
1.00E+20
1.00E+21
1.00E+22
0 50 100 150 200 250
Ge
Arb
. U
nit
s
B, C
, O
Co
nc
en
tra
tio
n (
at/
cm
3)
Depth (nm)
12C
16O
11B+28Si
28Si+74Ge
0.0001
0.001
0.01
0.1
1
10
100
1.00E+17
1.00E+18
1.00E+19
1.00E+20
1.00E+21
1.00E+22
1.00E+23
0 100 200
Ge A
rb.
Un
its
B, C
, O
Co
ncen
trati
on
(at/
cm
3)
Depth (nm)
12C
16O
11B+28Si
28Si+74Ge
0.0001
0.001
0.01
0.1
1
10
100
1.00E+17
1.00E+18
1.00E+19
1.00E+20
1.00E+21
1.00E+22
1.00E+23
0 50 100 150 200 250
Ge A
rb u
nit
s
B, C
, O
Co
ncen
trati
on
(at/
cm
3)
Depth (nm)
12C
18O
11B+28Si
28Si+74Ge
Borland et al., JOB-Tech/Micron/Innovavent/Excico/EAG/CNSE-SUNNY/KT/ALP, IWJT-2013, paper S4-4, p.49
55%-aSiGe 25% LPE-SiGe40%-polySiGe
Ge-plasma Implantation
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0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
Mo
bilit
y (
cm
2V
-1s
-1)
Depth (Å)
Mobility JA14ED12-1
Drift
0
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160
170
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
Depth (Å)
Ge=1E17/cm2 + BH=4E16/cm2
Ge=1E16/cm2 + BH=4E15/cm2
>4x hole-mobility!
ALP Hall Analysis of 308nmSlot#14:Ge=1E16+B=4E15
Slot#18: Ge=1E17+B=4E16
Ge=0%+BH=4E16/cm2
Borland et al., JOB-Tech/Micron/Innovavent/Excico/EAG/CNSE-
SUNNY/KT/ALP, IWJT-2013, paper S4-4, p.49
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Borland et al., IIT-2016, Sept 29, 2016
0
200
400
600
800
1000
1200
1400
0 500 1000 1500 2000cm
2/V
-s
Depth (A)
Layer Mobility
65.0 65.5 66.0 66.5 67.010
2
103
104
105
106
107
Angle (2)
Inte
nsi
ty (
cou
nts
/sec
)
1
2
3
4
5
6
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Outline• Introduction: Smartphone Market Driver for 3-D
• 3-D Bulk FinFET Transistor Formation
• 3-D FinFET High Mobility Channel Formation
• 3-D Gate-All-Around Nanowire Transistor Formation for sub-5nm node
or Monolithic 3-D stacking
– Si-nanowire
– Ge-nanowire
– CoolCube 3-D stacking
• Summary
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VLSI-2016 paper 15.1
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VLSI-2017
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VLSI-2017
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Summary: Smartphone the technology driver for 3-D
More Moore and More Than Moore in this Decade!
• March 2017 Samsung Galaxy S8 using 10nm 3-D FinFET, 12M pixel 3rd generation
hybrid wafer bonding 3-D stacked backside CMOS image sensor camera from Sony
and thin 3-D ePoP (embedded package on package).
• Sept 2016 Apple iPhone 7 A10-AP uses 3-D FinFET 16nm from TSMC, 12M pixel 2nd
generation 3-D stacked backside CMOS image sensor camera from Sony and
256Gb 48-layer 3-D NAND Flash memory from Toshiba.
• 10nm node production started in Oct-2016 at Samsung and TSMC for 2017
smartphone market but Intel delay to March 2017, industry focus is lower contact
resistance (Rc) with slight channel mobility boost with S/D stressor.
• 7nm node in 2018/19 and localized high mobility tensile and compressive strain
channel with the end of S/D stressor to improve Rc with S/D rap-around contacts.
• 5nm node in 2020/21 will still be FinFET
• Sub-5nm will be Si or Ge GAA nano-wire, GAA nano-sheet or 3-D stack transistor.
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